KR100364845B1 - Leadframe and molding die of semiconductor package - Google Patents

Leadframe and molding die of semiconductor package Download PDF

Info

Publication number
KR100364845B1
KR100364845B1 KR1020010018336A KR20010018336A KR100364845B1 KR 100364845 B1 KR100364845 B1 KR 100364845B1 KR 1020010018336 A KR1020010018336 A KR 1020010018336A KR 20010018336 A KR20010018336 A KR 20010018336A KR 100364845 B1 KR100364845 B1 KR 100364845B1
Authority
KR
South Korea
Prior art keywords
leadframe
molding die
molding
semiconductor package
groove
Prior art date
Application number
KR1020010018336A
Other languages
Korean (ko)
Inventor
Jong Chul Hong
Eun Deok Kim
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Priority to KR1020010018336A priority Critical patent/KR100364845B1/en
Priority to US09/998,844 priority patent/US6605865B2/en
Application granted granted Critical
Publication of KR100364845B1 publication Critical patent/KR100364845B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A leadframe and a molding die of a semiconductor package is provided to prevent a chip-out at an edge of the semiconductor package or a crack on the outer surface of the package by forming a step in a lead of a micro leadframe or forming a mold reinforcing groove in an upper molding die of the molding die. CONSTITUTION: A semiconductor chip(11) is installed in the leadframe(120). A wire(13) connecting the semiconductor chip with leads(12) is installed in the leadframe. A molding groove(32a) for molding the upper surface of the leadframe is formed in the upper molding die(32). A lower molding die(34) supports the back surface of the leadframe. The mold reinforcing groove(32b) extends to the outer circumference of the molding groove, having a depth smaller than a vertical depth of at least the molding groove.
KR1020010018336A 2001-03-19 2001-04-06 Leadframe and molding die of semiconductor package KR100364845B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020010018336A KR100364845B1 (en) 2001-04-06 2001-04-06 Leadframe and molding die of semiconductor package
US09/998,844 US6605865B2 (en) 2001-03-19 2001-10-19 Semiconductor package with optimized leadframe bonding strength

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010018336A KR100364845B1 (en) 2001-04-06 2001-04-06 Leadframe and molding die of semiconductor package

Publications (1)

Publication Number Publication Date
KR100364845B1 true KR100364845B1 (en) 2002-12-16

Family

ID=37490986

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010018336A KR100364845B1 (en) 2001-03-19 2001-04-06 Leadframe and molding die of semiconductor package

Country Status (1)

Country Link
KR (1) KR100364845B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701402B1 (en) * 2001-03-19 2007-03-28 앰코 테크놀로지 코리아 주식회사 Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701402B1 (en) * 2001-03-19 2007-03-28 앰코 테크놀로지 코리아 주식회사 Semiconductor package

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