KR100364423B1 - Pumping voltage supply circuit - Google Patents

Abstract

The present invention relates to a pumping voltage supply circuit. In particular, an object of the present invention is to supply a pumping voltage to a word line during a read operation so that the selected cell is turned on during a low voltage operation to enable low power and low voltage operation. . According to an exemplary embodiment of the present invention, a word line decoder 430 for selecting a word line of a cell array 440 and a bit for selecting a bit line of the cell array 440 and outputting data of the corresponding bit line The line decoder 450 compares the read signal READ with the data DATA of the bit line decoder 450 to output a logic level data OUTPUT, and a power supply constant. A low voltage detector 410 outputs a logic level signal LVON high when the level is below the level, and a low level when the signal level is higher than the predetermined level. A low voltage detector 410 outputs a low level when the output signal LVON of the low voltage detector 410 is low. When the voltage VP is supplied to the word line decoder 430 and the output signal LVON is high, the pumping voltage VP = 2VDD− is applied to the word line decoder 430 while the read signal READ is active high. It is characterized by consisting of a power pump 420 for supplying Vt).

Description

Pumping voltage supply circuit {PUMPING VOLTAGE SUPPLY CIRCUIT}

The present invention relates to EPROM, and more particularly to a pumping voltage supply circuit.

1 is a block diagram showing a conventional epirome, as shown therein, a cell array 120 for storing data, a word line decoder 110 for selecting a word line of the cell array 120, A bit line decoder 130 that selects a bit line of the cell array 120 and outputs data of the corresponding bit line, data DATA of the bit line decoder 130 and the cell array 120 ) And a sense amplifier 140 for comparing the reference value REF at the output signal and outputting the data OUTPUT.

As shown in the block diagram of FIG. 2, the sense amplifier 140 may level up / down the data REF of the reference cell and level up / down the data DATA of the data cell. A level shifter 230 for supplying current to the data of the reference cell and the data of the data cell while the read signal READ is active high. And a differential amplifier 220 for outputting data OUTPUT by comparing the output data of the level shifters 210 and 230.

The data cell is composed of a blank cell and a programmed cell, and the reference cell is configured identically to the blank cell.

Referring to the operation of the prior art as follows.

When the read mode of the EPROM starts, the word line decoder 110 selects one of a plurality of word lines included in the cell array 120, and the bit line decoder 130 is provided in the cell array 120. One of the plurality of pairs of bit lines is selected.

Accordingly, the sense amplifier 140 inputs the reference value REF in the cell array 120 and the data DATA in the bit line decoder 130 as inputs while the read signal READ is active at high VDD. Each current is compared and a logic high or low signal is output according to the comparison result.

For example, if the data DATA is blank, the sense amplifier 140 increases the level of the reference value REF by using the level shifter 210 and the level shifter 230 by using the level shifter 230. DATA) level is lowered.

At this time, the current sources 240 and 250 supply current to the reference value REF and the data DATA while the read signal READ is active high.

Accordingly, the differential amplifier 220 outputs the low signal OUTPUT by comparing the data shifted with the reference value REF and the level shifted reference value as shown in FIG. 3.

That is, the sense amplifier 140 outputs a low signal when the data DATA is blank and, conversely, outputs a high signal when the data DATA is programmed.

However, the conventional technique consumes a lot of current by applying a current to the reference cell and the data cell and compares the difference, and the operating voltage is lowered (less than 2V). There is a problem that is so small that the differential amplifier cannot be driven.

That is, it is difficult to implement the operation of 2V or less with the conventional technology.

here, There are two main reasons for the decrease.

1. This is because both the data level and the reference value level are lowered due to structural problems caused by the level shifters 210 and 230.

2. The gate of the cell is not sufficiently decoded by the wordline decoder 110.

This problem can be solved by lowering the threshold voltage of the cell, but it is difficult because the process may cause a problem when writing data.

Accordingly, the present invention provides a low voltage operation in which the selected cell is turned on even during low voltage operation by supplying a pumping voltage to a word line during read operation to apply the gate to the cell gate in order to improve the conventional problem. The purpose is to provide a circuit.

1 is a block diagram showing a conventional epirome.

2 is a block diagram of a sense amplifier in FIG.

FIG. 3 is an exemplary diagram illustrating a level difference between a reference value and cell data in FIG. 2; FIG.

4 is a block diagram of an epirome for an embodiment of the present invention.

5 is a circuit diagram of the power pump in FIG.

FIG. 6 is a waveform diagram showing a relationship between a pumping voltage and a read signal in FIG. 4; FIG.

7 is a circuit diagram of a sense amplifier in FIG.

Explanation of symbols on the main parts of the drawings

410: low voltage detector 420: power pump

430: word line decoder 440: cell array

450: bit line decoder 460: sense amplifier

In order to achieve the above object, the present invention provides an EPROM having a cell array, a word line decoder, and a bit line decoder. A low voltage detector for outputting a logic low signal if it is abnormal, a power pump for supplying a pumping voltage to the wordline decoder while the read signal is active when the low voltage detector outputs a logic high signal, and the bit while the read signal is active And a sense amplifier for amplifying the data of the cell array input through the line decoder and outputting the data as logic level data.

Hereinafter, the present invention will be described in detail with reference to the drawings.

4 is a block diagram of a device showing an embodiment of the present invention, as shown therein, a cell array 440 for storing data and a word line decoder 430 for selecting a word line of the cell array 440. ), A bit line decoder 450 that selects a bit line of the cell array 440 and outputs data of the corresponding bit line, a read signal READ and data of the bit line decoder 450. A sense amplifier 460 that compares (DATA) and outputs logic level data OUTPUT, and outputs a logic level signal LVON high when the operating power is below a certain level, and low when the level is above a certain level. When the low voltage detector 410 and the output signal LVON of the low voltage detector 410 are low, a voltage of 'VDD' level is supplied to the word line decoder 430 and the output of the low voltage detector 410 is output. When the signal LVON is high, the read signal READ goes high. During beuin constitute the power pump 420 to supply a pumping voltage (VP = 2VDD-Vt) to the word line decoder (430).

As shown in the circuit diagram of FIG. 5, the power pump 420 logically multiplies the read signal READ by the output signal LVON of the low voltage detector 410 to enable the signal. ) And an output signal (and output signal) of the AND gate 510. Is low when the switch 550 is turned on to output the voltage VP = VDD to the word line decoder 430, and the capacitor 540 charges the voltage VDD output through the switch 550; Output signal of the AND gate 510 ( Is high, the output signal of the high level such that the pumped voltage (VP = 2VDD-Vt) is output from the condenser 540. Inverters 520 and 530 which inverts the sequential order so that the (-) pole potential of the condenser 540 is at the 'VDD' level, thereby pumping the (+) pole potential of the condenser 540 to the '2VDD' level. ).

As illustrated in the circuit diagram of FIG. 7, the sense amplifier 460 includes a gate of an NMOS transistor HN1 having a drain connected to a bit line decoder 450 and a PMOS transistor P1 having a source connected to a voltage VDD. The read signal READ is connected to the gate of NMOS transistor N1 having the gate of P4 and the ground grounded, and the source of NMOS transistor HN1 is connected to the drain and source of PMOS transistor P4. It is commonly connected to the gate of the PMOS transistor P2 and the gate and the drain of the PMOS transistor P3 to which the VDD is connected, and the drain of the PMOS transistor P1 and P2 and the drain of the NMOS transistor N1. Are connected in common to the input terminal of the inverter 710 and configured to output a logic signal OUTPUT from the inverter 710.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

When the EPROM is in operation, the low voltage detector 410 checks the operating power of the pyrom, and outputs a logic high (LVON) when the operating power is below a certain level. Output

If the detection level is 2.5V, the output signal LVON of the low voltage detector 410 goes low when VDD> 2.5V. On the contrary, the output signal LVON goes high when VDD <2.5V.

At this time, the power pump 420 determines whether to output the pumping voltage to the word line decoder 430 by inputting the output signal LVON of the low voltage detector 410. When the output signal LVON is low, the voltage ( VP = VDD) outputs no power pumping. When the output signal LVON is high, the pumping voltage VP = 2VDD-Vt is only shown in FIG. 6B only while the read signal READ remains high as shown in FIG. 6A. )

That is, when the output signal LVON of the low voltage detector 410 is low, the power pump 420 outputs the output signal of the AND gate 510 regardless of the level of the read signal READ. Since the switch 550 is turned on and the voltage VDD is charged in the capacitor 540, the output voltage VP = VDD is supplied to the word line decoder 430.

If the output signal LVON of the low voltage detector 410 is high and the read signal READ is high, the output signal of the AND gate 510 is high. ) Becomes high, the switch 550 is turned off, and the electric potential charged in the condenser 540 is maintained.

Accordingly, the output signal of the AND gate 510 ( ) Is sequentially reversed in the inverters 520 and 530 so that the negative-pole potential of the capacitor 540 becomes 'VDD' at the ground level, so that the positive-pole potential of the capacitor 540 is '2VDD'. Pumped into.

However, in reality, the pumping voltage VP excluding the threshold value Vt of the switch 550 is supplied to the word line decoder 430.

For example, if VDD = 1.5V and Vt = 0.7V, then VP = (2 * 1.5)-0.7 = 2.3V.

In this case, the word line decoder 430 selects one of a plurality of word lines included in the cell array 440 and the column decoder 450 enabled for the read signal READ is provided in the cell array 440. One of a plurality of pairs of bit lines is selected to output the data DATA selected from the cell array 440 to the sense amplifier 460.

Accordingly, the sense amplifier 460 amplifies and outputs data DATA of the cell array 440 input from the bit line decoder 450 while the read signal READ is active high.

That is, in the sense amplifier 460, when the read signal READ is low, the NMOS transistor HN1 and the PMOS transistor P2 are turned off, and the PMOS transistor P1 and P4 are turned on so that the node ND1 ( ND2) goes high.

Accordingly, the inverter 710 inverts the high signal of the node ND2 and outputs the output signal OUTOUT low.

On the contrary, when the read signal READ is active high, the NMOS transistors HN1 and N1 are turned on and the PMOS transistors P1 and P2 are turned off.

Accordingly, when the data in the cell array 440 is blank, the node ND1 becomes low, the PMOS transistors P2 and P3 are turned on, and the node ND2 becomes high. OUTPUT) will be output low.

That is, when the read signal READ is high, the PMOS transistor P1 is turned off, the PMOS transistor P2 is turned on, and when the NMOS transistor N1 is turned on, the PMOS transistor P2 and the NMOS transistor are turned on. The node ND2 is configured to be high by the turn-on resistance ratio of N1.

If the data in the cell array 440 is programmed data, the node ND1 becomes high and the node ND2 goes low, so the inverter 710 outputs the output signal OUTPUT high.

Accordingly, the present invention is to supply a sufficient voltage to the gate of the cell by the operation as described above to prevent the selected cell is not turned on during the low voltage operation.

As described in detail above, the present invention has the effect of enabling the low voltage operation by turning on the selected cell even during the low voltage operation by supplying a pumping voltage to the word line during the read operation to the gate of the cell.

In addition, the present invention does not require a reference cell, unlike the prior art, there is an effect that the circuit can be simplified and power consumption can be reduced.

Claims (4)

In a EPROM having a cell array, a word line decoder, and a bit line decoder, a low voltage detector outputting a logic high signal when the operating power is below a certain level, and outputting a logic low signal when the power supply is above a certain level. And a low voltage detector outputs a logic high signal to supply a pumping voltage to the wordline decoder while the read signal is active, and data of a cell array input through the bitline decoder while the read signal is active. And a sense amplifier configured to amplify and output the data as logic level data. The power pump of claim 1, wherein the power pump multiplies the read signal READ by the output signal LVON of the low voltage detector. ) And the output gate of the AND gate ( ) Is low, the switch outputs the voltage VP = VDD to the word line decoder, the capacitor charging the voltage VDD output through the switch, and the output signal of the AND gate. Is high, the output signal of the high level such that the pumped voltage (VP = 2VDD-Vt) is outputted from the capacitor. ) And the first and second inverters pumping the positive pole potential of the capacitor to the '2 VDD' level by sequentially inverting the negative pole potential of the capacitor to the 'VDD' level from the ground level. A pumping voltage supply circuit. 2. The pumping voltage supply circuit as claimed in claim 1, wherein the sense amplifier is configured to output data at a logic level in accordance with a blank or programmed data in the cell array while the read signal (READ) is high. 4. The sense amplifier of claim 1 or 3, wherein the sense amplifier comprises a gate of an NMOS transistor HN1 having a drain connected to a bit line decoder, a gate and a source of PMOS transistor P1 and P4 having a source connected to a voltage VDD. A common signal is connected to the gate of the NMOS transistor N1 having the ground connected thereto, and a source of the NMOS transistor HN1 is connected to a drain of the PMOS transistor P4 and a voltage VDD is connected to the source. A common connection is made between the gate of the MOS transistor P2, the gate and the drain of the PMOS transistor P3, and the drain of the PMOS transistors P1 and P2 and the drain of the NMOS transistor N1 are connected in common to each other. And a logic signal (OUTPUT) is output from the inverter by connecting to an input terminal.