KR100358410B1 - The direct current off-set control method and thereof system of A/D converter at Orthogonal Frequency Division Multiplexing system - Google Patents

Abstract

The present invention relates to a direct current offset control system on an orthogonal frequency division multiplexing system. Particularly, in the quadrature frequency division multiplexing system that reduces the hardware size of the A / D converter DC offset estimator by estimating the DC offset of the A / D converter by accumulating only the value corresponding to the DC component among the frequency domain signals acquired during the fast Fourier operation. A direct current offset control system.

In the conventional quadrature frequency division multiplexing system, the DC offset control system in the DC offset control system estimates the DC offset in the A / D converter only when accumulating all the received signals output when estimating the DC offset of the A / D converter in the time domain. On the other hand, in the present invention, the present invention provides an A / B that estimates a DC offset value by receiving only a DC component signal among frequency domain signals output from the fast Fourier transformer and frequency domain signals output from the fast Fourier transformer. D converter DC offset estimator provides DC offset control system that reduces hardware size of A / D converter DC offset estimator in conventional quadrature frequency division multiplexing system in N point fast Fourier transform.

Description

A direct current off-set control method and system of A / D converters in an orthogonal frequency division multiplexing system and the system thereof A / D converter at Orthogonal Frequency Division Multiplexing system

The present invention relates to a direct current offset control system on an orthogonal frequency division multiplexing system. Particularly, in the fast Fourier operation, DC is accumulated in the orthogonal frequency division multiplexing system which reduces the hardware size of the A / D DC offset estimator by estimating the DC offset of the A / D converter by accumulating only the value corresponding to the DC component among the acquired frequency domain signals. To an offset control system.

Orthogonal Frequency Division Multiplexing (hereinafter, referred to as OFDM) is a multi-carrier transmission scheme that efficiently uses bandwidth through superposition between orthogonal subcarrier spectrums. In contrast to the transmission, the OFDM converts the high-speed data into low-speed parallel data and transmits the data to reduce the interference of adjacent transmission symbols under the multipath channel, thereby easily performing the high-speed transmission.

However, when data is transmitted using OFDM, the DC value set in the analog to digital converter (hereinafter referred to as AD converter) of the OFDM is changed while a predetermined time elapses. A deviation of a constant DC value is added to the received signal. This is called a DC offset of the A / D converter.

Therefore, a system for estimating the DC offset of an A / D converter has been developed. For example, a method of estimating the offset of an A / D DC is accumulated by accumulating a signal in a time domain for a long time. I use it.

Hereinafter, the prior art will be described with reference to FIGS. 1A and 1B.

1A and 1B are structural diagrams illustrating a modem structure for estimating a DC offset using a transmitter and a receiver of a general orthogonal frequency division multiplexing system.

As shown in FIG. 1A, in order to modulate an orthogonal frequency division multiplexing signal (OFDM signal) into a radio frequency signal, an error correction encoder (FEC coder) 100 is not shown in FIG. A 1-bit signal input to the transmitter modem is received from the control layer and converted into a convolutional encoded signal and output.

Here, the 1-bit input signal is input in a packet unit including a training sequence signal and a plurality of data signals of a predetermined period.

The interleaver / mapper 102 receives a convolutional encoded signal output from the error correction coder 100 and has a BPSK (Q channel having an orthogonal component and a Q channel orthogonal). The signal is converted into a symbol signal represented by Binary Phase Shift Keying (QPK), Quadrature Amplitude Modulation (QPSK), 16 Quadrature Amplitude Modulation (16QAM), or 16 Quadrature Amplitude Modulation (64QAM).

The inverse fast Fourier transformer 104 receives a symbol signal output from the interleaver / mapper 102 and performs an inverse Fourier transform process, and then converts the signal into an orthogonal frequency division multiplexing (OFDM) signal.

The guard interval adder 106 receives an orthogonal frequency division multiplexing (OFDM) signal output from the inverse fast Fourier transformer 104 and converts the signal into a signal to which a guard interval is added.

The symbol wave shaper 108 receives a signal to which a guard section output from the guard section inserter 106 is added and converts the signal into a signal in which pulse shaping is performed in the time domain.

The digital-to-analog converter (D / A converter) 110 and 112 receives a signal in which pulse shaping is output from the symbol waveform shaper 108 and converts the signal into an analog signal.

The IQ modulation 114 receives an analog signal output from the D / A converters 110 and 112 and converts the analog signal into an IQ modulated signal.

Here, in the IQ modulation, a generation signal of the local oscillator 116 is used. The mixer 118 converts the IQ modulated signal output from the IQ modulator 114 into a radio frequency signal by using the generated signal of the local oscillator 120.

The high gain amplifier 122 receives a radio frequency signal output from the mixer 118, converts the radio frequency signal into an amplified radio frequency signal, and transmits the amplified radio frequency signal to the receiver through the transmitter antenna 124.

Here, the bit input signals, the convolutional coded signals, and the symbol signals, which are signals before being converted into orthogonal frequency division multiplexing (OFDM) signals, are frequency domain signals, orthogonal frequency division multiplexing (OFDM) signals, signals with guard intervals, and pulse shaping. The performed signal, analog signal, IQ modulated signal, and amplified radio frequency signal are signals in the time domain.

FIG. 1B is a block diagram illustrating the estimation of a DC offset of an A / D converter by accumulating a signal in a general orthogonal frequency division multiplexing signal and a signal in a time domain for a long time.

As shown in FIG. 1B, in order to estimate the offset of the A / D direct current (DC) by accumulating the radio frequency signals received in the time domain for a long time, the receiver antenna 126 is connected to the transmit antenna 124. Receives an amplified radio frequency signal that is a transmitted signal.

The low noise amplifier 128 converts the amplified radio frequency signal output from the receiver antenna 126 into an amplified radio frequency signal with minimal noise.

The mixer 130 converts the amplified radio frequency signal, which minimizes the generation of noise output from the low noise amplifier 128, into an intermediate frequency signal by using the generated signal of the local oscillator 132.

The auto gain control amplifier 134 adjusts the intermediate frequency signal gain output from the mixer 130 and then outputs the adjusted gain.

The IQ demodulator 136 converts an intermediate frequency signal whose gain is adjusted from the automatic gain control amplifier 134 into a baseband signal and outputs the converted base frequency signal.

The A / D converters 140 and 142 convert the baseband signals output from the IQ demodulator 136 into digital signals and output them.

The remove guard interval remover 146 converts the digital signal output from the analog-digital converters 140 and 142 into a digital signal from which the guard interval is removed and outputs the converted digital signal.

The fast Fourier transform 148 converts the digital signal from which the guard interval is removed from the remove guard interval 146 into a frequency domain signal and outputs the converted digital signal.

The demapper / deinterleaver 150 converts the frequency domain signal output from the fast Fourier transformer 148 into a soft bit signal and outputs the soft bit signal.

The error correction decoder 160 converts the soft bit signal output from the deinterleaver and the demapper 150 into a bit signal and transmits the bit signal to a MAC layer (not shown).

The A / D DC offset estimator 145 estimates the DC offset of the A / D converter by accumulating the digital signals, which are all received signals output in the time domain, output from the A / D converters 140 and 142.

However, in the conventional Orthogonal Frequency Division Multiplexing (OFDM) system, in the DC offset control method, when the DC offset of the A / D converter is estimated in the time domain, the DC offset of the A / D converter cannot be estimated until all received signals are accumulated. There is a problem in that the size of the accumulator is increased.

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art, and an object of the present invention is to accumulate only by estimating a DC offset by accumulating only a signal corresponding to a DC component in a signal in a frequency domain obtained by performing a fast Fourier transform (FFT). Minimize the size of the hardware.

As a technical idea for achieving the present invention, in order to estimate a DC offset using a signal corresponding to a direct current (DC) component among the frequency domain signals output from the fast Fourier transformer of the orthogonal frequency division multiplexing system,

An I-channel accumulator for receiving and accumulating a DC component signal having an in-phase component among the frequency domain signals output from the fast Fourier transformer and accumulating the DC offset of the A / D converter, and an orthogonal component among the frequency domain signals output from the fast Fourier transformer. A / D DC offset estimator configured to receive a DC component signal and accumulate the DC channel offset by accumulating the DC component signal, and output the DC offset estimation signal, and the DC output from the A / D DC offset estimator. Quadrature including a D / A converter that converts the offset estimation signal into an analog signal used for DC offset adjustment and an A / D converter that uses the analog signal output from the D / A converter for DC offset adjustment. We present a DC offset control system for an A / D converter on a frequency division multiplexing system.

1A and 1B are diagrams illustrating a modem structure for estimating a DC offset using a transmitter and a receiver in a general orthogonal frequency division multiplexing system.

FIG. 2 is a diagram illustrating a method of estimating a DC offset by accumulating only a signal corresponding to a DC component in a frequency domain using the A / D converter DC offset estimator of the present invention. FIG.

FIG. 3 is a detailed diagram illustrating the DC offset estimator of the A / D converter of FIG. 2. FIG.

<Code Description of Main Parts of Drawing>

100: error correction encoder 102: interleaver / mapper

104: reverse fast Fourier transducer 106: guard section inserter

108: symbol waveform forming machine 110,112,156,158: D / A converter

114: IQ modulator 116,120,132,138: local oscillator

118,130 Mixer 122: High Gain Amplifier

124: transmitter antenna 126: receiver antenna

128: low noise amplifier 134: automatic gain control amplifier

136: IQ demodulator 140,142: A / D converter

144: automatic frequency controller 146: guard section controller

148: Fast Fourier Converter 150: Deinterleaver / Demapper

145,152: A / D DC offset estimator 154: I channel accumulator

156: Q channel accumulator 160: error correction decoder

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention will be described in detail.

FIG. 2 is a diagram illustrating a method of estimating a DC offset by accumulating only a signal corresponding to a DC component in a frequency domain using the A / D DC offset estimator of the present invention.

The same components of the interaction of FIG. 1 will be discussed.

As shown in FIG. 2, the A / D DC offset estimator 152 and the D / A converters 156 and 158 are configured to estimate DC offsets by accumulating only signals corresponding to DC components in the frequency domain. .

The A / D converter DC offset estimator 152 estimates a DC offset value by receiving a DC component signal among frequency domain signals output from the fast Fourier converter 148. And outputs a DC offset estimation signal estimated with a DC offset value.

The D / A converters 156 and 158 convert the DC offset estimation signal output from the A / D DC offset estimator 152 into an analog signal used for DC offset adjustment to the A / D converters 140 and 142. Is configured to transmit.

The A / D converters 140 and 142 convert the DC signal into a digital signal whose DC offset is adjusted according to the analog signal used to adjust the DC offset received from the D / A converters 156 and 158. 144 to generate a clock to be used for the IQ demodulator 136.

FIG. 3 is a diagram illustrating in detail the A / D DC offset estimator of FIG. 2.

As shown in FIG. 3, the A / D DC offset estimator 145 includes an I channel accumulator 154 and a Q channel accumulator 156.

The I channel accumulator 154 receives and accumulates a DC component signal having an in-phase component output from the fast Fourier transformer 148 to estimate an A / D converter DC offset.

The Q channel accumulator 156 receives a DC component signal having an orthogonal component output from the fast Fourier transformer 148 and accumulates the A / D converter DC offset.

As described above, when the N point FFT is performed by measuring the DC offset using the signal in the frequency domain output from the fast Fourier transformer 148, compared to the structure of estimating the DC offset in the A / D converter in the time domain The accumulator size can be reduced to 1 / N.

As described above, the present invention accumulates only a signal corresponding to a DC component from a signal in a frequency domain obtained by performing a fast Fourier transform, and estimates a DC offset. In the division multiplexing system, the hardware size of the A / D DC offset estimator can be reduced by 1 / N.

Claims (2)

In the apparatus for estimating the DC offset in the orthogonal frequency division multiplexing system, An A / D DC offset estimator which outputs a DC offset estimation signal by estimating a DC offset value among the frequency domain signals output from the fast Fourier transformer; A D / A converter converting the DC offset estimation signal output from the A / D DC offset estimator into an analog signal used for DC offset adjustment and outputting the analog signal; A / D converter on an orthogonal frequency division multiplexing system, characterized in that it comprises an A / D converter for converting the analog signal used in the DC offset adjustment output from the D / A converter into an output signal which is a digital signal DC offset control system. The method according to claim 1, The A / D DC offset estimator is an I-channel accumulator for estimating the DC offset of the A / D converter by accumulating and receiving a DC component signal having an in-phase component output from a fast Fourier transformer; On the orthogonal frequency division multiplexing system, a Q channel accumulator for receiving and accumulating a DC component signal having an orthogonal component output from a fast Fourier transformer and accumulating the DC offset is calculated. DC offset control system of A / D converter.