KR100351979B1 - Memory unit cell circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory unit cell circuit, and in the related art, the dimensions of transistors, word lines, and bit lines constituting cells are rapidly decreasing according to the development of lithography technology. It should have sufficient capacitance, but due to the inherent properties of the material, it is difficult to reduce the density below a certain size, which makes it difficult to improve the density. Accordingly, the present invention provides a first NMOS transistor having a first word line connected to a gate, a first data line connected to a drain, a second NMOS connected to a second word line connected to a gate, and a second data line connected to a drain. By configuring an asymmetric capacitor connected between the transistor and the source of the first and second NMOS transistors, the charge of three states can be stored and read using one asymmetric capacitor, so that two states are stored in one capacitor. When the area of the cell capacitor is dominant compared to the existing memory cell, the information storage capability can be improved.

Description

Memory unit cell circuit {MEMORY UNIT CELL CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory unit cell circuit, and more particularly, to a memory unit cell circuit capable of improving information storage capability by using an asymmetric capacitor.

In general, a unit cell of a DRAM is composed of one transistor and one capacitor to store two bits of information. The memory unit cell circuit will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a conventional memory unit cell circuit. As shown in FIG. 1, an n-MOS transistor Tr having a gate connected to a word line and a drain connected to a bit line, One side is grounded, and the other side is constituted by a capacitor C connected to the source of the enMOS transistor Tr, and the operation of the conventional apparatus configured as described above will be described.

First, when data '0' is stored, a high potential is applied to a word line as shown in FIG. 2 (a), whereby the NMOS transistor Tr is turned on, and at this time, a bit line When the low potential is applied to the capacitor C, the capacitor C is discharged, and when the word line is made low voltage at a predetermined time, the NMOS transistor Tr is turned off and data is stored in the capacitor C. '0' is stored.

On the contrary, when data '1' is stored, 'high potential' is applied to the word line as shown in FIG. 2 (b), whereby the NMOS transistor Tr is turned on, where the bit line ( When 'high potential' is applied to the bit line, the 'high potential' charges the capacitor C through the NMOS transistor Tr, and at a predetermined time, the word line turns to 'low potential'. When the NMOS transistor Tr is turned off, data '1' is stored in the capacitor C.

With the development of lithography technology, the dimensions of the transistors, word lines, and bit lines that make up a cell are rapidly decreasing. Capacitors must have sufficient capacitance to distinguish the required data. Therefore, there is a problem that it is difficult to improve the density because it is difficult to shrink below a certain size.

Accordingly, an object of the present invention is to provide a memory unit cell circuit capable of improving information storage capability without increasing an area of a chip by using an asymmetric capacitor.

1 is a circuit diagram showing a configuration of a conventional memory unit cell circuit.

FIG. 2 is a circuit diagram showing data storage in FIG.

Figure 3 is a circuit diagram showing the configuration of the memory unit cell circuit of the present invention.

4 shows data storage and sensing in FIG.

***** Description of the symbols for the main parts of the drawings *****

Tr1, Tr2: NMOS transistor C1: Asymmetric capacitor

In order to achieve the above object, the present invention provides a first NMOS transistor having a first word line connected to a gate, a first data line connected to a drain, a second word line connected to a gate, and a second data line connected to a drain. And an asymmetric capacitor connected between the connected second NMOS transistor and the sources of the first and second NMOS transistors.

Hereinafter, operations and effects of the memory unit cell circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing a configuration of a memory unit cell circuit according to an embodiment of the present invention, in which a first word line having a first word line (Word Line1) connected to a gate and a first data line (Data Line1) connected to a drain connected thereto, as shown in FIG. A second NMOS transistor Tr2 having a MOS transistor Tr1, a second word line Word2 connected to a gate thereof, a second bit line Bit2 connected to a drain thereof, and the first and second NMOS transistors; It consists of an asymmetric capacitor C1 connected between the sources of the transistors Tr1 and Tr2, and this operation of the present invention will be described.

First, when storing the data '0', 'high potential' is applied to the first and second word lines (Word Line 1, 2) as shown in Figure 4 (a) and the first and second bit lines (Bit Line 1, When 'low potential' is applied to 2), data '0' is stored in the asymmetric capacitor C1, and 'high potential' is applied to the first and second word lines 1, 2 and When 'high potential' is applied to the two bit lines Bit Line 1 and 2, data '0' is stored in the asymmetric capacitor C1.

When the data '1' is stored, 'high potential' is applied to the first and second word lines (Word Line 1 and 2) as shown in FIG. 4 (b) and 'low' to the first bit line (Bit Line 1). When 'high potential' is applied to the potential 'second bit line Bit Line2, data' 1 'is stored in the asymmetric capacitor C1.

When the data '2' is stored, 'high potential' is applied to the first and second word lines (Word Lines 1 and 2) and 'classic' is applied to the first bit line as shown in FIG. When 'low potential' is applied to the second bit line Bit line 2, data '2' is stored in the asymmetric capacitor C 1.

When reading the data stored in the asymmetric capacitor C1, as shown in (d) of FIG. 4, 'low potential' in the first word line (Word Line1) and 'high potential' in the second word line (Word Line2). When the reference voltage Ref is applied to the first bit line Bit Line 1, the data stored in the asymmetric capacitor C 1 is sensed through the second bit line Bit Line 2.

That is, since different charges are stored when the voltage polarities of both ends of the asymmetric capacitor C1 are changed, information of three different states can be stored in one asymmetric capacitor C1. It is composed of Poly-Si and Metal having Depletion area inside and Dielctric Layer existing in the middle.

As described in detail above, the present invention can store and read charges of three states using a single asymmetric capacitor, so that the area of the cell capacitor becomes smaller than that of an existing memory cell having two states in one capacitor. Dominant has the effect of improving information storage ability.

Claims (6)

The first NMOS transistor Tr1 having a first word line (Word Line1) connected to the gate, the first bit line (Bit Line1) connected to the drain, and the second word line (Word Line2) connected to the drain, And an asymmetric capacitor (C1) connected between a second NMOS transistor (Tr2) to which two bit lines (Bit Line2) are connected and a source of the first and second NMOS transistors (Tr1 and Tr2). Memory unit cell circuit. The asymmetric capacitor of claim 1, wherein 'high potential' is applied to the first and second word lines, and 'low potential' is applied to the first and second bit lines. A memory unit cell circuit, characterized in that data '0' is stored in (C1). 2. The asymmetric capacitor of claim 1, wherein 'high potential' is applied to the first and second word lines, and 'high potential' is applied to the first and second bit lines. A memory unit cell circuit, characterized in that data '0' is stored in (C1). The method of claim 1, wherein 'high potential' is applied to the first and second word lines (Word Lines 1 and 2) and 'low potential' is applied to the first bit line (Bit Line1). The memory unit cell circuit is characterized in that when the high potential 'is applied data' 1 'is stored in the asymmetric capacitor (C1). The method of claim 1, wherein 'high potential' is applied to the first and second word lines (Word Lines 1 and 2), and 'high potential' is applied to the first bit line (Bit Line1). The memory unit cell circuit, characterized in that the data '2' is stored in the asymmetric capacitor (C1) when the low potential 'is applied. The method of claim 1, wherein 'low potential' is applied to the first word line (Word Line1), 'high potential' is applied to the second word line (Word Line2), and the reference voltage Ref is applied to the first bit line (Bit Line1). The memory unit cell circuit of claim 1, wherein the data stored in the asymmetric capacitor C1 is sensed through the second bit line.