KR100347514B1 - Apparatus for Processing an ATM Layer Function - Google Patents

Abstract

As an ATM system becomes high-capacity and requires new service functions, an improved ATM layer function processing apparatus is disclosed that enables all ATM layer functions required by an ATM system to be implemented on a single ASIC chip. The present invention implements an ATM layer function commonly used for all physical links, and goes beyond a simple ATM cell generation / termination function, by using a QOS (Quality Of Service) buffering function of high-capacity 622 Mbps traffic and hardware. By providing real-time operation and management (OAM) processing function, UPC (Usage Parameter Control) and ABR traffic control function in one ASIC chip, it provides ATM layer function processing device to be competitive in terms of function and price.

Description

ATM layer function processing unit {Apparatus for Processing an ATM Layer Function}

The present invention relates to an apparatus for processing an asynchronous transfer mode (hereinafter, referred to as ATM) layer function, and more particularly, an ATM layer that accommodates all ATM layer functions and implements them on one chip. It relates to a functional processing device.

In the early ATM devices, ATM layer function processing devices were manufactured in the form of a single board using various devices such as memory, FPGA, and CAM. However, as the number and speed of subscribers to be supported increase, ATM devices are composed of commercial devices. Doing so would increase the size of the system and raise prices, making it economically viable.

Accordingly, this problem was solved by implementing some of the ATM layer functions using an application specific integrated circuit (ASIC), but the devices mainly related to 155Mbps traffic processing.

Recently, QOS (Quality Of Service) buffering function for 622Mbps traffic, in addition to the creation / termination function of ATM cells basically provided by ATM devices in order to use network resources as efficiently as possible and provide better quality of service. In addition, new functions such as real-time OAM (Operation And Management) processing by hardware, UPC (Usage Parameter Control) and ABR (Avariable Bit Rate) traffic control are additionally required.

Accordingly, the present invention has been made under such a technical background, and in order to solve the problem that an ATM system cannot be implemented as a commercial device as a high-speed, high-capacity and new service function is required, all ATM layer functions required by the recent ATM system are required. The purpose of the present invention is to provide an ATM hierarchical processing unit having an efficient function so that it can be implemented in one ASIC chip.

In addition, the present invention is a broadband ATM terminal (B-TE) and network terminator (B-NT) required for the construction of a broadband integrated information network (B-ISDN), as well as ATM switch, ATM cross-connect (Cross-Connect), etc. Implementing the ATM layer function commonly used for all physical links in all ATM devices, the QOS (Quality Of Service) buffering function of the high-capacity 622Mbps traffic goes beyond the simple processing of creating / terminating the ATM cell. Real-time operation and management (OAM) processing, UPC (Usage Parameter Control) and ABR traffic control functions are implemented in one ASIC chip to enable the development of competitive ATM devices in terms of function and price. do.

1 is a detailed block diagram of an apparatus for processing an ATM layer function according to the present invention.

* Explanation of symbols for main parts of the drawings

B2 to B11: Receiver B12 to B20: Transmitter

B21: cell memory connection part B22: cell extraction buffer

B23: status extraction buffer B24: processor connection

The present invention for achieving the above object, beyond the processing of only the generation / termination function of the simple ATM cell, QOS (Quality Of Service) buffering function of large-capacity 622Mbps traffic, real-time OAM processing function by hardware Receive UTOPIA connection, receive connection table management, receive OAM processing, UPC processing, receive routing control, receive output control, receive test cell generator, receive cell to perform UPC (Usage Parameter Control) and ABR traffic control functions. Multiplexing control unit, receiving switch connection unit, receiving connection memory connection unit, transmission switch connection unit, transmission connection table management unit, transmission output control unit, transmission OAM processing unit, transmission test cell generation unit, transmission cell multiplexing control unit, transmission UTOPIA connection unit, transmission connection memory connection unit, cell A memory connection, a cell extraction buffer, a state extraction buffer, and a processor connection.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a detailed block diagram of an apparatus for processing an ATM layer function according to the present invention.

Referring to Fig. 1, the 622Mbps ATM layer function processing apparatus of the present invention is largely composed of receiving means (B2 to B11), transmitting means (B12 to B20), cell memory connection portion (B21), and processor connection portion (B24). do.

The receiving means comprises: a receiving UTOPIA connection B2 for generating a receiving physical layer device connection signal and thus reconfiguring header information of the received cell to generate a receiving connection memory address corresponding to the connection to which the received cell belongs; Receive connection table management unit (B3) that reads parameters related to the receiver function from the receive connection memory and transfers them to each function processor, and stores the parameter values after all processing is completed, and performs two stages of the generic cell rate algorithm. Each virtual connection using maximum cell rate, cell delay variation and sustainable cell rate, maximum burst size, burst tolerance, etc. UPC processing unit (B4) for detecting and acting on a cell exceeding the negotiated traffic rate for each virtual connection), AIS, RDI, CC alarm Receive OAM processing unit (B5), Receive connection table management unit (B3), Receive OAM processing unit that detects the occurrence and release conditions, calculates and accumulates performance-related data when the PM cell is received, and determines the routing direction for the processed OAM cell. (B5), the reception routing control unit (B6) and the receiving routing control unit (B6) to determine the direction in which the cell is delivered by combining the information transmitted from the UPC processing unit (B4) and manages the cell memory in the form of a shared memory; A reception output control unit (B7) which receives the cell from the cell memory and transfers it to the reception switch connection unit (B10), and a reception test cell for generating any type of ATM cell required by the user to test the ATM switch function at an arbitrary speed. The generator B8, the cell inserted in the receiving direction from the external processor, the test cell generated from the receiving test cell generator B8, and the use read from the external cell memory from the receiving output control unit B7. Receive cell multiplexing control unit (B9) for multiplexing its own cells according to priority; Receive switch connection unit for converting ATM cell data processed in 32-bit units into 8 bits or 16 bits and attaching routing tags to the switch device ( B10), and each receiving UTOPIA connection unit B2, a reception connection table management unit B3, a reception output control unit B7, a reception OAM processing unit B5, and a processor connection unit B24 each read and write a reception connection memory. It consists of a receiving connection memory connection section B11 for reading and writing data by arbitrating the request of the functional section.

On the other hand, the transmitting means, the transmission switch connection unit (B12) for removing the routing tag of the input cell and reconstruct the header information to generate a transmission connection memory address corresponding to the connection to which the input cell belongs, and the received cell A send connection table manager (B13) which reads parameters related to the transmit OAM and QOS buffering functions from the receive connection memory by using the memory address of the connection to which they belong, and transmits them to each function processor and stores the processed parameter values again; The routing information transmitted from the table management unit B13 is aggregated, the FIFO inside the transmission switch connection unit B12 is read, the cell is transferred to the corresponding place, and the cell memory is managed as a shared memory, according to the output port and class of the input cell. In response to commands from the transmission routing control unit B14 and the transmission routing control unit B14 stored in the corresponding priority queue, Transmits the cell to the transmission output control unit B15, which reads the cell from the cell, and transmits it to the transmission cell multiplexing control unit B18, and the connection set to transmit the alert cell or CC cell while checking the connection table of the transmission unit at a period of 1 second. A transmission test cell for generating an ATM cell of any type required by a user for testing a transmission OAM processing unit B16 to be transmitted to the cell multiplexing control unit B18 and an external physical layer device connected to the transmission UTOPIA connection unit B19. Generation unit B17, a cell inserted in the transmission direction by an external processor, a test cell generated by the transmission test cell generation unit B17, a user cell read from the external cell memory by the transmission output control unit B15, and a transmission OAM processing unit A transmission cell multiplexing control unit B18 for multiplexing the OAM cell generated at (B16) and the loopback cell delivered at the reception routing control unit B6 according to priority, and a transmission physical layer device Transmission UTOPIA connection unit B19, transmission switch connection unit B12, transmission connection table management unit B13, transmission output which converts internally processed ATM cell data in 8-bit or 16-bit units according to the connection signal and transmits them The control unit B15, the transmission OAM processing unit B16, and the processor connection unit B24 each comprise a transmission connection memory connection unit B20 that arbitrates the request of each block so as to read and write the transmission connection memory.

The cell memory connection portion B21 formed between the reception means and the transmission means includes a reception routing control unit B6, a reception output control unit B7, a transmission routing control unit B14, a transmission output control unit B15, and a processor. The connection unit B24 reads and writes data by arbitrating the request of each functional unit so that the cell memory can be read and written respectively.

The processor connection unit B24 controls the operation mode of each functional unit, reads the state in operation, and inserts a software-configured cell from the processor in a receiving and transmitting direction, and receives and receives for connection establishment and release. This function reads and writes the transmit connection memory and converts the data stored in the cell extraction buffer and the state extraction buffer into 16-bit units and transfers the data to the processor. The cell extract buffer B22, which is stored and delivered to the processor access point B24, and detailed information such as a connection address and a state generated when an interrupt occurs related to an internal UPC, OAM, header conversion, etc. And a state extraction buffer B23 to be passed to B24.

The operation of the ATM layer function processing apparatus of the present invention having the above-described configuration will be described below.

First, the receiving UTOPIA connection unit B2 generates a reception physical layer device access signal according to UTOPIA Level-1 and UTOPIA Level-2 standards, and accordingly reconfigures header information of the received cell to which the received cell belongs. Generates the receive connection memory address corresponding to the connection.

A maximum of 31 physical layer devices can be connected, and a sequential method checks and reads whether a cell to be transmitted exists in the physical layer device.

The receiving connection table manager B3 reads parameters related to the receiving OAM, UPC and QOS buffering functions from the receiving connection memory by using the memory address of the connection to which the received cell generated at the receiving UTOPIA connection B2 belongs. It transfers to each function processing unit and when all processing is completed, it stores the parameter value which needs updating again in the receiving connection memory.

The UPC processor B4 protects the network from malfunction of a subscriber device due to cell delay and congestion or intentional or mistake by the statistical multiplexing method, which is a characteristic of ATM, and provides quality of service (QoS) for all preset connections. In order to ensure the traffic, the network detects and measures a cell exceeding the negotiated traffic rate for each virtual connection.

That is, the CLP bit tagging or discarding signal is transmitted to the reception routing control unit B6 for the cell exceeding the negotiated traffic rate by comparing the negotiation traffic parameter received from the reception connection table management unit B3 with the traffic rate of the input cell. do.

The detailed configuration uses the Generic Cell Rate Algorithm based on the Virtual Scheduling Algorithm in two stages to control not only the Constant Bit Rate (CBR) but also the Variable Bit Rate (VBR) traffic. .

In this case, the first normal cell rate algorithm execution unit uses the maximum cell rate and cell delay variation, and the second general cell rate algorithm execution unit uses the sustainable cell rate and the maximum burst size. (Maximum Burst Size) and Burst Tolerance parameters are used to determine whether a negotiation is violated.

The receiving OAM processing unit B5 is divided into a part that operates every time a cell is received and a part that processes the OAM while scanning all the connection tables in units of 1 second separately from each other. Various OAM functions are performed based on the data read from the data, the data extracted from the cell at the receiving UTOPIA connection unit B2, and the connection table in the unit of 1 second.

The receiving OAM processing unit B5 detects the occurrence and release conditions of the AIS, RDI, and CC alarms, and writes the type of alarm and the connection table address where the alarm occurs to the state extraction buffer B23, and the forward PM cell or the like. Performs a function of calculating and accumulating performance related data when a backward PM cell is received.

In addition, when the OAM cell is received, routing information, that is, the OAM loopback cell, the cell to be extracted by the processor, the cell to discard, the reverse PM loopback cell, or the RM cell must be passed as a result of the processing of the OAM cell. Whether the cell is to be transmitted is transmitted to the reception routing control unit B6.

The reception routing control unit B6 receives routing information (passed through a switch, CPU extraction, loopback, unregistered) received from the reception connection table management unit B3, and routing information received from the reception OAM processing unit B5 (discard, OAM loopback, First-in-first-out (FIFO: First Input First Output) of the receiving UTOPIA connection (B2) by combining CPU extraction, modified with backward reporting cell, loopback, RM cell or not, and information received from UPC processing unit (B4) (disposal, CLP tagging). ) Will send the cell to the appropriate location.

At this time, the information received from the reception connection table management unit B3 (header value to be converted, VP connection) and the information required to create a backward reporting cell (PM cell SN error, received CLP0 +) The cell header and payload can be determined using one cell count, CLP0 cell count, BIP error number without SN error, or information needed to create an ABR cell (CI, NI and ER values updated, ER value to be replaced). Will change.

In addition, when a cell is extracted by the CPU, the location where the cell is extracted is a receiver, how many times the cell is received through the port, and the reason why the cell is extracted is the routing information set in the reception connection table. Whether it is a result of or a non-registered cell is coded and inserted into the front of the cell and delivered.

In case of loopback, in case of OAM loopback, the loopback identifier (ID) is subtracted by 1, and when sending a backward reporting PM cell, TRCC0 + 1, TRCC0, and BIPV values are inserted at the back of the payload.

In addition, in the case of the OAM loopback cell and the RM cell for ABR, the last CRC10 value is newly calculated and replaced by using the CRC10 encoder.

In addition, the reception routing controller B6 internally manages the cell memory as a shared memory, stores the cell memory in a corresponding priority queue according to the class of the input cell, and independently schedules it to determine and read a queue of a class to be serviced. The service of this cell is requested to the reception output control unit B7 together with the address of the ATM cell.

In addition, when the reception output control unit B7 completes the service, the reception output controller B7 updates the information of the corresponding queue and determines a class queue to receive the next service.

The reception output control unit B7 receives a command from the reception routing control unit B6, reads the cell from the cell memory, and transfers the cell to the reception switch connection unit B10.

At the same time, the data is read from the connection table associated with the cell and the routing tag, HEC, and UDF are sent together. In the non-QOS buffering mode, the data is read with the cell through the FIFO interface inside the receiving routing controller B6. Come.

The reception output control unit B7 informs the reception routing control unit B6 of the next head address of the corresponding class queue when the cell finishes reading and transferring the cell from the cell memory so that the queue information is newly updated.

The reception test cell generation unit B8 randomly selects an ATM cell of any type required by the user to test an ATM switch function of routing the cell to a corresponding output port according to routing information of each ATM cell. To create.

The receiving cell multiplexing control unit B9 prioritizes a cell inserted in a receiving direction by an external processor, a test cell generated by the receiving test cell generating unit B8, and a user cell read from the external cell memory by the receiving output control unit B7. The signal is multiplexed according to the ranking and transmitted to the reception switch connecting unit B10.

The reception switch connection unit B10 converts the ATM cell data processed in 32-bit units into 8 bits or 16 bits and transmits it to the switch device together with the switch connection signal generated by attaching a routing tag. Up to 11 routing tags can be attached depending on the type of external switch to be connected.

The reception connection memory connection unit B11 reads the reception connection memory from the reception UTOPIA connection unit B2, the reception connection table management unit B3, the reception output control unit B7, the reception OAM processing unit B5, and the processor connection unit B24, respectively. It performs the function of reading and writing data by mediating the requests of each functional unit so that they can be written.

In case of reading, the read data is transferred to the requesting function. In case of writing, the data transmitted from the selected function is written to memory.

The transmit switch connection unit B12 removes the routing tag of the input cell and reconfigures header information to generate a transmit connection memory address corresponding to the connection to which the input cell belongs.

The transmission connection table management unit B13 reads parameters related to the transmission OAM and QOS buffering functions from the reception memory by using the memory address of the connection to which the received cell generated at the transmission switch connection unit B12 belongs, to each function processing unit. When all processing is completed, the parameter value that needs to be updated is stored again in the send connection memory.

The transmission routing control unit B14 aggregates the routing information (passed through the switch, CPU extraction, loopback, unregistered, and RM cell information) transmitted from the transmission connection table management unit B13 to collect the FIFO inside the transmission switch connection unit B12. Read and pass the cell to the appropriate place.

Information transmitted from the transmission connection table management unit B13 (header value to be converted, VP connection status) in the process of delivering a cell, and information necessary for generating an RM cell (update of CI, NI and ER values, and replacement) ER value) to change the cell header and payload.

In addition, when a cell is extracted by the CPU, whether the cell is extracted is a transmitting unit and whether the CPU is extracted from routing information set in the transmission connection table, is a result of OAM processing, or an unregistered cell. Code it, insert it at the front of the cell, and pass it.

In the case of an RM cell, the CRC10 value is also newly calculated. In addition, the transmission routing control unit internally manages the cell memory as a shared memory, stores it in the corresponding priority queue according to the output port and class of the input cell, and independently schedules it to determine the port and class queue to be serviced. Request the cell's service to the transmit power control unit along with the address of the ATM cell to receive. In addition, when the transmission output controller finishes the service, it updates the information of the corresponding queue and determines the next serviced port and the class queue.

The transmission output control unit B15 receives a command from the transmission routing control unit B14 and reads the cell from the cell memory and transfers the cell to the transmission cell multiplexing control unit B18. It also reads data from the linked table associated with the cell and updates the performance data, or inserts a Forward Monitoring PM cell, and delivers HEC and UDF with the cell, and multicast Sends a port identifier (port ID) including.

When in the QOS function execution mode, such data is read directly from the transmission connection memory, and when not in the QOS function execution mode, the data is read together with the cell through the FIFO interface of the transmission routing control unit B14.

On the other hand, the transmission output control unit B15 has a one-cell FIFO therein, and performs buffering with the transmission cell multiplexing control unit B18 to process the next cell before the previous cell is completely processed and output. Increase

When the transmission output control unit B15 reads the cell from the cell memory and transfers the cell, the transmission output control unit B15 notifies the reception routing control unit B14 of the next head address of the corresponding class queue so that the queue information is newly updated.

The transmission OAM processor B16 forwards the cells to the transmission cell multiplexing control unit B18 for the connection set to transmit the alert cell or CC cell while checking the transmission connection table at a period of 1 second to be sent out.

In addition, the transmission OAM processor B16 creates and sends a cell header and payload in consideration of the type of the configured alarm (or CC), the connection setting (whether it is a segment or an endpoint), and a VP connection, and inserts a CRC10.

The transmission test cell generation unit B17 generates an ATM cell of any type required by the user to test an external physical layer device connected to the transmission UTOPIA connection B19.

The transmission cell multiplexing control unit B18 is a cell inserted in the transmission direction by an external processor, a test cell generated by the transmission test cell generation unit B17, a user cell read from the external cell memory by the transmission output control unit B15, and transmission. The OAM cell generated by the OAM processing unit B16 and the loopback cell delivered by the reception routing control unit B6 are multiplexed according to priority and transmitted to the transmitting UTOPIA access unit B19.

The transmitting UTOPIA connection unit B19 generates a transmission physical layer device connection signal according to the UTOPIA Level-1 and UTOPIA Level-2 standards and accordingly converts ATM cell data processed in 32-bit units into 8 bits or 16 bits. To pass. At this time, up to 31 physical layer devices are checked whether the cells can be received in a sequential manner, and the cells are transmitted.

The transmission connection memory connection unit B20 reads the transmission connection memory from the transmission switch connection unit B12, the transmission connection table management unit B13, the transmission output control unit B15, the transmission OAM processing unit B16, and the processor connection unit B24, respectively. It performs the function of reading and writing data by mediating the requests of each functional unit so that they can be written. In case of reading, the read data is transferred to the requesting function. In case of writing, the data transmitted from the selected function is written to memory.

The cell memory access unit B21 reads and writes the cell memory from the reception routing control unit B6, the reception output control unit B7, the transmission routing control unit B14, the transmission output control unit B15, and the processor connection unit B24, respectively. It mediates the requests of each functional unit to read and write data. In case of reading, the read data is transferred to the requesting function. In case of writing, the data transmitted from the selected function is written to memory.

The cell extraction buffer B22 extracts a cell from a receiving and transmitting direction when the cell is extracted by an external processor, temporarily stores the cell, and transmits the cell to the processor access unit B24 when a read request is received from the processor. In this case, a word is attached to the front of the cell, including the extracted direction and cause.

The state extraction buffer B23 temporarily stores detailed information such as a state and a connection address generated when an interrupt occurs related to a function such as internal UPC, OAM, header conversion, etc., and sends a read request from the processor to the processor access unit B24. To pass.

The processor connection unit B24 controls the operation mode of each functional unit, reads the state in operation, and inserts a software-configured cell from the processor in the receiving and transmitting directions, and receives and transmits for connection establishment and release. It reads and writes the connected memory and converts the data stored in the cell extraction buffer and the state extraction buffer to 16-bit units and transfers them to the processor.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only for describing the best embodiment of the present invention and not for limiting the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

As described above, according to the present invention, in implementing an ATM layer function commonly used for all physical links of all ATM devices, it is possible to provide a high-capacity 622Mbps-class traffic beyond the level of processing a simple ATM cell generation / termination function. QOS buffering, hardware real-time OAM processing, UPC and ABR traffic control can all be implemented on a single ASIC chip, enabling functional and cost-effective ATM devices to be developed.

In addition, the present invention contributes to the construction of a domestic B-ISDN based on pure Korean technology, by causing the development of ATM devices that are competitive in terms of function and price, and induces the import substitution effect of core parts, and furthermore, B -It is effective in activating the domestic telecommunications industry related to ISDN, preoccupying international superiority of technology and securing international competitiveness of related products.

Claims (7)

A receiving UTOPIA connection (B2) for generating a receiving physical layer device connection signal and thereby reconstructing header information of the received cell to generate a receiving connection memory address; A reception connection table manager (B3) which reads parameters related to the reception function from the reception connection memory, transfers them to each function processing unit, and stores the parameter values in which all processing is completed; A UPC processor (B4) for detecting and acting on a cell exceeding the traffic rate negotiated for each virtual connection for traffic input to the network to guarantee a quality of service (QoS); A receiving OAM processor (B5) for detecting occurrence and release conditions of AIS, RDI, and CC alarms, calculating and accumulating performance related data when a PM cell is received, and determining a routing direction for the processed OAM cell; Receiving routing control unit (B6) by combining the information transmitted from the receiving connection table management unit (B3), the receiving OAM processing unit (B5), UPC processing unit (B4) to determine the direction in which the cell is to be delivered and manages the cell memory in the form of shared memory. ); A reception output control unit (B7) which receives a command from the reception routing control unit (B6) and reads a cell from a cell memory and transfers the cell to the reception switch connection unit (B10); A reception test cell generation unit B8 for generating any type of ATM cell required by the user to test the ATM switch function at an arbitrary speed; Receive cells for multiplexing cells inserted in a reception direction by an external processor, a test cell generated by the receive test cell generator B8, and a user cell read from an external cell memory by the receive output controller B7 according to priority. A multiplexing control unit B9; A reception switch connecting unit (B10) converting ATM cell data processed in 32-bit units into 8 bits or 16 bits and attaching a routing tag to the switch device; Receive requests from each functional unit so that the receiving UTOPIA connection unit B2, the reception connection table management unit B3, the reception output control unit B7, the reception OAM processing unit B5, and the processor connection unit B24 each read and write a reception connection memory. A receiving connection memory connection B11 for arbitration of reading and writing data; A transmission switch connection unit B12 for removing a routing tag of an input cell and reconfiguring header information to generate a transmission connection memory address corresponding to a connection to which the input cell belongs; Transmission connection table manager (B13) which reads parameters related to the transmission OAM and QOS buffering functions from the reception connection memory by using the memory address of the connection to which the received cell belongs, transfers them to each function processing unit, and stores the processed parameter values again. ; The output port of the input cell by combining the routing information transmitted from the transmission connection table management unit B13, reading the FIFO inside the transmission switch connection unit B12, and transferring the cell to a corresponding place, and managing the cell memory as a shared memory; A transmission routing control unit B14 for storing in a priority queue corresponding to the class; A transmission output control unit (B15) which receives a command from the transmission routing control unit (B14) and reads a cell from a cell memory and transmits the cell to the transmission cell multiplexing control unit (B18); A transmission OAM processing section (B16) for delivering such a cell to a transmission cell multiplexing control section for a connection set to transmit an alert cell or CC cell while checking the connection table of the transmission section at a period of 1 second; A transmission test cell generation section B17 for generating any type of ATM cell required by the user to test an external physical layer device connected to the transmission UTOPIA connection; A cell inserted in the transmission direction by an external processor, a test cell generated by the transmission test cell generation unit B17, a user cell read from the external cell memory by the transmission output control unit B15, and an OAM generated by the transmission OAM processing unit B16. A transmission cell multiplexing control unit B18 for multiplexing the loopback cells transmitted from the cell and the reception routing control unit B6 according to priority; A transmission UTOPIA connection unit B19 for converting ATM cell data processed in 32-bit units internally into 8 bits or 16 bits according to the transmission physical layer device connection signal, and transferring the converted 8 cell or 16 bits; The transmission switch connection unit B12, the transmission connection table management unit B13, the transmission output control unit B15, the transmission OAM processing unit B16, and the processor connection unit B24 each request the request of each block to read and write the transmission connection memory. A transmission connection memory connection B20 for arbitration of reading and writing data; The reception routing control section B6, the reception output control section B7, the transmission routing control section B14, the transmission output control section B15, and the processor connection section arbitrate the request of each functional section to read and write data, respectively, to read data. A write cell memory connection portion B21; To control the operation mode of each functional unit, to read the status during operation, to insert a software-configured cell from the processor in the receive and send direction, to read and write the receive and send connection memory for connection establishment and release, And a processor connection unit (B24) for converting the data stored in the cell extraction buffer and the state extraction buffer into 16-bit units and transferring the data to the processor. The method of claim 1, wherein the UPC processing unit B4, An ATM layer function processing apparatus, comprising two stages of a Generic Cell Rate Algorithm performing unit for controlling both CBR (Constant Bit Rate) and Variable Bit Rate (VBR) traffic. The method of claim 2, The first general cell rate algorithm execution unit uses a maximum cell rate and a cell delay variation parameter. The second general cell rate algorithm execution unit determines whether to negotiate a violation by using a sustained cell rate, a maximum burst size, and a burst tolerance parameter. . The receiving OAM processing unit B5 according to claim 1, An ATM layer function processing apparatus, comprising: a part operating only when a cell is received, and a part processing OAM (Operation and Management) while separately scanning all connection tables in units of 1 second. The method of claim 1, wherein the cell forwarding direction in the reception routing control unit B6, In the case of OAM loopback, 1 is subtracted from the loopback identifier (ID), In the case of the OAM cell and the RM cell for the ABR, ATM layer function processing apparatus, characterized in that by using the CRC 10 encoder to calculate and replace the last CRC 10 value. The transmission output control unit (B15) according to claim 1, ATM layer function further comprising a one-cell FIFO therein so as to process the next cell before the previous cell is completely processed and outputted by performing temporal buffering with the transmitting cell multiplexing control unit. Processing unit. The method of claim 1, wherein the processor connector (B24), A cell extraction buffer (B22) for extracting a cell from a receiving and transmitting direction and temporarily storing the cell from the receiving and transmitting direction when transferring the cell to an external processor; And ATM, characterized in that it further comprises a state extraction buffer (B23) for temporarily storing the detailed information, such as the state generated when the interrupt occurred associated with the function such as the internal UPC, OAM, header conversion, and the connection address, and forwarded to the processor connection unit. Layer function processor.