KR0140782B1 - Measurement system for performance of cell transferring system in atm switch - Google Patents

Abstract

The present invention is a cell delivery system of an ATM switching system operating as a node in a broadband communication network.

The present invention relates to a measurement device for measuring performance, and provides a measurement device for measuring cell delivery system performance of an ATM switching system by measuring and storing arrival time intervals of an actual ATM service cell in advance and using the data as cell generation interval setting data. In order to do so, using a commercially available SDH chip, UNI matching means 23 for matching with the external ATM switching system 12;

ATM cell generation and means (22) for generating an ATM cell and verifying cell information looped back through the ATM switching system via the system bus (24) and UNI matching means; Storage means (13) for storing the ATM cell generation time interval data for each service; And reading the cell generation time interval data from the ATM cell generation and verification means 22 via the system bus 24 and storing it in the storage means 13, and splitting the cell generation time interval data into a cell discard rate. And a central processing unit (CPU) and a memory 21 for outputting an error rate to an operator, thereby accurately measuring cell performance.

Description

Cell delivery system performance measurement device of ATM switching system

1 is a connection state diagram of a cell delivery system performance measurement apparatus of an ATM switching system;

2 is a block diagram of a cell delivery system performance measurement apparatus according to the present invention,

3 is a block diagram of an ATM cell generation and verification unit according to the present invention.

* Explanation of symbols for main parts of the drawings

11: ATM cell delivery system performance measurement device 12: ATM exchange system

13: Hard disk 14: Personal computer or cathode ray tube terminal device

21: central processing unit (CPU) and memory 22: ATM cell generation and verification unit

23: UNI matching unit 24: System bus

31,32,33: Cell occurrence time interval data memory

34, 35, 36: Timer 37, 38, 39: Cell generation and verification control circuit

40, 41, 42: cell transmission data circuit 43, 44, 45: cell reception data circuit

The present invention relates to a measuring apparatus for measuring the performance of a cell transfer system of an ATM (Asynchronous Transfer Mode) switching system operating as a node in a broadband communication network.

The general ATM network transmits and switches all user information in the form of a unified packet of fixed length called a cell, so that various services from low to high speed can be provided in a unified network and new services are introduced. Has the advantage of facilitating. In addition, statistical multiplexing has the ability to cope with bursty traffic in which the amount of traffic is greatly changed in time.

However, when such burst traffic flows into the ATM network at the same time, it may fall into a congestion state where user quality requirements (QOS: Quality Of Service) cannot be satisfied.

Therefore, in order to prevent network congestion in advance and to efficiently use network resources, it is necessary to first understand the performance of the ATM switching system that performs the node function of the network. In other words, it is important to calculate the total serviceable capacity by actually measuring, verifying and confirming the performance of the ATM switching system before actually installing it in the ATM network for subscriber service.

Performance target parameters of such an ATM switching system can be classified into cell delivery system performance and cell processing system performance.

The cell delivery system performance is expressed as the total bandwidth that the cell traffic from the subscriber station may be delivered to the switching system and delivered to the destination terminal or the next switching node system while satisfying user quality requirements such as cell discard rate and cell delay.

The performance of the cell processing system is based on the Q.2931 protocol recommended by the International Telecommunication Union (ITU-T), when a call request arrives from a subscriber station, call disconnection delay time, call disconnection probability, call forwarding delay time, etc. It can be expressed as the maximum number of call services per unit time while satisfying the user quality requirements.

In order to measure the performance of such a cell delivery system, a function of generating a cell is required in the same manner as that of a subscriber station.

The types of traffic generated from the subscriber station are generally classified into voice, data, and video services according to the characteristics of the traffic.

To date, the proposed distribution of ATM cell traffic arrivals is based on the ON-OFF model for voice, the Modulated Poisson Process (MMPP) model for data, and the video telephony service. Mini-Source models are being announced.

However, the actual ATM service traffic is not only difficult for any one to model as the arrival distribution, but also has a lot of difficulty in selecting the parameter values of the arrival distribution.

Therefore, the present invention devised to meet the above demands, instead of generating cells using arrival distribution, measures and stores arrival time intervals of actual ATM service cells in advance and uses them as cell generation interval setting data. It is an object of the present invention to provide a measuring device capable of measuring the performance of a cell delivery system of an exchange system.

In order to achieve the above object, the present invention uses a SDH (Synchronous Digital Hierarchy) commercial chip, terminates the physical layer of the ATM cell received from an external ATM switching system, and outputs it to the system bus 24. UNI (User Network Interface) matching means for transmitting the ATM cell received through the system bus to the ATM switching system; ATM cell generation using an ATM cell generation time interval data for each service and transmitting the generated cell to the ATM switching system through the UNI bus and the UNI matching means, and then verifying the looped cell information through the ATM switching system. And verification means; Storage means for storing the ATM cell generation time interval data for each service; And central processing for reading the cell generation time interval data from the ATM cell generation and verification means through the system bus and storing it in the storage means, analyzing the cell generation time interval data, and outputting the cell discard rate and error rate to the operator. Device (CPI) and memory.

The present invention transmits cell data of a predetermined pattern to the switching system at the time intervals of occurrence of the measured and stored ATM service cells in order to measure the cell discard rate and the error rate in the ATM switching system. When the transmitted cells are received back to the measurement device through the cell transfer system of the ATM switching system, the maximum bandwidth that satisfies the user quality requirements can be obtained by examining the cell discard rate and the error rate.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a connection state of a cell delivery system performance measuring device of an ATM switching system, where 11 is an ATM cell delivery system performance measuring device, 12 is an ATM switching system, 13 is a hard disk, and 14 is a personal computer or a cathode ray tube terminal device.

The cell delivery system performance measuring apparatus according to the present invention uses a hard disk 13 that stores ATM traffic cell generation time interval information for each service in advance as an auxiliary storage device. The small computer system interface (SCSI) is applied between the cell transfer system performance measuring device 11 and the hard disk 13. An RS-232C interface is provided to the cell delivery system performance measurement device for testing, operating and managing the cell delivery system performance measurement device through a personal computer (PC) or cathode ray tube terminal device (CRT) 14.

The ATM cell delivery system performance measurement apparatus transmits ATM cells to the switching system in accordance with UNI (User Network Interface) of the International Telecommunication Union-Telecommunication (ITU-T) Recommendation based on the cell occurrence time interval data. As the physical layer of the UNI, an optical fiber, a coaxial cable, a twisted pair line, etc. may be used, and a transmission frame method uses a SDH (Synchronous Digital Hierarchy) method.

The transmitted ATM cell is transmitted back to the cell delivery system performance measurement device through the switch network after the ATM layer is processed in the subscriber matching device of the switching system. At this time, in the ATM switching system, it is required to set the route in advance so that the ATM cell transmitted from the cell delivery system performance measuring apparatus can be transmitted again. This can be done by the operator via the Man Machine Communication (MMC) command.

2 is a configuration diagram of a cell delivery system performance measurement apparatus according to the present invention, in which 21 represents a central processing unit (CPU) and a memory, 22 represents an ATM cell generation and verification unit, 23 represents a UNI matching unit, and 24 represents a system bus. .

Referring to the operation, first, a hard disk 13 for storing cell generation time interval data for each service is connected to the CPU and the memory 21. Because ATM traffic has a very high correlation of cell arrival interval distributions, accurate performance can be specified by periodically transmitting data based on a certain time interval. Therefore, the hard disk 13 is required to store such a large amount of ATM cell generation time interval data.

In addition, the central processing unit (CPU) and the memory 21 include a central processing unit (CPU) peripheral circuit, a memory circuit, a system bus interface circuit for transferring data to the ATM cell generation and verification unit 22, a hard disk 13, The ATM cell generation and verification unit 22 includes a SCSI interface circuit for the interface between the ATM cell performance measuring apparatus 11 and an RS-232C interface circuit for testing, operating and managing the ATM cell delivery system performance measuring apparatus. Reads the cell generation time interval data through the system bus 24 and stores it in the hard disk 13, analyzes the cell generation time interval data, and transmits the cell discard rate and error rate to the operator through a personal computer or cathode ray tube terminal device. Output

Circuitry around the central processing unit (CPU) includes a system clock generator, an address and data bus interface, and other control signal interfaces. It is desirable to design the system clock speed as fast as possible in consideration of the ATM cell generation speed. The other circuit part is not different from the existing CPU, and thus description thereof is omitted here.

The ATM cell generation and verification unit 22 includes a system bus interface circuit for interfacing with the central processing unit (CPU) and the memory 21, a cell generation time interval data memory circuit for each service, a timer circuit, a cell generation and verification control circuit, A cell transmit data circuit, a cell receive data circuit, and the like are provided to generate an ATM cell to be used for the test, and to verify the cell data passed through the ATM switching system.

The system bus 24 is a parallel bus that consists of a data bus, an address bus, a control signal, and the like, and detailed signal definitions may vary depending on the type of central processing unit (CPU) used.

The UNI matching unit 23 uses the SDH commercial chip to transmit the ATM cells transmitted from the ATM cell generation and verification unit 22 to the switching system, and the ATM cells transmitted from the switching system terminate the physical layer again. Transfer to ATM cell generation and verification unit 22. At this time, the interface between the ATM cell generation and verification unit 22 and the UNI matching unit 23 uses a system bus 24.

The acceptance of the UNI interface is designed to allow the system bus 24 to operate at any level of speed, as much as possible is beneficial for performance measurement. The UNI matching unit 23 is composed of a physical layer processing circuit unit and an ATM layer processing circuit unit.

3 is a configuration diagram of an ATM cell generation and verification unit according to the present invention, wherein 31, 32 and 33 are cell generation time interval data memories, 34, 35 and 36 are timers, and 37, 38 and 39 are cell generation and verification control circuits. , 40, 41, 42 denote cell transmission data circuits, and 43, 44, 45 denote cell reception data circuits, respectively.

Looking at the operation in detail, if the cell generation time interval data is stored in the cell generation time interval data memory (31, 32, 33) for each service through the system bus 24, the cell generation and verification control circuit (37, 38, 39) Reads the cell generation time interval data and initializes the tires 34, 35, 36 which count the cell generation intervals. When the timers 34, 35, 36 time out, the cell generation and verification control circuits 37, 38, 39 inform the cell transmission data circuits 40, 41, 42 of the cell transmission timing. The cell transmission data circuits 40, 41, and 42 notified of the cell transmission timing transfer the cell to the UNI matching unit via the system bus 24.

At this time, the data portion of the cell delivered to the UNI matching unit 23 is configured in a predetermined pattern for the verification function. For example, in order to specify a cell error rate, a cyclic redundancy check (CRC) function used in an ATM adaptation layer (AAL) layer may be applied, and a timer (34, 35, 36) value may be counted for the purpose of measuring cell delay time. It can be attached to the data part.

Cell data generated from the cell transmission data circuits 40, 41, 42 is transferred to the UNI matching section 23 via the system bus 24.

ATM cells received from the ATM switching system 12 are extracted from the ATM layer of the UNI matching unit 23, which is the cell receiving data circuit 43 of the ATM cell generation and verification unit 21 via the system bus 24. 44,45). In this case, the cell discarding and cell error can be confirmed by checking whether the comparison circuit matches the transmission cell data.

Since the ATM cell data is transmitted to the number exchange system delivered to the UNI matching unit 23 through the system bus 24, the number of cell generations per unit time must be increased in order to load the exchange system. For this purpose, the speed of the system bus 24 should be a structure that can operate above a certain speed.

In the present invention as described above, an analysis method and a simulation method have been used to grasp the performance of a cell delivery system of an ATM switching system in which each service has different traffic characteristics. In the above, it is important to measure the cell delivery system performance accurately by comparing traffic with the received cell data after generating and transmitting traffic that matches the actual cell generation in the ATM switching system.

Claims (8)

A SDH (Synchronous Digital Hierarchy) commercial chip is used and the physical layer of the ATM cell received from the external ATM switching system 12 is terminated and outputted to the system bus 24 through the system bus 24. UNI (User Network Interface) matching means (23) for transmitting the received ATM cell to the ATM switching system; An ATM cell is generated using the service-specific ATM cell generation time interval data, transmitted to the ATM switching system through the system bus 24 and the UNI matching means 23, and then loop-backed through the ATM switching system. ATM cell generation verification means (22) for verifying information; Storage means (13) for storing the ATM cell generation time interval data for each service; And reading the cell generation time interval data from the ATM cell generation and verification means 22 via the system bus 24 and storing it in the storage means 13, analyzing the cell generation time interval data, and then discarding the cell. And a central processing unit (CPU) and a memory (21) for outputting an error rate to an operator. The personal computer (14) according to claim 1, wherein the personal computer (14) is connected to the central processing unit and the memory (21) via an RS-232C interface to allow an operator to test, operate, and manage an ATM cell delivery system performance measurement device (11). Cell delivery system performance measurement apparatus of the ATM exchange system further comprises. The cell delivery system performance measurement according to any one of claims 1 to 2, wherein the UNI matching means 23 includes a physical layer processing circuit portion and an ATM layer processing circuit portion. Device. The cell of any one of claims 1 to 2, wherein the system bus 24 is a parallel bus and includes a data bus, an address bus, and a control signal. Transmission system performance measurement device. The CPU according to any one of claims 1 to 2, wherein the central processing unit (CPU) and the memory (21) comprise a central processing unit (CPU) peripheral circuit, a memory circuit, the ATM cell generation and verification means (22); Test, operate, and manage a system bus interface circuit for data transfer of the data, a SCSI interface circuit for the interface between the storage means 13 and the ATM cell performance measuring apparatus 11, and the ATM cell transfer system performance measuring apparatus 11. Cell transmission system performance measurement apparatus of an ATM switching system comprising an RS-232C interface circuit for. 6. The cell transfer system performance measurement of an ATM switching system according to claim 5, wherein the CPU peripheral circuit comprises a system clock generator, an address and data bus interface and a control signal interface. Device. The method according to any one of claims 1 to 2, wherein the ATM cell generation and verification means (22) generates at least one cell stored for each service when cell generation time interval data is input through the system bus (24). Time interval data memories 31, 32, and 33; At least one timer (34, 35, 36) for counting cell occurrence intervals; At least one cell which notifies the cell transmission time when the time is out after initializing the timers 34, 35, and 36 by reading the cell occurrence time interval data from the cell occurrence time interval data memories 31, 32, and 33. Generation and verification control circuits 37, 38, 39; At least one cell transmission data circuit which is informed of the cell transmission time from the cell generation and verification control circuits 37, 38, 39 and transfers the cell to the UNI matching means 23 via the system bus 24; 40,41,42); And receiving the ATM cells received from the ATM switching system 12 extracted from the ATM layer of the UNI matching means 23 through the system bus 24. The cell generation and verification control circuits 37 and 38; 39. At least one cell receiving data circuit (43, 44, 45) for transmitting to the cell transmission system performance measurement apparatus, characterized in that it comprises. 8. The data portion of a cell, which is transmitted from the cell transmission data circuits (40, 41, 42) to the UNI matching means 23, is used in an ATM Adaptation Layer (AAL) layer to measure a cell error rate. The cyclic redundancy check (CRC) function is used and the timer 34, 35, 36 is added to the cell data portion to measure the cell delay time. Cell delivery system performance measurement device.