KR100346155B1 - Apparatus for multiplication in a digital automatic gain controller - Google Patents

Abstract

The present invention improves the performance of the digital automatic gain controller by compensating the nonlinear characteristics of the multiplier structurally, and also allows the design of the multiplier in the digital automatic gain controller to ensure flexibility in hardware implementation and to facilitate design. The present invention relates to a first register to which an output signal of a loop filter is applied, a second register to which an AGC input signal is applied, and a first output to be multiplied by a signal output from the first and second registers. A first multiplier comprising a double multiplier, a third register receiving a signal output from the first register, a fourth register receiving the signal output from the first and second multipliers of the first multiplier and the third register; A second multiplier consisting of third and fourth multipliers for receiving and multiplying signals output from the four registers, and outputting from the Nth register; The N + 2 register receiving the signal to be applied, the 2N register receiving the signal output from the N-1 and N-2 multipliers of the N-1 multiplier, and the N + 2 and 2N registers output from the N + 2 and 2N registers. The N + 3 multiplier consists of N + 3 and N + 4 multipliers for receiving and multiplying the signals to output AGC_OUT_I / Q signals.

Description

Multiplication device in digital automatic gain controller {Apparatus for multiplication in a digital automatic gain controller}

The present invention relates to a digital automatic gain control (AGC), and more particularly, to improve the performance of the digital automatic gain controller by compensating the nonlinear characteristics of the multiplier structurally and to implement the hardware. The present invention relates to a multiplication device in a digital automatic gain controller that can guarantee flexibility and facilitate design.

In general, with the development of an analog to digital converter (ADC) and a digital to analog converter (DAC) capable of processing high-speed data, it is possible to process the modulation and demodulation and filtering in the digital domain. This is called a digital radio or a software defined radio (SDR), and a receiver to which the digital radio is applied is called a digital receiver. In addition, as the ADC's dynamic range increases, AGC can be performed on digital receivers.

On the other hand, analog AGC is largely composed of a detector (detector), a loop filter (loop filter) and VCA (Voltage Controlled Amplifier).

The detector measures the power of the output signal and compares it to the desired power level. At this time, the desired power level is called a threshold of the AGC.

The loop filter is a low pass filter and integrates a power difference between a threshold value and a signal.

The VCA is an amplifier that adjusts a gain according to an input voltage, and an output value of a low pass filter is used as an input signal of the VCA. The double detector can be divided into a VCA having a linear characteristic and a VCA having an exponential characteristic.

In addition, when the fading depth is not large, that is, when the amount of change in the power level of the input signal is not large, the performance of the VCA having a linear characteristic and an exponential characteristic is similar. On the other hand, when the fading depth is large, the exponential VCA performs better than the linear VCA.

1 is a block diagram of a general digital AGC.

As shown in FIG. 1, in the case of digital AGC, the detector 10 and the loop filter 20 have the same structure as that of the analog AGC, while the part corresponding to the VCA is generally implemented by the multiplier 30.

In addition, since the output signal of the digital AGC is the product of the AGC input signal and the output signal of the loop filter 20, the multiplier 30 may be interpreted as a VCA having a linear characteristic.

In order to implement the multiplier 30 corresponding to the VCA having the exponential characteristic in the digital AGC, the power of 10 must be taken with respect to the output signal of the loop filter 20.

However, this greatly increases the complexity of the digital receiver.

Therefore, in the case of the existing digital AGC, the portion corresponding to the VCA is implemented by a simple multiplier, which causes a problem of degrading performance.

Accordingly, an object of the present invention is to solve the above-described problems according to the prior art, and an object of the present invention is to improve the performance of the digital automatic gain controller by compensating the nonlinear characteristics of the multiplier structurally and to implement the hardware. The present invention provides a multiplication device in a digital automatic gain controller that can guarantee flexibility and facilitate design.

The multiplication apparatus of the digital automatic gain controller according to the present invention for achieving the above object is characterized in that the first register is applied to the output signal of the loop filter, the register and the second register is applied to the input signal of the AGC and the first A first multiplier comprising first and second multipliers for receiving and multiplying a signal output from the two registers, a third register receiving a signal output from the first register, and a first and second multiplication of the first multiplier A second multiplier comprising a fourth register to receive a signal output from a negative portion, a third and fourth multiplier to receive and multiply the signals output from the third and fourth registers, and a second to receive a signal output from the Nth register. N + 2 register, the second N register receiving the signal output from the N-1, N-2 multiplier of the N-1 multiplier and the signal output from the N + 2, 2N register is received and multiplied N-th multiplier consisting of N + 3 and N + 4 multipliers that output AGC_OUT_I / Q signals, respectively.

1 is a block diagram of a general digital AGC,

2 is a configuration diagram of a first embodiment of a multiplication apparatus in a digital automatic gain controller according to the present invention;

3 is a simulation diagram of a multiplication apparatus in a digital automatic gain controller according to the present invention;

4 is a configuration diagram of a second embodiment of the multiplication apparatus in the digital automatic gain controller according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 110: register,

120, 130: multiplication unit,

140: The multiplier.

Hereinafter, a preferred embodiment of the multiplier according to the present invention will be described with reference to the accompanying drawings.

2 is a configuration diagram of a first embodiment of a multiplication apparatus in a digital automatic gain controller according to the present invention.

As illustrated in FIG. 2, the first register 100 to which the output signal LOOP_OUT of the loop filter is applied, the register 2 to which the AGC input signal AGC_IN_I / Q is applied, and the first and second registers 110 are applied. A first multiplier 140 comprising first and second multipliers 120 and 130 for receiving and multiplying a signal output from the second registers 100 and 110 and a signal output from the first register 100. Is applied to the third register 150 and the first and second multipliers 120 and 130 of the first multiplier 140 is applied to the fourth register 160 and the third and fourth, respectively. The second multiplier 190 including the third and fourth multipliers 170 and 180 for receiving and multiplying the signals output from the registers 150 and 160 and a signal output from the Nth register (not shown). A second N register that receives a signal output from the N-th + 2 register 200, and the N-1 and N-2 multipliers (not shown) of the N-1 multiplier (not shown). 210 and the N + 2th The N-multiplier 240 includes N + 3 and N + 4 multipliers 220 and 230 for multiplying the signals output from the 2N registers 200 and 210 to output the AGC_OUT_I / Q signals. Is made of.

The operation of the multiplication apparatus in the digital automatic gain controller configured as described above is as follows.

First, the output signal loop_out of the loop filter is stored in the first register 100, and the input signal AGC_IN_I / Q of the AGC is stored in the second register 110 of the first multiplier 140.

Subsequently, the signal output from the first register 100 and the signal output from the second register 110 are multiplied by each other in the first and second multipliers 120 and 130 and output to the fourth register 160. And stored. At this time, when used as the output signal (AGC_OUT_I / Q) of the AGC output to the fourth register 180 has the same characteristics as the VCA having a linear characteristic.

The signal output from the first register 100 is output to the third register 150 and stored.

In addition, the signal output from the third register 150 and the signal output from the fourth register 160 are multiplied by each other in the third and fourth multipliers 170 and 180, and the next 2N register 210 is next. ) Is printed and saved.

The signal output from the third register 150 is then output to the next N-2 register 200 and stored.

Finally, the signal output from the N + 2 register 150 and the signal output from the second N register 210 are multiplied by each other in the N + 3, N + 4 multipliers 220 and 230. Each outputs an AGC_OUT_I / Q signal.

Therefore, the AGC output signal is obtained by multiplying the AGC input signal by the N power of the loop filter output signal.

3 is a simulation diagram of a multiplication apparatus in a digital automatic gain controller according to the present invention.

As shown in FIG. 3, a multiplier corresponding to a VCA having a linear characteristic, a multiplier corresponding to a VCA having an exponential characteristic, and N = 2, 3 and N + 10 are illustrated.

4 is a configuration diagram of a second embodiment of the multiplication apparatus in the digital automatic gain controller according to the present invention.

As shown in FIG. 4, the first register 300 receiving the output signal LOOP_OUT of the loop filter and the signal output from the first register 300 are received and multiplied by the first multiplier 310. The third and fourth registers 330 and 340 and the third and fourth registers 150 that receive the signals output from the squarer 320 and the first multiplier 310 of the squarer 320. A multiplier 360 consisting of a second multiplier 350 for receiving and multiplying the signal output from the 160 and from the N-1 multiplier (not shown) of the N-1th power (not shown) N-th multiplier 390 for receiving and multiplying the signals output from the N-th, N + 1 registers 370 and 380 and the N-th, N + 1 registers 370 and 380 respectively. Nth multiplier 400, N + 2 registers 410 receiving the signal output from the Nth multiplier 390 of the Nth multiplier 400, and AGC input signal AGC_IN_I / Q) authorized N + 1 and N + output the AGC_OUT_I / Q signals by multiplying and receiving the signals output from the N + 3 register 420 and the N + 2 and N + 3 registers 410 and 420, respectively. It consists of two multipliers 430 and 440.

The operation of the multiplication apparatus in the digital automatic gain controller configured as described above is as follows.

First, the output signal loop_out of the loop filter is stored in the first register 300 of the squarer 320 and multiplied by the first multiplier 310.

Subsequently, the signal output from the first multiplier 310 of the squarer 320 is stored in the second and third registers 330 and 340 of the multiplier 360 and multiplied by the second multiplier 350. .

The signal output from the N-1 multiplier (not shown) of the N-1th multiplier (not shown) is stored in the N, N + 1 registers 370 and 380 of the Nth multiplier 400. Multiplied by the N-th multiplier 390.

In addition, the signal output from the Nth multiplier 390 is stored in the N + 2th register 410.

Meanwhile, the AGC input signal AGC_IN_I / Q is stored in the N + 3 register 420.

Subsequently, the signal output from the N + 2 register 410 and the signal output from the N + 3 register 420 are multiplied by each other in the N + 1 and N + 2 multipliers 430 and 440. Next, AGC_OUT_I / Q signals are output.

As described above, the present invention can improve the performance of the digital automatic gain controller by compensating the nonlinear characteristics of the multiplier structurally, and also can ensure the flexibility in hardware implementation and facilitate the design.

Claims (2)

In a digital AGC equipped with a loop filter, A first register receiving the output signal LOOP_OUT of the loop filter; A first multiplier comprising a register which receives an AGC input signal (AGC_IN_I / Q) and first and second multipliers that receive and multiply signals output from the first and second registers; A third register receiving the signal output from the first register, a fourth register receiving the signal output from the first and second multipliers of the first multiplier, and a signal output from the third and fourth registers; A second multiplier consisting of third and fourth multiplication units to multiply; N + 2 register receiving a signal output from the Nth register and a 2N register receiving a signal output from the N-1, N-2 multiplier of the N-1 multiplier and the N + 2, 2N A multiplier according to claim 1, wherein the multiplier comprises an N + 3 multiplier comprising N + 3 and N + 4 multipliers that receive and multiply the signal output from the register to output the AGC_OUT_I / Q signal. In a digital AGC equipped with a loop filter, A squarer including a first register to receive the output signal LOOP_OUT of the loop filter and a first multiplier to receive and multiply the signal output from the first register; A multiplier comprising a third and fourth registers receiving the signals output from the first multiplier of the squarer and a second multiplier for receiving and multiplying the signals output from the third and fourth registers; N-th and N + 1 registers receiving the signals output from the N-th multiplier of the N-1th power, respectively, and N-th multipliers that receive and multiply the signals output from the N-th and N + 1 registers. The Nth carriage; N + 2 register receiving the signal output from the Nth multiplier of the Nth multiplier and N + 3 register receiving the input signal AGC_IN_I / Q of AGC and the N + 2, N + 3 register A multiplier of claim 1, wherein the multiplier comprises N + 1 and N + 2 multipliers for outputting AGC_OUT_I / Q signals.