KR100343467B1 - Java processor - Google Patents

Abstract

The present invention relates to a Java processor. In the prior art, if the Java processor does not have a SIMD instruction and the data path does not support the SIMD structure, 64 loops are performed eight times for an 8-bit addition operation in a 32-bit data path. Since the operation speed is slowed down and the data path is controlled to operate only one at a time, the floating point calculation consumes a maximum of 2000 cycles. The sub-operation waits for up to 2000 cycles, resulting in inefficient problems. Accordingly, the present invention provides a control unit for controlling a folded instruction having a current destination address, which has no data dependency from a previous instruction, and issues an issue when the data path operator to be allocated is at rest in an execution step; The conventional stack cache structure is further configured by receiving an output_ready signal from each operator in the data path, sending a necessary mux selec- tion signal to the mux, and further including an output controller for managing a state of the current operator. There is an effect that the data path operators of the existing Java processor can be used simultaneously for selectively folded and destination addressed instructions without changing.

Description

Java processor {JAVA PROCESSOR}

TECHNICAL FIELD The present invention relates to a Java processor, and more particularly, to a Java processor capable of simultaneously processing multiple data paths having different operation cycles without changing a stack cache structure.

1 is a block diagram showing a configuration of a conventional Java processor, as shown therein; a bus interface unit 10 for inputting and outputting data between external input / output devices through a bus; A command cache 20 for decoding and outputting a command through the bus interface unit 10; An input buffer 30 for buffering and outputting the decoded command and data; An integer unit (70) and a floating point unit (50) for performing an operation corresponding to the command from the data input through the input buffer (30); A data cache (60) for storing the results of the integer unit (70) and the floating point unit (50) and inputting and outputting the result to the bus interface unit (10); The stack controller 40 controls data input / output of the data cache 60, the integer unit 70, and the floating point unit 50.

The integer unit 70 includes: a folding unit 71 for folding data and instructions from the input buffer 30; A register control unit 72 for storing data and instructions folded by the folding unit 71; A stack cache (73) for storing data and instructions stored in the register controller (72) under the control of the stack controller (40); An arithmetic operation and shifter unit 74 for adding or subtracting data stored in the stack cache 73; A multiplication and division unit 75 for multiplying and dividing data stored in the stack cache 73; A multiplexer (76) which receives arithmetic results of the floating point unit (50), arithmetic operation and shifter unit (74) or multiplication and division unit (75), and selects and outputs them; It consists of a multiplexer 77 which receives the output signal of the data cache 60 and the multiplexer 76 and selects and outputs the output signal. The operation of one embodiment according to the prior art configured as described above is as follows.

In general, conventional Java technology can operate only one of several data paths at a time, and does not support a single instruction multi-data (SIMD) instruction.

In Fig. 1, the portions represented by the arithmetic and shifter 74, the multiplication and division 75 and the floating point 50 are data paths, and only one of them is operated at one instant. .

However, because the data paths complete their operations in 1 cycle, 2-32 cycles, and up to 2000 cycles, respectively, a structure in which only one data path operates at a time is inefficient.

In addition, if the 8-bit data is continuously input because the SIMD operation is not supported, a large portion of the 32-bit data path is stopped.

As described above, in the conventional technology, when the Java processor does not have a SIMD instruction and the data path does not support the SIMD structure, 64 8-bit addition operations are performed on a 32-bit data path. In the case of floating point calculations, when the instruction consumes up to 2000 cycles, the arithmetic and shifter operations can be up to 2000 after the floating point part operation because the speed is reduced and the data path is controlled to operate only one at a time. There was an inefficient problem to wait for the cycle.

Accordingly, the present invention has been created to solve the above-mentioned conventional problems, and allows Java to improve the computational efficiency by allowing parallel processing of a plurality of data paths having different operation cycles without significant change in the conventional structure. The purpose is to provide a processor.

1 is a block diagram showing the configuration of a conventional Java processor.

2 shows an example of stack cache comparisons for operations with and without destination addresses.

Figure 3 is a block diagram showing the configuration of a Java processor according to the present invention.

4 is a block diagram showing a detailed configuration of the issue control unit and the output control unit in FIG.

*** Description of the symbols for the main parts of the drawings ***

100: issue control unit 100a: folding and group inspection unit

100b: decoding 100c: data path allocation unit

100d: Issue controller 100e: Data path idle check unit

200: output control unit

The present invention for achieving the above object is an issue in the Java processor, when the folded instruction having the current destination address has no data dependency with the previous instruction and the data path operator to be allocated is resting at execution stage. Issue control unit for controlling to issue; And an output controller configured to receive an output_ready signal from each operator of the data path, to send a necessary mux selec- tion signal to the mux, and to manage a state of the current operator.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention solves the limitation that a conventional Java processor must operate only one of the data path units at a moment in the execution stage of the pipeline, thereby enabling a plurality of data path units to be operated in the execution stage of the Java processor. 'To improve.

However, since it is possible to develop a new Java processor when it is possible for all instructions, the present invention maintains the structure of the stack cache of the existing Java processor, while folding and changing some control circuits to a minimum, and the destination address. (destination address) is a control structure that allows the simultaneous use of multiple operators in the data path if there is no data dependency on the previous command.

Once, according to the present invention, the instruction format that can use data paths in parallel is limited to instructions having a destination address.

For example, the operation of 'V <= u × w' and 'Z <= x + y' is divided into a case of using an instruction having a destination address and an instruction having no instruction, and the result is shown as shown in FIG.

As shown in (a) of FIG. 2, when the target address is included, the result value is immediately moved to the corresponding variable position in the VARS region without putting the operation result in OP_TOP.

Therefore, the position of OP_TOP in the stack cache is not changed.

On the other hand, if there is no destination address, as shown in (b) of FIG. 2, operation results (V and Z) are stored in an arbitrary area of the stack cache. Has the property to depend on.

In other words, the present invention is characterized by maintaining several data paths in an active state at the same time, the structure is not interested before and after the end of the calculator.

3 is a block diagram showing the configuration of a Java processor according to the present invention. In the conventional configuration, as shown therein, a folded instruction having a current destination address has no data dependency on the previous instruction and is allocated. An issue control unit 100 which controls to issue when the data path operator to be rested in the execution phase; And an output control unit 200 which receives an output ready signal from each operator of the data path, sends a necessary mux selection signal Mux_sel to the mux, and manages the state of the current operator.

Here, the issue control unit 100 may include a folding and group checking unit 100a which checks whether a folding group of instructions supplied into the processor is present; A decoding unit 100b for determining which instruction; A data path assignment unit (100c) for allocating an appropriate data path of the decoded instruction; A data path idle check unit 100e for checking whether a specific data path is in an idle state; It consists of an issue controller (100d) for controlling so that each process can be performed properly.

Next, the configuration and operation of the issue control unit 100 and the output control unit 200 will be described with reference to FIG. 4.

The Java processor is a Java language-only processor that receives and processes byte codes. The pair of instructions is divided into one of nine groups, and the instructions in this category are reorganized into one new instruction. do.

The folded Java instructions are issued into the processor at each pipeline stage.

When fed into the processor, the instructions are checked for their folding group, decoded which instructions and then assigned to the appropriate data path.

The idle check is performed by passing a value indicating whether each data path is in an idle state in the output control unit 200 of FIG. That is, when the issue control unit 100 supplies a new command, the allocated data path information is provided to the output control unit 200 by the data path information signal issued DP_ID, and the output control unit 200 idles the idle state signal. DP_id indicates to the issue controller 100 whether the data path is in an idle state. In other words, the data path information signal issued DP_ID is a signal output from the issue controller 100 to the output controller 200. Contains data path information allocated according to the type of the input command, and updates the internal database containing information on whether the output control unit 200 has assigned a data path. idle DP_id) is a signal output from the output control unit 200 to the issue control unit 100, and receives the output preparation signal Output_ready from the data pass to the internal data. It updates the data and notifies the issue controller 100 of the data path information in the idle state. In addition, when a command is supplied to the stack cache, a space for supplying necessary variables and data must be managed. It provides a pointer called OP_TOP.

That is, the folding and group checking unit 100a checks the command value that the input command can use the data path at the same time. Here, the checking of the command group may have various methods, but the command may be required according to the type. By using different data paths, users can easily distinguish between groups of commands by pre-dividing the types into a database and checking whether they match each time a command is entered. If it turns out to be a missing instruction family, the issue halts until all operators in the data path are idle at the execution stage.

Once the instruction is folded and the instruction has a destination address, decoding and data path allocation proceed.

At this time, if there is no data dependency on previous instructions being executed and the specified data path is idle in the execution phase, an issue is issued.

If a command is issued to the data path, the data path information allocated to the output control unit 200 is output using the data path information signal Issued_DP_ID, thereby updating the value of the table that the output control unit 200 has.

At this time, the idle state is utilized by the information of the data path idle check unit 100e.

The data path idle check unit 100e is updated with reference to an idle state signal id DP_id derived from the values shown in the table of the output control unit 200.

Next, the output control unit 200 sets a value indicating whether each data path is occupied at the execution stage, and a database configuration (FPU: 1, Mult / div: 1, ALU) as shown in the table shown in the output control unit of FIG. / shift: 0). This value is changed by the data path information signal Issued_DP_ID of the issue control unit 100 and the output ready signal output_ready from the signal associated with each data path.

If the value of the data path information signal Issued_DP_ID is displayed for the data path, the state of the corresponding operator in the table becomes 1, and when the execution of the operator is completed, it changes to 0.

This value outputs a mux selection signal mux_sel so that the mux of the output terminal can detect the value, and also outputs the updated state value of the corresponding operator to the data path idle check unit 100e of the issue control unit 100.

As described above, the Java processor of the present invention has the effect of selectively using data path operators of the existing Java processor selectively for the folded and the destination addressed instruction without changing the conventional stack cache structure.

Claims (2)

1. A Java processor, comprising: an issue control unit for controlling a folded instruction having a current destination address to have no data dependency with a previous instruction and to issue an issue when the data path operator to be allocated is at rest in an execution step; And an output control unit which receives an output_ready signal from each operator of the data path, sends a necessary mux selec- tion signal to the mux, and further manages the state of the current operator. The apparatus of claim 1, wherein the issue controller comprises: a folding and group checking unit configured to check whether or not a folding group of instructions supplied into a processor is present; A decoding unit for determining which instruction; A data path assignment unit for allocating an appropriate data path of the decoded instruction; A data path idle check unit for checking whether a specific data path is in an idle state; Java processor, characterized in that consisting of an issue controller for controlling so that each process can be performed properly.