KR100341124B1 - Method for manufacturing LCD having high aperture ratio and high transmittance - Google Patents
Method for manufacturing LCD having high aperture ratio and high transmittance Download PDFInfo
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- KR100341124B1 KR100341124B1 KR1019990012823A KR19990012823A KR100341124B1 KR 100341124 B1 KR100341124 B1 KR 100341124B1 KR 1019990012823 A KR1019990012823 A KR 1019990012823A KR 19990012823 A KR19990012823 A KR 19990012823A KR 100341124 B1 KR100341124 B1 KR 100341124B1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000002834 transmittance Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010408 film Substances 0.000 claims abstract description 79
- 239000010410 layer Substances 0.000 claims abstract description 47
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 244000126211 Hericium coralloides Species 0.000 claims abstract description 3
- 239000011241 protective layer Substances 0.000 claims abstract description 3
- 230000001681 protective effect Effects 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000583 Nd alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
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Abstract
본 발명은 고개구율 및 고투과율 액정 표시 장치의 제조방법을 개시한다. 개시된 본 발명은, 투명 절연 기판상에 투명 전도막을 증착하고, 소정 부분 패터닝하여 카운터 전극을 형성하는 단계와, 투명 절연 기판 상에 일방향으로 연장된 게이트 버스 라인과, 상기 카운터 전극과 콘택되는 공통 전극선 및 절연 기판 외곽에 게이트 패드를 동시에 형성하는 단계와, 결과물상에 게이트 절연막과 비정질 실리콘층 및 도핑된 반도체층을 순차적으로 적층한다음, 도핑된 반도체층과 비정질 실리콘층을 소정 부분 식각하여, 박막 트랜지스터 영역을 한정하는 단계와, 상기 투명 절연 기판 결과물상에 데이터 버스 라인용 금속막을 증착한다음, 소정 부분 식각하여 상기 박막 트랜지스터 영역에 소오스, 드레인 전극을 형성하고, 상기 게이트 버스 라인과 교차되도록 데이터 버스 라인을 형성함과 동시에 상기 게이트 패드가 형성된 부분에 게이트 패드의 소정 부분만을 덮도록 데이터 패드를 형성하는 단계와, 상기 투명 절연 기판 상부에 절연층 보호막을 형성하고, 상기 드레인 전극의 소정 부분을 오픈시킴과 동시에, 데이터 패드 및 게이트 패드 부분을 오픈시키는 단계, 및 상기 노출된 드레인 전극 및 패드 부분들과 콘택되면서, 상기 절연층 보호막 상부에 투명 전도막을 형성하고, 이 투명 전도막을 소정 부분 패터닝하여 빗살 형태의 화소 전극을 형성하는 단계를 포함한다.The present invention discloses a method of manufacturing a high opening ratio and a high transmittance liquid crystal display. According to the present invention, the method includes depositing a transparent conductive film on a transparent insulating substrate, patterning a predetermined portion to form a counter electrode, a gate bus line extending in one direction on the transparent insulating substrate, and a common electrode line in contact with the counter electrode. And simultaneously forming a gate pad on an outer surface of the insulating substrate, sequentially laminating a gate insulating film, an amorphous silicon layer, and a doped semiconductor layer on the resultant, and etching a predetermined portion of the doped semiconductor layer and the amorphous silicon layer. Defining a transistor region, depositing a metal layer for a data bus line on the resultant transparent insulating substrate, and etching a predetermined portion to form a source and a drain electrode in the thin film transistor region, and to intersect the gate bus line. A portion where the gate pad is formed at the same time as forming a bus line Forming a data pad to cover only a predetermined portion of the gate pad, forming an insulating layer protective layer on the transparent insulating substrate, opening a predetermined portion of the drain electrode, and opening the data pad and the gate pad portion. And forming a transparent conductive film over the insulating layer protection layer while contacting the exposed drain electrode and pad portions, and patterning the transparent conductive film by a predetermined portion to form a comb-tooth shaped pixel electrode.
Description
본 발명은 액정 표시 장치의 제조방법에 관한 것으로, 보다 구체적으로는 포토리소그라피 공정수를 줄일 수 있는 프린지 필드(fringe field switching)로 스위칭하는 고개구율 및 고투과율 액정 표시 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display, and more particularly, to a method for manufacturing a high opening ratio and a high transmittance liquid crystal display for switching to fringe field switching, which can reduce the number of photolithography processes.
일반적으로 프린지 필드(fringe field)에 의하여 동작되는 고개구율 및 고투과율 액정 표시 장치는 일반적인 IPS 모드 액정 표시 장치의 낮은 개구율 및 투과율을 개선시키기 위하여, 대한민국 특허출원 98-9243호로 출원되었다.In general, a high aperture ratio and high transmittance liquid crystal display device operated by a fringe field has been filed in Korean Patent Application No. 98-9243 to improve the low aperture ratio and transmittance of a general IPS mode liquid crystal display device.
이러한 고개구율 및 고투과율 액정 표시 장치는 카운터 전극과 화소 전극을 투명 전도체로 형성하면서 카운터 전극과 화소 전극과의 간격을 상하 기판 사이의 간격보다 좁게 형성하여 카운터 전극과 화소 전극 상부에 프린지 필드(fringe filed)가 형성되도록 하므로써, 전극들 상부에 존재하는 액정 분자들이 모두 동작되도록 한다.Such a high aperture ratio and high transmittance liquid crystal display forms a counter electrode and a pixel electrode with a transparent conductor, and forms a gap between the counter electrode and the pixel electrode to be smaller than the gap between the upper and lower substrates, thereby forming a fringe field on the counter electrode and the pixel electrode. By forming the filed), all of the liquid crystal molecules present on the electrodes are operated.
이러한 종래의 고개구율 및 고투과율 액정 표시 장치의 제조방법을 도 1 내지 도 3을 참조하여 설명하면 다음과 같다.도 1은 종래의 액정 표시 장치의 박막 트랜지스터 부분을 나타낸 단면도이고, 도 2는 종래의 액정 표시 장치의 화소부를 나타낸 단면도이며, 도 3은 종래의 액정 표시 장치의 패드 부분을 나타낸 단면도이다.Referring to FIGS. 1 to 3, a method of manufacturing a conventional high aperture and high transmittance liquid crystal display is as follows. FIG. 1 is a cross-sectional view of a thin film transistor of a conventional liquid crystal display, and FIG. Is a cross-sectional view showing a pixel portion of a liquid crystal display device, and FIG. 3 is a cross-sectional view showing a pad portion of a conventional liquid crystal display device.
종래기술에 따른 고개구율 및 고투과율 액정표시장치의 제조방법은, 도 1 및 도 2에 도시된 바와같이, 투명성 절연 기판(1) 상부에 ITO(indium tin oxide)를 Ar 가스, O2가스 및 ITO 타겟을 이용하여 스퍼터링 방식으로 형성한다음, 빗살 형태를 이루도록 패터닝하여 카운터 전극(2)을 형성한다(제 1 마스크 공정).In the method of manufacturing a high aperture and high transmittance liquid crystal display according to the related art, as shown in FIGS. 1 and 2, indium tin oxide (ITO) is disposed on the transparent insulating substrate 1, and Ar gas, O 2 gas, and the like. The counter electrode 2 is formed by sputtering using an ITO target and then patterned to form a comb tooth (first mask process).
그다음, 카운터전극(2)이 형성된 투명 절연기판(1)상부에 절연막(3)을 증착한후, 그 상부에 불투명 금속막을 스퍼터링 방식으로 형성한다음, 소정부분을 패터닝하여 게이트버스라인(4)과 공통 전극선(도시되지 않음)을 형성한다. 이때, 공통 전극선은 카운터전극(2)과 콘택되도록 형성한다(제 2 마스크 공정).이어서, 게이트 버스라인이 형성된 투명절연기판(1)상부에 게이트 절연막(5)과 비정질 실리콘막 및 실리콘 질화막을 순차적으로 적층한다음, 실리콘 질화막을 소정 부분 패터닝하여 에치 스톱퍼(6)를 형성한다(제 3 마스크 공정).Next, after the insulating film 3 is deposited on the transparent insulating substrate 1 on which the counter electrode 2 is formed, an opaque metal film is formed thereon by sputtering, and then a predetermined portion is patterned to form the gate bus line 4. And a common electrode line (not shown). In this case, the common electrode line is formed to be in contact with the counter electrode 2 (second mask process). A gate insulating film 5, an amorphous silicon film, and a silicon nitride film are formed on the transparent insulating substrate 1 on which the gate bus lines are formed. After sequentially stacking, the silicon nitride film is patterned by a predetermined portion to form an etch stopper 6 (third mask process).
그다음, 에치 스톱퍼(6)가 형성된 비정질 실리콘층 상부에 불순물이 도핑된 비정질 실리콘막을 PECVD(plasma enhanced chemical vapor deposition) 방식으로 형성한다음, 도핑된 비정질 실리콘막과 비정질 실리콘막을 패터닝하여 채널층(7)과 오믹 콘택층(8)을 형성한다(제 4 마스크 공정).Then, an amorphous silicon film doped with impurities on the amorphous silicon layer having the etch stopper 6 formed thereon is formed by a plasma enhanced chemical vapor deposition (PECVD) method, and then the doped amorphous silicon film and the amorphous silicon film are patterned to form a channel layer 7. ) And the ohmic contact layer 8 are formed (fourth mask step).
이어서, 결과물 상부에 ITO층을 스퍼터링 방식으로 증착한다음, 빗살 형태로 형성하되, 카운터 전극(2)의 빗살 사이에 배치되도록 패터닝하여 화소 전극(9)을 형성한다(제 5 마스크 공정).Subsequently, the ITO layer is deposited on the resultant by sputtering, and then formed in the shape of a comb, and patterned to be disposed between the comb teeth of the counter electrode 2 to form the pixel electrode 9 (a fifth mask process).
그다음, 도 3에 도시된 바와 같이, 게이트 패드부(4a) 위의 게이트 절연막을 제거하여 패드(미도시)를 오픈시킨다(제 6 마스크 공정).3, the gate insulating film on the gate pad portion 4a is removed to open the pad (not shown) (a sixth mask process).
이어서, 결과물 상부에 불투명 금속막을 스퍼터링 방식으로 증착한다음, 불투명금속막의 소정 부분을 식각하여 소오스, 드레인 전극(10a,10b) 및 데이터 버스 라인(도시되지 않음)을 형성한다(제 7 마스크 공정).그다음, 상기 에치 스톱퍼(6) 상부에 잔존하는 오믹 콘택층을 공지의 방식으로 제거한다. 이때, 오픈되어진 게이트 패드부(4a)와 데이터 버스 라인용 금속막 (10)이 콘택되어진다.Subsequently, an opaque metal film is deposited on the resultant by sputtering, and then a portion of the opaque metal film is etched to form a source, drain electrodes 10a and 10b and a data bus line (not shown) (seventh mask process). Then, the ohmic contact layer remaining on the etch stopper 6 is removed in a known manner. At this time, the gate pad portion 4a opened and the metal film 10 for data bus line are contacted.
이어서, 기판 결과물 상부에 SiN으로 된 절연층보호막(100)을 증착한다음, 게이트 패드부(4a)와 데이터 버스 라인(10)이 오픈되도록 절연층 보호막(100)의 일부분을 제거하여 하부 기판 공정을 마친다(제 8 마스크 공정).Subsequently, an insulating layer protective film 100 made of SiN is deposited on the substrate, and then a portion of the insulating layer protective film 100 is removed to open the gate pad portion 4a and the data bus line 10. To finish (eighth mask process).
그러나, 상기와 같은 고개구율 및 고투과율 액정 표시 장치의 하부 기판 구조물을 형성함에 있어 상술한 바와 같이 8번의 마스크 공정이 요구된다.However, in forming the lower substrate structure of the high aperture ratio and high transmittance liquid crystal display device as described above, eight mask processes are required as described above.
이때, 상기 마스크 공정이라 함은 공지된 바와 같이 포토리소그라피 공정으로, 그 자체 공정만으로도 레지스트 도포 공정, 노광 공정, 현상 공정, 식각 공정, 레지스트 제거공정을 포함한다. 이에 따라, 한 번의 마스크 공정을 진행하는데 장시간이 소요된다.In this case, the mask process is a photolithography process as known, and includes a resist coating process, an exposure process, a developing process, an etching process, and a resist removing process only by its own process. Accordingly, it takes a long time to proceed with one mask process.
이로 인하여, 8번의 마스크 공정을 포함하는 고개구율 및 고투과율 액정 표시 장치를 제조하는데 매우 긴 시간이 요구되고, 제조 비용이 상승하게 되므로써 수율이 저하된다.For this reason, very long time is required for manufacturing the high opening ratio and high transmittance liquid crystal display device including the eight mask processes, and the manufacturing cost rises, and the yield falls.
따라서, 본 발명은 상기 종래기술의 문제점을 해결하기 위한 것으로, 프린지 필드 스위칭하는 액정 표시 장치의 제조시에, 마스크 공정수를 줄여 제조공정시간을 단축시키고 생산수율을 증대시킬 수 있는 고개구율 및 고투과율 액정 표시 장치의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the problems of the prior art, in the manufacture of a fringe field switching liquid crystal display device, a high opening rate and high that can shorten the manufacturing process time and increase the production yield by reducing the number of mask processes It is an object of the present invention to provide a method for manufacturing a transmittance liquid crystal display device.
도 1은 종래의 고개구율 및 고투과율 액정 표시 장치의 박막 트랜지스터 부분을 나타낸 단면도.1 is a cross-sectional view showing a thin film transistor portion of a conventional high aperture and high transmittance liquid crystal display.
도 2는 종래의 고개구율 및 고투과율 액정 표시 장치의 화소부를 나타낸 단면도.2 is a cross-sectional view showing a pixel portion of a conventional high aperture and high transmittance liquid crystal display device;
도 3은 종래의 고개구율 및 고투과율 액정 표시 장치의 패드 부분을 나타낸 단면도.3 is a cross-sectional view showing a pad portion of a conventional high opening ratio and high transmittance liquid crystal display device;
도 4는 본 발명에 따른 고개구율 및 고투과율 액정 표시 장치의 박막 트랜지스터를 나타낸 단면도.4 is a cross-sectional view of a thin film transistor of a high aperture and high transmittance liquid crystal display according to the present invention;
도 5는 본 발명에 따른 고개구율 및 고투과율 액정 표시 장치의 화소부를 나타낸 단면도.5 is a cross-sectional view of a pixel part of a high aperture ratio and high transmittance liquid crystal display device according to the present invention;
도 6은 본 발명에 따른 고개구율 및 고투과율 액정 표시 장치의 패드부를 나타낸 평면도.6 is a plan view illustrating a pad part of a high opening ratio and a high transmittance liquid crystal display according to the present invention;
도 7은 본 발명에 따른 도 6의 Ⅶ-Ⅶ'선을 따라 절단한 단면도.7 is a cross-sectional view taken along the line VII-VII 'of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 - 투명 절연 기판 12 - 카운터 전극11-transparent insulated substrate 12-counter electrode
13 - 기판 보호막 14 - 게이트 버스 라인13-Board Shield 14-Gate Bus Line
14a - 게이트 패드 15 - 게이트 절연막14a-gate pad 15-gate insulating film
16 - 실리콘 질화막 17 - 비정질 실리콘막16-silicon nitride film 17-amorphous silicon film
18 - 도핑된 반도체층 19a,19b - 소오스, 드레인 전극18-doped semiconductor layer 19a, 19b-source, drain electrode
20 - 데이터 버스 라인 20a - 데이터 패드20-Data Bus Line 20a-Data Pad
21 - 절연층 보호막 22- 화소 전극21-insulating layer protective film 22- pixel electrode
상기 목적을 달성하기 위한 본 발명에 따른 고개구율 및 고투과율 액정표시장치의 제조방법은, 카운터전극과 화소전극사이에 프린지 필드를 형성시켜 동작하는 고개구율 및 고투과율을 갖는 액정 표시 장치의 제조방법에 있어서, 투명 절연 기판상에 투명 전도막을 증착하고, 투명전도막의 소정 부분을 패터닝하여 카운터 전극을 형성하는 제1마스크공정; 상기 카운터 전극이 형성된 투명 절연 기판 상에 일방향으로 연장된 게이트 버스 라인과, 상기 카운터 전극과 콘택되는 공통 전극선 및 절연 기판 외곽에 게이트 패드를 동시에 형성하는 제2마스크공정; 상기 결과물상에 게이트 절연막과 비정질 실리콘층 및 도핑된 반도체층을 순차적으로 적층한후, 도핑된 반도체층과 비정질 실리콘층의 소정부분을 식각하여 박막 트랜지스터 영역을 한정하는 제3마스크공정; 상기 투명 절연 기판 결과물상에 데이터 버스 라인용 금속막을 증착한후 금속막의 소정부분을 식각하여 상기 박막트랜지스터 영역에 소오스 및 드레인 전극을 형성하고, 상기 게이트 버스 라인과 교차되도록 데이터 버스 라인을 형성함과 동시에 상기 게이트 패드가 형성된 부분에 게이트 패드의 소정 부분만을 덮도록 데이터 패드를 형성하는 제4마스크공정; 상기 투명 절연 기판 상부에 절연층 보호막을 형성하고, 상기 드레인 전극의 소정부분을 오픈시킴과 동시에 상기 데이터 패드 및 게이트 패드 부분을 오픈시키는 제5마스크공정; 및 상기 노출된 드레인 전극 및 패드 부분들과 콘택되면서 상기 절연층 보호막 상부에 투명 전도막을 형성하고, 상기 투명 전도막의 소정부분을 패터닝하여 빗살 형태의 화소 전극을 형성하는 제6마스크공정을 포함하여 구성되는 것을 특징으로한다.In order to achieve the above object, a method of manufacturing a high aperture ratio and high transmittance liquid crystal display according to the present invention includes a method of manufacturing a liquid crystal display having high aperture ratio and high transmittance, which is formed by forming a fringe field between a counter electrode and a pixel electrode. A first mask process comprising: forming a counter electrode by depositing a transparent conductive film on a transparent insulating substrate and patterning a predetermined portion of the transparent conductive film; A second mask process of simultaneously forming a gate bus line extending in one direction on the transparent insulating substrate on which the counter electrode is formed, a common electrode line contacting the counter electrode, and a gate pad outside the insulating substrate; A third mask process of sequentially depositing a gate insulating film, an amorphous silicon layer, and a doped semiconductor layer on the resultant, and then etching a predetermined portion of the doped semiconductor layer and the amorphous silicon layer to define a thin film transistor region; Depositing a metal film for a data bus line on the resultant of the transparent insulating substrate, etching a predetermined portion of the metal film to form source and drain electrodes in the thin film transistor region, and forming a data bus line to cross the gate bus line; A fourth mask process of forming a data pad at the same time to cover only a predetermined portion of the gate pad on a portion where the gate pad is formed; Forming a protective layer over the transparent insulating substrate, opening a predetermined portion of the drain electrode, and simultaneously opening the data pad and the gate pad; And a sixth mask process of forming a transparent conductive film on the insulating layer protection layer while contacting the exposed drain electrode and pad portions, and patterning a predetermined portion of the transparent conductive film to form a comb-shaped pixel electrode. It is characterized by.
본 발명에 의하면, 에치 스톱퍼를 형성하는 공정과 절연층 보호막 형성후 패드 오픈시키는 공정을 배제하므로써, 종래보다 2개의 마스크를 줄일 수 있다.According to the present invention, by eliminating the step of forming the etch stopper and the step of opening the pad after formation of the insulating layer protective film, two masks can be reduced than before.
(실시예)(Example)
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 자세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명에 따른 고개구율 및 고투과율 액정 표시 장치의 박막 트랜지스터를 나타낸 단면도이고, 도 5는 본 발명에 따른 고개구율 및 고투과율 액정 표시 장치의 화소부를 나타낸 단면도이다. 도 6은 본 발명에 따른 고개구율 및 고투과율 액정 표시 장치의 패드부를 나타낸 평면도이고, 도 7은 본 발명에 따른 도 6의 Ⅶ-Ⅶ'선을 따라 절단한 단면도이다.4 is a cross-sectional view illustrating a thin film transistor of a high aperture and high transmittance liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of a pixel portion of a high aperture and high transmittance liquid crystal display according to an exemplary embodiment of the present invention. 6 is a plan view illustrating a pad part of a high aperture ratio and high transmittance liquid crystal display according to the present invention, and FIG. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. 6 according to the present invention.
본 발명에 따른 고개구율 및 고투과율 액정표시장치의 제조방법은, 도 4 및 도 5에 도시된 바와같이, 투명 절연기판(11)상부에 ITO층을 Ar 가스나 O2가스 및 ITO 타겟을 이용하여 스퍼터링 방식으로 소정 두께만큼 형성한다.그다음, 제 1 마스크 공정을 통하여 ITO층을 사각판 형태 또는 빗살 형태로 식각하여 카운터 전극(12)을 형성한다. 이때, ITO층은 HCl, HNO3, 및 H2O 케미컬에 의한 습식 식각 방식으로 패터닝하는 것이 바람직하다.In the method of manufacturing a high aperture and high transmittance liquid crystal display device according to the present invention, as shown in FIGS. 4 and 5, an ITO layer is used on the transparent insulating substrate 11 using an Ar gas, an O 2 gas, and an ITO target. And a predetermined thickness by sputtering. Then, the counter electrode 12 is formed by etching the ITO layer in the form of a square plate or a comb through the first mask process. In this case, the ITO layer is preferably patterned by a wet etching method using HCl, HNO 3 , and H 2 O chemicals.
이어서, SiH4가스와, O2가스 및 N2가스를 이용하여 APCVD 방식으로 절연 기판(11) 상부에 실리콘산화막으로 된 기판 보호막(13)을 형성한다. 이때, 보호막(13)은 유리기판내의 유기물이 소자에 영향을 미치는 것을 방지하는 역할을 한다.Subsequently, a substrate protective film 13 made of a silicon oxide film is formed on the insulating substrate 11 by APCVD using SiH 4 gas, O 2 gas, and N 2 gas. At this time, the protective film 13 serves to prevent the organic material in the glass substrate from affecting the device.
그다음, MoW 금속막, Al-Nd 합금막 또는 Mo/Al의 적층막을 기판 결과물 상부에 스퍼터링 방식으로 증착한다음, 제 2 마스크 공정을 통하여 일방향으로 연장된 게이트 버스 라인의 형태를 식각하여 게이트 버스 라인(14)을 형성한다. 이때, 상기 식각공정시에, Al 계열 금속막 또는 Mo/Al 금속막으로 게이트 버스 라인(14)을 형성할 경우에는 H3PO4, CH3COOH,HNO3, 및 H2O로 이루어진 에천트를 이용하여 습식 식각하고, MoW 금속막으로 게이트 버스 라인(14)을 형성할 경우에는 SF6가스나 CF4및 O2가스를 이용하여 건식 식각하여 주는 것이 바람직하다.Next, a MoW metal film, an Al-Nd alloy film, or a Mo / Al laminate film is deposited on the substrate by sputtering, and the gate bus line is etched by etching the shape of the gate bus line extending in one direction through the second mask process. (14) is formed. At this time, when the gate bus line 14 is formed of an Al-based metal film or an Mo / Al metal film during the etching process, an etchant including H 3 PO 4 , CH 3 COOH, HNO 3 , and H 2 O is used. In the case of wet etching, and when forming the gate bus line 14 with the MoW metal film, it is preferable to dry-etch using SF 6 gas or CF 4 and O 2 gas.
또한, 게이트버스라인(14)을 형성하는 공정과 동시에, 카운터전극(12)에 공통신호를 전달하는 공통전극선(도시되지 않음)이 형성되며, 기판 외측에는 외부 단자와 연결되어질 패드부(14a)가 형성된다(도 6에 도시됨).In addition, at the same time as the process of forming the gate bus line 14, a common electrode line (not shown) for transmitting a common signal to the counter electrode 12 is formed, the pad portion 14a to be connected to the external terminal on the outside of the substrate Is formed (shown in FIG. 6).
이어서, 결과물 상부에 실리콘 질산화막(SiON:15)과 실리콘 질화막(SiN:16)과 비정질실리콘막(a-Si:17) 및 도핑된 반도체층(n+a-si:18)을 PECVD(plasma enhacned chemical vapor deposition) 방식으로 적층한다.그다음, 제 3 마스크 공정을 진행하여 상기 도핑된 반도체층(18)과 비정질 실리콘층(17) 및 실리콘 질화막(16)의 소정부분을 SF6,He, HCl 가스를 이용하여 패터닝하여 박막 트랜지스터 영역을 한정한다.Subsequently, a silicon nitride oxide film (SiON: 15), a silicon nitride film (SiN: 16), an amorphous silicon film (a-Si: 17), and a doped semiconductor layer (n + a-si: 18) were formed on top of the resultant plasma. the stacked enhacned chemical vapor deposition) method. then, the third forward masking process to a predetermined portion of the doped semiconductor layer 18 and the amorphous silicon layer 17 and silicon nitride film (16), SF 6, He, HCl Patterning with gas is used to define the thin film transistor region.
이어서, 도핑된 반도체층(18)상에 데이터 버스 라인용 금속막 예를들어, Mo/Al/Mo 적층이나 MoW과 같은 불투명 금속막을 Kr 가스나 Ar 가스와 MoW 타겟, Mo 타겟 또는 Al 타겟을 이용하여 스퍼터링 방식으로 형성한다. 이때, 데이터 버스 라인용 금속막으로는 Al 계열의 금속막은 이용하지 않는 것이 좋다. 이는 이후의 화소 전극 형성시에 Al 금속막이 영향을 받기 때문이다.Subsequently, a metal film for a data bus line, for example, a Mo / Al / Mo stack or an opaque metal film such as MoW, is formed on the doped semiconductor layer 18 using Kr gas, Ar gas, MoW target, Mo target, or Al target. To form a sputtering method. At this time, it is preferable not to use an Al-based metal film as the data bus line metal film. This is because the Al metal film is affected during the subsequent pixel electrode formation.
그다음, 제 4 마스크 공정에 의해 상기 불투명 금속막을 패터닝하여 소오스, 드레인 전극(19a,19b)과 데이터 버스 라인(20)을 형성한다. 이때, 상기 데이터 버스 라인(20)이 Mo/Al/Mo의 적층막으로 구성되는 경우에는 H3PO4, CH3COOH,HNO3, 및 H2O로 이루어진 에천트를 이용하여 습식 식각하고, MoW 금속막을 이용할 경우에는 SF6가스나 CF4및 O2가스를 이용하여 건식 식각할 수 있다.The opaque metal film is then patterned by a fourth mask process to form the source, drain electrodes 19a and 19b and the data bus line 20. At this time, when the data bus line 20 is formed of a laminated film of Mo / Al / Mo wet etching using an etchant consisting of H 3 PO 4 , CH 3 COOH, HNO 3 , and H 2 O, When the MoW metal film is used, dry etching may be performed using SF 6 gas or CF 4 and O 2 gas.
이때, 상기 데이터버스라인(20)은, 도 6 및 도 7에 도시된 바와 같이, 게이트패드부(14a)와 오버랩되도록 연장되어 데이터패드부(20a)를 형성한다. 여기서, 상기 데이터패드부(20a)는 게이트패드부(14a)의 2분의 1정도만이 오버랩되도록 형성된다.따라서, 게이트 패드부(14a)와 데이터 버스 라인(20)은 전기적으로 연결되지 않은 상태가 된다.In this case, as illustrated in FIGS. 6 and 7, the data bus line 20 extends to overlap the gate pad portion 14a to form the data pad portion 20a. Here, the data pad part 20a is formed so that only about one half of the gate pad part 14a overlaps. Thus, the gate pad part 14a and the data bus line 20 are not electrically connected. Becomes
이어서, 소오스 및 드레인 전극(19a,19b)이 형성된 기판(11)상부에 PECVD 방식으로 실리콘 질화막을 증착하여 절연층 보호막(21)을 형성한다.그다음, OLB(out lead bonding) 작업시에, 패드부가 외부 단자와 콘택이 되도록 하기 위해, 제 5 마스크 공정을 진행하여 게이트패드부(14a), 데이터 패드부(20a)의 소정 부분이 오픈될 수 있도록 절연층 보호막(21)을 제거한다. 이때, 절연층 보호막(21)은 SF6, O2가스를 이용하여 제거한다. 또한, 박막 트랜지스터의 드레인 전극(19b) 부분도 오픈시킨다.Subsequently, a silicon nitride film is deposited on the substrate 11 on which the source and drain electrodes 19a and 19b are formed by PECVD to form an insulating layer protective film 21. Then, in an out lead bonding (OLB) operation, the pad In order to be in contact with the additional external terminal, the fifth mask process is performed to remove the insulating layer protective film 21 so that a predetermined portion of the gate pad portion 14a and the data pad portion 20a can be opened. At this time, the insulating layer protective film 21 is removed using SF 6 , O 2 gas. The drain electrode 19b portion of the thin film transistor is also opened.
이어서, 결과물 상부에 화소 전극용 ITO 금속막을 증착하고, 제 6 마스크 공정을 진행하여 ITO층을 빗살 형태로 패터닝하므로써 화소 전극(22)을 형성한다. 이때, 화소 전극(22)은 오픈된 드레인 전극(19b)과 콘택되면서 카운터 전극(12)상에 형성된다. 아울러, 패드 부분(도 6 및 도 7 참조)에서는 데이터 패드(20a)와 게이트 패드(14a)간을 전기적으로 연결시킨다.Subsequently, an ITO metal film for pixel electrodes is deposited on the resultant, and the pixel electrode 22 is formed by patterning the ITO layer in the form of a comb through the sixth mask process. In this case, the pixel electrode 22 is formed on the counter electrode 12 while being in contact with the open drain electrode 19b. In addition, the pad portion (see FIGS. 6 and 7) electrically connects the data pad 20a and the gate pad 14a.
이와같이, 본 발명에 따르면, 에치 스톱퍼를 형성하지 않으므로 하나의 마스크 공정을 생략할 수 있다.또한, 절연층 보호막을 형성한 다음 화소전극을 형성하므로써 화소 전극용 전도 물질이 데이터 패드와 게이트 패드를 접속시키는 역할을 하게 되므로, 절연층 보호막을 형성한 다음의 패드 오픈을 위한 또하나의 마스크공정을 생략할 수 있다.As described above, according to the present invention, since the etch stopper is not formed, one mask process can be omitted. Further, the conductive material for the pixel electrode connects the data pad and the gate pad by forming the insulating layer protective film and then forming the pixel electrode. In this case, another mask process for opening the pad after forming the insulating layer protective film may be omitted.
따라서, 종래에 비하여 마스크 수를 줄일 수 있다.Therefore, the number of masks can be reduced as compared with the prior art.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 에치 스톱퍼를 형성하는 마스크공정과 절연층 보호막 형성후 패드 오픈시키는 마스크공정을 줄일 수 있어, 종래보다 2개의 마스크를 줄일 수 있다.As described in detail above, according to the present invention, the mask process of forming the etch stopper and the mask process of opening the pad after forming the insulating layer protective film can be reduced, and thus, two masks can be reduced.
따라서, 본 발명은 제조 비용이 감소되고, 제조 수율을 증가시킬 수 있다.Thus, the present invention can reduce the manufacturing cost and increase the production yield.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR910008459A (en) * | 1989-10-04 | 1991-05-31 | 호시덴 가부시기가이샤 | LCD device |
| KR19980032965A (en) * | 1996-10-18 | 1998-07-25 | 미타라이 후지오 | Matrix substrate, liquid crystal device using the matrix substrate, and display device using the liquid crystal device |
| KR19980068515A (en) * | 1997-02-20 | 1998-10-26 | 문정환 | LCD and its manufacturing method |
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| KR910008459A (en) * | 1989-10-04 | 1991-05-31 | 호시덴 가부시기가이샤 | LCD device |
| KR19980032965A (en) * | 1996-10-18 | 1998-07-25 | 미타라이 후지오 | Matrix substrate, liquid crystal device using the matrix substrate, and display device using the liquid crystal device |
| KR19980068515A (en) * | 1997-02-20 | 1998-10-26 | 문정환 | LCD and its manufacturing method |
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| US8542331B2 (en) | 2009-07-24 | 2013-09-24 | Samsung Display Co., Ltd. | Display apparatus |
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