KR100340427B1 - Method of formation via in pcb - Google Patents

Abstract

According to the present invention, a via hole formed on a substrate sheet (CCL) of a printed circuit board is formed as a plugged via in which conductor pins are inserted, and a conductive circuit layer is printed on the upper and lower sides thereof, respectively, so that the upper and lower conductor circuit layers are plugged via. A method of forming a via of a substrate to be connected and connected, the technical configuration of which forms a via hole in an insulator substrate sheet, inserts a pin-shaped conductor pin into the inside of the substrate by press-fitting to form a plugged via hole, and the substrate sheet. After removing the conductive pins protruding from the surface of the substrate by grinding, and performing metallization operation for forming a conductor circuit layer of a constant thickness to the upper and lower surfaces of the substrate sheet, the conductive pins on the surface conductor layer up and down The plugged vias are applied to the substrate sheet through a conductor circuit layer forming step of forming a conductor circuit layer having a constant The main purpose is to connect and connect the upper and lower circuit patterns.

Description

Via formation method of substrate {METHOD OF FORMATION VIA IN PCB}

The present invention interpolates a pin-like conductor into a via hole formed on a substrate sheet CCL of a build-up PCB to form a plugged via. It relates to a method of forming vias of a substrate in which a conductive circuit layer is printed on the upper side and a lower side, respectively, and the upper and lower conductor circuit layers are connected by plugged vias. Inserting pin-shaped conductor pins into the vias to form plugged via holes, and flattening the substrate sheet by grinding the substrate sheets to remove the conductor pins protruding from the surface of the substrate sheet; Surface conductor layer forming step of performing a metallizing (Metalall) operation for forming a conductor circuit layer of a constant thickness to the upper and lower surfaces of the substrate sheet By connecting the plugged vias to the upper and lower circuit patterns on the substrate sheet through a conductor circuit layer forming step of forming a conductor circuit layer having a predetermined pattern connected to the upper and lower conductor pins on the surface conductor layer. The present invention relates to a method of forming vias in a substrate in which vias in a vertical state are formed with conductor pins to prevent undercut and unplated phenomenon in the via holes from occurring.

In a generally known method of forming a via hole of a substrate, a plurality of via holes 20 formed by laser processing are formed on the surface of the substrate sheet 10 (CCL) as shown in FIG. Thereafter, (B in FIG. 1), an electroless plating layer is applied to the upper and lower surfaces of the substrate sheet 20 on which the via holes 20 are formed and the inside of the via holes 10 to provide conductivity. 30 is formed as shown in FIG.

Subsequently, as shown in FIG. 1D, in order to secure a plating thickness of a predetermined thickness inside the via hole 20 on the substrate sheet 10, a plating operation using a material having excellent conductivity at low speed plating is performed. (10) After forming the plating layer 40 therein and completing the formation of the plating layer 40 inside the micro via hole 10 as described above, as shown in FIG. 1E, the upper conductor circuit layer 50 is exposed and etched. The circuit pattern is formed through the processing.

However, in the conventional method of forming a micro via hole, the via hole 20 is formed as shown in FIG. 2 when a minute hole is formed by processing such as a laser to form the micro via hole 20. If the inside is irregularly frequently generated, there is a disadvantage that it is impossible to ensure the flatness of the inner wall surface.

In particular, when the plating layer 40 is formed for interlayer connection in the via hole 20 as described above, a short circuit occurs with the conductor circuit layers of the upper and lower layers due to an irregular inner wall surface, resulting in product defects. There are many problems.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to form a via in a vertical state with a conductor pin inside a PCB to generate an undercut phenomenon and an unplating phenomenon in a via hole. The present invention provides a method of forming a via of a substrate that can prevent the defect of the product in advance.

Another object of the present invention is to form a plugged via in which conductor pins are filled by indentation in a via hole formed in a PCB, to prevent short circuit between upper and lower conductor circuit layers, and to form the plugged via vertically, thereby interlayer connection. The present invention provides a method of forming a via of a substrate that can be perfectly achieved.

1A-E are process diagrams sequentially illustrating a method of forming a via of a general printed circuit board.

FIG. 2 is an enlarged view illustrating main parts of a structure of a micro via hole formed on a substrate through conventional laser processing; FIG.

3A to E are sequential diagrams showing a method of forming a plugged via of a printed circuit board according to the present invention.

4 is an enlarged view of a main portion showing a structure of forming a plugged via on a printed circuit board according to the present invention;

Explanation of symbols on the main parts of the drawings

100 ... substrate sheet 110 ... via hole

120 ... conductor pin

130 ... Plugged Via

140 ... conductor circuit layer

As a technical configuration for achieving the above object, the present invention comprises the steps of: forming a via hole in an insulator substrate sheet, and inserting a pin-shaped conductor pin into the via hole by indentation to form a plugged via hole;

A substrate sheet planarization step of performing a planarization of the substrate sheet by grinding to remove conductor pins protruding from the surface of the substrate sheet;

A surface conductor layer forming step of performing a metallization operation for forming a conductor circuit layer having a constant thickness to upper and lower surfaces of the substrate sheet;

A conductive circuit layer forming step of forming a conductive circuit layer having a predetermined pattern connected to the upper and lower conductor pins on the surface conductor layer is connected to connect the plugged via to the upper and lower circuit patterns on the substrate sheet. By forming the vias.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are process diagrams sequentially illustrating a method of forming plugged vias of a printed circuit board according to the present invention, and FIG. 4 is an enlarged main structural diagram showing a structure of forming plugged vias on a printed circuit board according to the present invention. In the method of forming a plugged via hole of a printed circuit board of the present invention, a via hole 110 having a predetermined pattern is formed on an insulator substrate sheet 100 (CCL) as shown in FIG. Inside the via hole 110, a pin-shaped conductor pin 120 is interpolated by indentation to form a plugged via 130 as shown in FIG.

At this time, the via pins 110 through which the conductor pins 120 are interpolated and penetrated by indentation may be formed to be slightly smaller than the diameter of the conductor pins 120, or the diameter of the conductor pins may also be large when the diameter of the via holes is large. It becomes larger so that the plug pin 130 may be formed by extruding the conductor pin 120 by the high pressure without forming the via hole.

In addition, the via hole 110 inserted through the inside of the via hole 110 by indentation is formed of copper for interlayer connection.

As described above, after the formation of the plugged via 130 is completed in the via hole 110 of the substrate sheet, the conductor pin 120 protruding from the upper and lower surfaces of the substrate sheet 100 is as shown in FIG. It is removed by grinding to planarize the substrate sheet 100.

After the flattening operation by grinding is completed on the surface of the substrate sheet 100 as described above, the metallizing operation for the formation of the conductor circuit layer 140 having a predetermined thickness on the upper and lower surfaces of the substrate sheet 100. The substrate sheet 100 as described above allows the upper and lower conductor circuit layers 140 to be interconnected by conductor pins 120 inserted therein. E)

Subsequently, after the formation of the conductor circuit layer 140 on the upper and lower surfaces of the substrate sheet 100 as described above, the conductor circuit layer having a constant pattern connected to the surface conductor layer up and down with the conductor pin 120 ( 140 is formed by etching or the like (Fig. 3E), as shown in Fig. 4, the upper conductor circuit layer 140 intersects with the lower conductor circuit layer 140 and the plugged via 130 filled with copper inside. It can be connected.

As described above, according to the via of the printed circuit board and the method of forming the same, an undercut phenomenon generated during the formation of micro vias and unplated in the via hole is formed by forming a plug via having a vertical state in the multilayer PCB with copper conductor pins. It is possible to prevent the occurrence of the phenomenon in advance, thereby preventing the occurrence of product defects in advance, and to form plugged vias in which the conductor pins are inserted in the via holes formed on the PCB, thereby preventing short circuits between the upper and lower conductor circuit layers. Prevention, and by forming the plugged vias vertically, there is an excellent effect that the interlayer connection can be made perfectly.

While the invention has been shown and described with respect to specific embodiments thereof, it will be appreciated that the invention can be varied and modified without departing from the spirit or scope of the invention as set forth in the claims below. It will be clear to those skilled in the art that it can be easily understood.

Claims (3)

In the method of forming a via of a substrate, Forming via holes in the insulator substrate sheet, and inserting pin-shaped conductor pins into the via holes by indentation to form plugged via holes; A substrate sheet planarization step of performing a planarization of the substrate sheet by grinding to remove conductor pins protruding from the surface of the substrate sheet; A surface conductor layer forming step of performing a metallization operation for forming a conductor circuit layer having a constant thickness to upper and lower surfaces of the substrate sheet; A conductive circuit layer forming step of forming a conductive circuit layer having a predetermined pattern connected to the upper and lower conductor pins on the surface conductor layer is connected to connect the plugged via to the upper and lower circuit patterns on the substrate sheet. How to Form Vias 2. The method of claim 1, wherein the via pin through which the conductor pin is interpolated by the indentation is formed to be slightly smaller than the diameter of the conductor pin to interpolate the conductor pin through the indentation. . The method of claim 1, wherein the via holes penetrated and inserted through the via holes are made of copper for interlayer connection.