KR100340077B1 - Input frequency detector having no concern with change of processing and power voltage - Google Patents

Abstract

The present invention relates to a frequency detector of a semiconductor device, and is intended to implement a frequency detector irrespective of process changes and power supply voltages by setting a reference voltage and a charge voltage equally. To this end, the present invention provides a frequency detector of a semiconductor integrated circuit, comprising: duty adjusting means for adjusting the frequency of an input signal by receiving an input signal Vin; Reference voltage generating means for generating a reference signal; Charging current generating means for receiving the output signal of the duty regulator to charge and discharge current in the capacitor; The capacitor connected to an output of the charging current generating means and a ground terminal; Comparison means for comparing a reference voltage output from said reference voltage generating means with an output of said charging current generating means; And a flip-flop for receiving the output of the comparing means and the output of the duty adjusting means and outputting a frequency detection signal.

Description

Input frequency detector having no concern with change of processing and power voltage}

TECHNICAL FIELD The present invention relates to semiconductor integrated circuits, and more particularly, to an input frequency detector.

In general, the synchronous semiconductor circuit receives a reference signal from the outside and operates the system according to the period of the reference signal. Since there is no other frequency on which the magnitude of the reference frequency can be measured, you must use your own signal to know this input frequency. Frequency and period are inversely related, and period has repetitive regularity of high and low levels of the signal.

1 is a detailed circuit diagram of a conventional frequency detector.

Referring to FIG. 1, the conventional frequency detector includes a PMOS transistor 100 having a gate connected to a node Vc, and a source-drain path formed between a power supply voltage and the node Vc, and an input signal Vin0. Is inputted to the gate terminal, and a source-drain path is formed between the node Vc and the ground terminal, and the capacitor 120 formed between the node Vc and the ground terminal, and the node Vc. Inverter 130 for outputting the output signal (Vo) by inverting the signal.

The purpose of the frequency detector is to detect when a frequency lower than a frequency determined according to the standard of the system is input. In the section where the input signal Vin0 is at a low level, the capacitor 120 is charged with current through the PMOS transistor 100, and in the section where the input signal Vin0 is at the high level, the enMOS transistor 110 is turned on. On and the current is discharged through the enMOS transistor 110. The voltage charged in the capacitor is defined by the following equation (1).

I dt

2 is a timing diagram showing an operation of charging and discharging a capacitor of a conventional frequency detector.

Referring to FIG. 2, the voltage Vc of the node Vc of FIG. 1 is connected to the input of the inverter 130 and evaluated by the logic threshold voltage Vsp of the inverter 130. As shown in FIG. 2, when the voltage Vc is lower than the logic threshold voltage of the inverter 130, a logic high is output. When the voltage Vc is high, a logic low is output. Therefore, if set as shown in Equation 2

Vc (T) = Vsp,

Where T is the period of the logic high or logic low level of the minimum threshold of the input signal Vin0 frequency.

Vsp is the logic threshold voltage of the inverter

When the frequency of the input signal Vin0 is lowered (see Fig. 2) and the T is longer, Vc ≥ Vsp becomes so that the output of the inverter turns to logic low. This makes it possible to find out that the frequency of the input signal Vin0 is lower than the desired frequency.

In the frequency detector of Fig. 1, the design parameter is to find a suitable point that equals Vc (T) and Vsp. I, C, Vsp is determined under the same condition as in Equation 3 below.

At this time, Vsp is defined as Equation 4 below.

Equation 4 indicates that Vsp is dependent on the process change and the change in the supply voltage. In addition, the charge current I and the capacitor value also depend on process variations.

As a result, the design is dependent on process changes and changes in power supply voltage, and greatly affects the possibility of malfunction and the yield reduction. The Shmoo plot of FIG. 2 is a result of simulating the process dependency of the circuit of FIG. As can be seen from the results, it can be seen that the process change and the change in the supply voltage cause a problem that the change is severe at the set frequency at design time.

The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a frequency detector irrespective of changes in process and power supply voltage.

1 is a detailed circuit diagram of a frequency detector of the prior art;

2 is a timing diagram showing an operation of charging and discharging a capacitor of a conventional frequency detector;

3 is a detailed circuit diagram showing a frequency detector of the present invention;

Fig. 4 is a timing diagram showing the operation of the frequency detector.

Explanation of symbols on the main parts of the drawings

300: reference voltage generator 310: charging voltage generator

320: comparator 340: duty controller

In order to achieve the above object, the frequency detector of the present invention is a frequency detector of a semiconductor integrated circuit, comprising: duty adjusting means for adjusting the frequency of an input signal by receiving an input signal (Vin); Reference voltage generating means for generating a reference signal; Charging current generating means for receiving an output signal of the duty regulator and charging and discharging a current in a capacitor; The capacitor connected to an output of the charging current generating means and a ground terminal; Comparison means for comparing a reference voltage output from said reference voltage generating means with an output of said charging current generating means; And a flip-flop for receiving the output of the comparing means and the output of the duty adjusting means and outputting a frequency detection signal.

As described above, the frequency detector of the present invention sets the reference voltage Vref corresponding to the threshold frequency set in the input signal and the charging voltage Vc charged in the capacitor to be the same, so that the two voltages have the same change according to the process change. After the design, the difference can be evaluated using the comparator, so that the frequency detection can be stably performed regardless of the change in the power supply voltage and the process.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a detailed circuit diagram showing a frequency detector of the present invention.

Referring to FIG. 3, the frequency detector according to the present invention receives an input signal Vin, a duty adjuster 340 for adjusting the frequency of the input signal, and a reference voltage generator 300 for generating a reference signal. And a charge current generator 310 for charging and discharging current to a capacitor by receiving the first and second outputs of the reference voltage generator and the output signal of the duty controller 340, and the charge current generator ( A capacitor 350 connected to the output of the 310 and the ground terminal, the first and second outputs of the reference voltage generator 300, and the third output of the reference voltage generator 300 and the charging current generator A deflip-flop for outputting a frequency detection signal Vo by receiving a comparator 320 for comparing the outputs of the 310 and an output Vin of the comparator 320 and an output Vin2 of the duty adjuster 340. 330.

In detail, the reference voltage generator 300 includes a first PMOS transistor 301 having a gate terminal connected to the node Vc and a source-drain path formed between the power supply voltage and the third node, and the drain supply voltage. A second PMOS transistor 302 connected to the node and a gate terminal and a source terminal connected to the node Vc, a gate terminal connected to the second node, and a source-drain path between the third node and the fourth node. A third PMOS transistor 303 formed at the gate, a fourth PMOS transistor 304 having a drain terminal connected to the node Vc, a gate terminal and a source terminal connected to the second node, and a drain and gate terminal A first NMOS transistor 305 connected to a fourth node and a source terminal connected to the fifth node, a gate terminal connected to the fourth node, and a source-drain path between the second node and the sixth node. The second NMOS transistor 306 formed in the drain, and the gay A third NMOS transistor M11 having a terminal connected to the fifth node Vref and a source terminal connected to the ground terminal, a gate terminal connected to the fifth node, and a source-drain path connected to the sixth node. And a fourth NMOS transistor M12 formed between the seventh node and a resistor R formed between the seventh node and the ground terminal.

The charging current generator 310 receives a first node (first output), a second node (second output), and an output of the duty controller 340 through a gate terminal and receives a power supply voltage and an output. The three PMOS transistors 311, 312, and M13 connected in series between the nodes Vc and the output of the duty controller 340 are input to the gate stage, and a source-drain path is connected between the output node Vc and the ground terminal. And an MOS transistor M14 formed therein.

The comparator receives the first node (first output) and the second node (second output) of the reference voltage generator 300 as a gate terminal, and the two NMOS transistors 321 connected in series between the power supply voltage and the comparator. 322 and a comparator 323 for receiving the output Vc of the charging current generator 310 and the third output (the fifth node) of the reference voltage generator 300.

In order to determine the charging current and the reference voltage can be expressed by the following equation (5).

Vgs1 = Vgs2 + I × R

If the voltage Vgs between the gate and the source of the MOS transistors M11 and M12 is rewritten as a variable charging current, the following Equation 6 is obtained.

Considering the simplification of the design, let the channel length and width of the MOS transistors M11 and M12 be as follows. L11 = L12, W12 = KW11 (K: Arbitrary Variable)

When the charging current is obtained by using Equations 5 and 6, Equation 7 is obtained.

As a design factor for determining the charging current, it can be seen that the ratio of the resistance and the size of the MOS transistors M11 and M12. The resistance value can be obtained from Equation 8 below.

Equation 5 is used to set a voltage using the charging current as a reference voltage. That is, R, I, and K are determined under the condition that the voltage charged in the capacitor is equal to the reference voltage at the time corresponding to the half period of the frequency to be detected.

In the PMOS transistor M13 of the charging current generator 310 of FIG. 3, the output signal Vin2 of the duty controller 340 is turned on in a logic low period to charge. At this time, the n-mo transistor M14 of the charging current generator 310 is turned off. In the period in which the input signal Vin2 is logic high, the PMOS transistor M13 is turned off, and the enmos transistor M14 is turned on to discharge. If the current driving capability of the NMOS transistor M14 is less than the charging current, and if the duty of the input signal Vin is 50%, the charged voltage is not completely discharged and is offset in the next cycle. As a result, the power supply voltage eventually becomes inoperable. Therefore, the current driving capability of the NMOS transistor M14 should be designed to be larger than the charging current, and the duty of the input signal Vin should be 50%. The duty controller 340 of FIG. 3 is a circuit that makes the duty of the input signal Vin 50%.

The comparator 320 of FIG. 3 connects the charging voltage Vc which is the output of the charging current generator 310 to the positive input and the third output of the reference voltage generator 300 to the negative input. Connect the reference voltage (Vref) to compare the difference between the two inputs.

The deflip-flop 330 of FIG. 3 is a circuit for sampling the output of the comparator according to the output Vin2 of the duty controller 340.

4 is a timing diagram showing the operation of the frequency detector. The operation of the frequency detector of FIG. 3 is explained with time.

In conclusion, by designing the variable of the charging voltage (Vc) and the variable of the reference voltage (Vref) the same at the set frequency it is possible to prevent the frequency detector from malfunctioning in accordance with the variation of the design element values according to the process change.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, since the present invention is not affected by the process change and the change of the power supply voltage, it is possible to secure stability in the operation of the frequency detector itself and contribute to the improvement of the semiconductor manufacturing yield.

Claims (9)

In the frequency detector of a semiconductor integrated circuit, Duty adjusting means for receiving an input signal Vin and adjusting a frequency of the input signal; Reference voltage generating means for generating a reference signal; Charging current generating means for receiving an output signal of the duty regulator and charging and discharging a current in a capacitor; The capacitor connected to an output of the charging current generating means and a ground terminal; Comparison means for comparing a reference voltage output from said reference voltage generating means with an output of said charging current generating means; And A deflip-flop for receiving the output of the comparing means and the output of the duty adjusting means and outputting a frequency detection signal; Frequency detector comprising a. The method of claim 1, The reference voltage generating means, A first PMOS transistor having a gate terminal connected to the first node and a source-drain path formed between the power supply voltage and the third node; A second PMOS transistor having a drain connected to a power supply voltage and a gate terminal and a source terminal connected to the first node; A third PMOS transistor having a gate terminal connected to the second node and a source-drain path formed between the third node and the fourth node; A fourth PMOS transistor having a drain terminal connected to the first node and a gate terminal and a source terminal connected to the second node; A first NMOS transistor having a drain and a gate terminal connected to a fourth node and a source terminal connected to a fifth node; A second NMOS transistor having a gate terminal connected to the fourth node and a source-drain path formed between the second node and the sixth node; A third NMOS transistor having a drain and a gate terminal connected to a fifth node Vref and a source terminal connected to a ground terminal; A fourth NMOS transistor having a gate terminal connected to the fifth node and a source-drain path formed between the sixth node and the seventh node; And Resistance formed between the seventh node and the ground terminal Frequency detector comprising a. The method of claim 1, The charging current generating means, Three PMOS transistors connected in series between a power supply voltage and an output node Vc by receiving a signal output from the reference voltage generating means and an output of the duty adjusting means into a gate terminal; And An NMOS transistor having an output of the duty adjusting means input to a gate terminal and a source-drain path formed between its output node Vc and a ground terminal Frequency detector consisting of. The method of claim 1, And said duty adjustment means adjusts the duty to 50% while lowering the frequency in order to avoid malfunction due to the difference in duty of the input signal. The method of claim 1, And the charging current generating means discharges in the logic low period when the logic high of the signal having a duty of 50% is the charge period, and discharges in the logic high period when the logic low is the charge period. The method of claim 1, The charging current generating means is a frequency detector, characterized in that the discharge current is set larger than the charging current to remove the offset (offset) of the input signal. The method of claim 1, And a reference voltage, which is an output of the reference voltage generating means, is proportional to the charging current, thereby minimizing the dependence of the process change and the influence on the change of the power supply voltage. The method of claim 1, And the comparing means compares the reference voltage with a voltage charged in the capacitor. The method of claim 1, The deflip-flop is a circuit for sampling the output of the comparator according to the input signal (Sampling) characterized in that the circuit.