KR100336786B1 - Bit line equalizing control circuit for semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line equalization control circuit of a semiconductor memory. In the prior art, current is consumed by inputting at a boosted voltage level of a voltage level equalized at the time of bit line equalization. When enabled, as the swing between the boosted voltage and the ground voltage at the time of equalization is released, the timing margin until the bit line is selected after the application of the ras signal is normally reduced and the timing margin until the next ras signal is applied, thereby reducing previous data. There is a problem that the data is lost by changing the next data value by the value. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, by outputting the equalization signal equalizing the corresponding bit line at the boosted voltage level only for a predetermined time and then outputting the power supply voltage level during bit line equalization. In addition to minimizing the current consumption, the timing margin until the bit line is normally selected after the application of the ras signal and the timing margin until the next ras signal is applied are secured, thereby preventing data from being burned out.

Description

BIT LINE EQUALIZING CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line equalization control circuit of a semiconductor memory, and more particularly, to an equalization circuit for equalizing a bit line for transferring memory cell data. It relates to a bit line equalization control circuit.

FIG. 1 is a circuit diagram showing a configuration of a general bit line sense amplifier, and as shown therein, a bit line pair BLI, / BLI (BLJ, / BLJ) of memory cells respectively connected by an equalization signal BLEQI (BLEQJ). A bit line equalizer (10) (11) for equalizing; A bit line selector (20) (21) for conveying the bit line pairs (BLI, / BLI) (BLJ, / BLJ) respectively by a selection signal (BSI) (BSJ); A sense amplifier configured to sense bit line pairs BLI, / BLI (BLJ, / BLJ) connected through the bit line selectors 20, 21 with sensing voltages SPC and SNC; Each of the NMOS transistors is electrically controlled by an output control signal YSEL and outputs a voltage sensed by the sense amplifier as a data signal DB and a data bar signal / DB.

The bit line equalizers 10 and 11 are electrically controlled by the equalization signals BLEQI and BLEQJ to connect the bit line pairs BLI and / or BLI to BLJ and BLJ. Transistors NM1 and NM6; EnMOS transistors NM2, NM3, NM7, which are electrically controlled by the equalization signals BLEQI and BLEQJ, respectively, and output the equalization voltage BVLP to bit line pairs BLI, / BLI, BLJ, / BLJ. NM8), and the bit line selectors 20 and 21 are conductively controlled by the selection signal BSI (BSJ) to convert the bit line pairs BLI, / BLI (BLJ, / BLJ) into sense amplifiers, respectively. NMOS transistors NM4 and NM5 (NM9 and NM10) to be output.

In addition, the configuration of the bit line equalization control unit for controlling the operations of the bit line equalizers 10 and 20 and the bit line selectors 20 and 21 is sensed with the block selection signal BI as illustrated in FIG. 2. A mismatch gate NOR1 for mismatching the signal SN0; A mismatch gate NOR2 that mismatches the block selection signal BJ and the sensing signal SN0; Mismatched gates NOR3 and NOR4 that receive feedback from the output signals of the mismatched gates NOR1 and NOR2 and the output signals of each other; Inverters I1 and I2 that receive and invert the output signals of the mismatched gates NOR3 and NOR4, respectively; Inverters I3 and I4 respectively receiving and outputting the output signals of the inverters I1 and I2; A level shifter (30) (31) for receiving the output signals of the inverters (I1, I3) (I2, I4) and level shifting them to a boosted voltage (VPP) level respectively; Inverters (I10) (I13) for respectively inverting the output signal of the level shifters (30) (31) to a boosted voltage (VPP) level; Inverters I11 and I14 for respectively inverting the output signal of the inverters I10 and I13 to the boosted voltage VPP level; Reversing the output signal of the inverters I10 and I13 to the boosted voltage VPP level, respectively, so that the equalization signal BLEQI and BLEQJ are inverters I12 and I15; A mismatch gate NOR5 for mismatching an output signal of the inverters I10 and I13; Inverters I16 and I17 for respectively inverting the output signal of the inverters I14 and I11 to the boosted voltage VPP level; NMOS transistors NM11 and NM13, each being electrically controlled by the output signal of the mismatched gate NOR5 and outputting a power supply voltage VCC to the selection signal BSI BBS; NMOS transistors NM12 and NM14, which are electrically controlled by the output signals of the inverters I16 and I17 to ground the selection signal BSI and BSJ, respectively; Each of the PMOS transistors NM10 and NM11 is electrically controlled by the output signals of the inverters I11 and I14 to output a boosted voltage VPP to the selection signal BSI BJ. With reference to Figure 3 attached to the operation process according to the prior art configured will be described in detail.

When a block including a bit line pair BLI (/ BLI) is selected in a semiconductor memory and is sensed and output by a sense amplifier, first, the selection signal BI predecoding the highest row address is shown in FIG. As shown in FIG. 2, the signal is raised to a high potential, but the selection signal BJ maintains a low potential.

Accordingly, the bit line equalization control unit receiving the sensing signal SN0 as shown in FIG. 2B output by the selection signal BI BJ and the sensing enable signal for starting bit line sensing is illustrated in FIG. As shown in (c) and (d), the selection signal BSI and BSJ are output, and the equalization signal BLEQI and BLEQJ are output as shown in FIG.

That is, the mismatch gate NOR1 receiving the high potential selection signal BI and the low potential sensing signal SNO outputs a low potential, but the low potential selection signal BJ and the low potential sensing signal ( The mismatched gate NOR2 that receives SNO outputs a high potential.

The mismatched gates NOR3 and NOR4 that receive the input signals and the respective output signals of the mismatched gates NOR1 and NOR2 are mutually mismatched to output high potentials and low potentials, respectively. The inverters I1 and I2 that have received the output signals of NOR3 and NOR4 invert and output the same, and the output signals of the inverters I1 and I2 are inverted again through the inverters I3 and I4. do.

In addition, the level shifters 30 and 31 that receive the output signals of the inverters I1 and I3 (I2 and I4) respectively output a boosted voltage VPP and a ground voltage, and the level shifter 30 ( The output signal of 31 is sequentially reversed through the inverters I10 and I12 (I13 and I15) and output as an equalization signal BLEQI and BLEQJ.

The bit line equalization control unit outputs a boosted voltage VPP that is electrically controlled by an output signal of the inverters I11 and I14 that inverts the output signal of the inverters I10 and I13. NMOS transistors NM11 and NM13 which are electrically controlled by the output signals of the mismatching gate NOR5 that mismatch the output signals of the PM10 and PM11 and the inverters I10 and I13 to output the power supply voltage VCC. And the selection signal BSI by the NMOS transistors NM12 and NM14 which output ground voltages by the output signals of the inverters I16 and I17 inverting the output signals of the inverters I14 and I11, respectively. Will output (BSJ).

Accordingly, since the bit line selector 20 is operated by the selection signal BSI (BSJ), when the word line is enabled as shown in FIG. 3G, the sense voltage SPC as shown in FIG. The voltage of the bit line pair BLI (/ BLI) is sensed as shown in FIG.

Further, the case where another bit line pair BLJ (/ BLJ) is selected also operates in the same manner as the bit line pair BLI (/ BLI).

As described above, when the input voltage is increased to the boosted voltage level of the voltage level to be equalized at the time of bit line equalization, when the current consumption is large and other word lines are enabled in the same bit line, As the swing to ground voltage reduces the timing margin until the bit line is normally selected after the las signal is applied, and the timing margin until the next las signal is applied, the next data value is changed by the previous data value and data is lost. There was a problem thrown away.

Accordingly, the present invention has been made to solve the above-described problems, and minimizes the current consumption by outputting the boosted voltage level only for a predetermined time during bit line equalization and then outputting the bit line equalized signal at the power supply voltage level. In addition, an object of the present invention is to provide a bit line equalization control circuit of a semiconductor memory having an improved equalization speed.

1 is a circuit diagram showing the configuration of a general bit line sense amplifier.

2 is a circuit diagram showing a configuration of a conventional bit line equalization control unit.

3 is an input / output voltage waveform diagram of a bit line sense amplifier according to FIG. 2;

4 is a circuit diagram showing the configuration of the bit line equalization control unit of the present invention.

5 is an input / output voltage waveform diagram of the bit line sense amplifier shown in FIG. 4;

*** Description of the symbols for the main parts of the drawings ***

100,101: level shifter 110,120: equalization voltage control unit

111,112: Delays I1 to I4, I10 to I19: Inverter

NAND1, NAND2: Non-Gate Gates NOR1-NOR7: Mismatch Gates

NM1-NM18: NMOS transistor PM1-PM4: PMOS transistor

A configuration of the present invention for achieving the above object comprises a first mismatch gate for mismatching the first block selection signal and the sensing signal; A second mismatch gate for mismatching the second block selection signal and the sensing signal; Third and fourth mismatched gates that receive feedback from the output signals of the first and second mismatched gates and the respective output signals; The output signals of the first and second inverters inverting the output signals of the third and fourth mismatched gates and the output signals of the third and fourth inverters inverted from the third and fourth mismatched gates are respectively input. First and second level shifters which level-shift the output signal to a boosted voltage level and output the level signal; Fifth and sixth inverters for respectively inverting output signals of the first and second level shifters to a boosted voltage level; A seventh and eighth inverters for respectively inverting the output signals of the fifth and sixth inverters to a boosted voltage level; A fifth mismatch gate configured to mismatch the output signals of the fifth and sixth inverters; Ninth and tenth inverters for respectively inverting output signals of the eighth and seventh inverters to a boosted voltage level; First and second NMOS transistors, each being electrically controlled by an output signal of the fifth mismatch gate and outputting a power supply voltage as first and second selection signals; Third and fourth NMOS transistors electrically connected to each other by the output signals of the ninth and tenth inverters to ground the first and second selection signals; First and second PMOS transistors respectively connected to and controlled by the output signals of the seventh and eighth inverters and outputting a boosted voltage to the first and second selection signals; First and second equalized voltage controllers respectively configured to receive output signals of the first and second level shifters to control voltage levels of the first and second equalized signals; Third and fourth PMOS transistors respectively connected to and controlled by the first output signal of the first and second equalized voltage controllers to output a boosted voltage as the first and second equalized signals; Fifth and sixth NMOS transistors respectively connected to each other by the second output signal of the first and second equalized voltage controllers and output a power supply voltage as the first and second equalized signals; And a seventh and eighth NMOS transistors which are electrically controlled by the output signals of the fifth and sixth inverters and output ground voltages to the first and second equalized signals, respectively.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

The configuration of a general bit line sense amplifier is the same as that of FIG.

4 is a circuit diagram illustrating a configuration of the bit line equalization control unit of the present invention, and a mismatch gate NOR1 for mismatching the block selection signal BI and the sensing signal SN0 as shown therein; A mismatch gate NOR2 that mismatches the block selection signal BJ and the sensing signal SN0; Mismatched gates NOR3 and NOR4 that receive feedback from the output signals of the mismatched gates NOR1 and NOR2 and the output signals of each other; Inverters I1 and I2 that receive and invert the output signals of the mismatched gates NOR3 and NOR4, respectively; Inverters I3 and I4 respectively receiving and outputting the output signals of the inverters I1 and I2; A level shifter (100) (101) for receiving the output signals of the inverters (I1, I3) (I2, I4), respectively, and level shifting them to a boosted voltage (VPP) level; Inverters I10 and I14 for respectively inverting the output signal of the level shifters 100 and 101 to a boosted voltage VPP level; Inverters I11 and I15 for respectively inverting the output signal of the inverters I10 and I14 to the boosted voltage VPP level; A mismatch gate NOR7 that mismatches the output signal of the inverters I10 and I14; Inverters I18 and I19 for respectively inverting the output signals of the inverters I15 and I11 to the boosted voltage VPP level; NMOS transistors NM11 and NM13, each being electrically controlled by an output signal of the mismatched gate NOR7 and outputting a power supply voltage VCC to the selection signal BSI BBS; NMOS transistors NM12 and NM14 which are electrically controlled by the output signals of the inverters I18 and I19 to ground the selection signal BSI and BSJ, respectively; PMOS transistors NM10 and NM11, each being electrically controlled by the output signals of the inverters I11 and I15 and outputting a boosted voltage VPP to the selection signal BSI and BSJ; An equalization voltage controller (110) (120) for receiving the output signals of the level shifters (100) (101) to control the voltage level of the equalization signal (BLEQI); PMOS transistors PM12 and PM13 that are electrically controlled by first output signals of the equalization voltage controllers 110 and 120 to output a boosted voltage VPP as the equalization signal BLEQI and BLEQJ; NMOS transistors NM15 and NM17 which are electrically controlled by the second output signals of the equalization voltage controllers 110 and 120 to output a power supply voltage VCC as the equalization signal BLEQI and BLEQJ, respectively; NMOS transistors NM16 and NM18 which are electrically controlled by the output signals of the inverters I10 and I14 and output a ground voltage as the equalization signal BLEQI and BLEQJ.

The equalization voltage controllers 110 and 120 may include delayers 111 and 121 that receive an output signal of the level shifter 100 and 101 and delay a predetermined time; An inverter (I12) (I16) for inverting the output signal of the level shifter (100) (101) to a boosted voltage (VPP) level; An inverter (I13) (I17) for inverting the output signal of the retarders (111) (121) to a boosted voltage (VPP) level; A negative gate (NAND1) (NAND2) for performing a product of a multiplication on the output signal of the level shifters (100) (101) and the output signals of the inverters (I13) (I17) and outputting it as a first output signal; Each of the mismatched gates NOR5 and NOR6 that mismatches the output signals of the output signals I12 and I13 (I16 and I17) of the inverter, respectively, refer to FIG. 5 attached to the operation process of the present invention. It will be described in detail.

In the case where a block including a bit line pair BLI (/ BLI) is selected in a semiconductor memory and is sensed and output by a sense amplifier, first, the selection signal BI having pre-decoded the highest row address is illustrated in FIG. Rise to high potential, but select signal BJ maintains low potential.

In addition, the bit line equalization control unit receiving the sensing signal SN0 as shown in FIG. 5B output by the selection signal BI BJ and the sensing enable signal for starting bit line sensing is illustrated in FIG. 3. (c) The selection signal BSI (BSJ) is output as shown in (d), and the equalization signal BLEQI (BLEQJ) is output as shown in FIG.

In this case, the operation of outputting the selection signal BSI (BSJ) by the bit line equalization control unit operates in the same manner as in FIG. 2. That is, the mismatch gate NOR1 receiving the high potential selection signal BI and the low potential sensing signal SNO outputs a low potential, but the low potential selection signal BJ and the low potential sensing signal ( The mismatched gate NOR2 receiving the SNO outputs a high potential, and the mismatched gate NOR3 (NOR4), which receives the output signals of the mismatched gates NOR1 and NOR2 and the respective output signals from each other, mismatches them. Compute and output the high and low potentials, respectively.

The level shifter 100 receives input signals of the inverters I1 and I2 inverting the output signals of the mismatching gates NOR3 and NOR4 and output signals of the inverters I3 and I4 inverting the same. 111 respectively outputs the output signal of the output signal of the mismatching gates NOR3 and NOR4 at the boosted voltage VPP and the ground voltage level.

Accordingly, the bit line equalization control unit may output a PMOS transistor that outputs a boosted voltage VPP that is electrically controlled by an output signal of the inverters I11 and I15 inverting the output signal of the inverters I10 and I14. NMOS transistors NM11 and NM13 that are electrically controlled by the output signals of the mismatching gate NOR7 that mismatch the output signals of the PM10 and PM11 and the inverters I10 and I14 to output the power supply voltage VCC. And the selection signal BSI by the NMOS transistors NM12 and NM14 which output ground voltages by the output signals of the inverters I18 and I19 inverting the output signals of the inverters I15 and I11, respectively. (BSJ) is output.

The equalization voltage control unit 110 and 120 receiving the output signals of the level shifters 100 and 101 are described. First, since the output signal of the level shifter 101 does not change with the ground voltage, the equalization voltage is maintained. As the controller 120 outputs the high potential and the low potential as the first and second output signals, the PMOS transistor PM13 and the NMOS transistor NM17 are turned off, respectively, and the low potential output of the level shifter 101 is output. The NMOS transistor NM18 conducted by the output signal of the inverter I14 inverting the signal outputs a low potential as the equalization signal BLEQJ.

However, in the case of the equalization voltage controller 110 receiving the output signal of the level shifter 100, when the output signal of the first level shifter 100 is output from the low potential to the high potential, the delayed delay 111 received the low signal is low. The potential is output for a predetermined time.

As a result, the negative gate NAND1 of which the output signal of the inverter I13 which inverts the low potential output signal of the delay unit 111 and the high potential output signal of the level shifter 100 for a predetermined time is multiplied. An inverter that outputs a high potential as a first output signal, turns off the PMOS transistor PM12, and inverts the high potential output signal of the level shifter 100 and the low potential output signal of the delay unit 111, respectively. The mismatching gate NOR5 that mismatches the output signal of I12) I13 outputs a high potential to turn on the NMOS transistor NM15 to output the power supply voltage VCC as an equalization signal BLEQI.

When the predetermined time has elapsed, the equalizing voltage controller 110 outputs the first and second output signals at high potential and low potential, respectively, as the delay unit 111 outputs the high potential. The equalization signal BLEQI is turned off through the NMOS transistor NM16 having the transistor PM12 and NM15 turned off and the output signal of the inverter I10 inverting the output signal of the level shifter 100 input to the gate. Output the ground voltage.

When the block selection signal BI drops from the high potential to the low potential, the delay unit 111 in the equalizing voltage controller 110 maintains the same at a predetermined time high potential.

Accordingly, the negative gate NAND1 of which the low potential output signal of the inverter I13 and the low potential output signal of the level shifter 100 are inversely calculated by inverting the output signal of the delay unit 111 for the predetermined time. Outputs a low potential as a first output signal, turns on the PMOS transistor PM12 to output a boosted voltage using the equalization signal BLEQI, and outputs the output signals of the level shifter 100 and the retarder 111, respectively. The mismatching gate NOR5 that mismatches the output signal of the inverted inverters I12 and I13 outputs a low potential to turn off the NMOS transistor NM15.

When the delay time of the delay unit 111 has elapsed, the equalizing voltage controller 110 outputs the first output signal at high potential as the delay unit 111 outputs a low potential, and the second output signal. Outputs a low potential and outputs a power supply voltage VCC to the equalization signal BLEQ1 through the NMOS transistor NM15 to equalize the bit line pair BLI / BLI to an equalization voltage BVLP.

Accordingly, since the bit line selector 20 is operated by the selection signal BSI (BSJ), when the word line is enabled as shown in FIG. 5G, the sense voltage SPC as shown in FIG. The voltage of the bit line pair BLI (/ BLI) is sensed as shown in FIG.

Further, the case where another bit line pair BLJ (/ BLJ) is selected also operates in the same manner as the bit line pair BLI (/ BLI).

As described in detail above, the present invention outputs an equalization signal equalizing the corresponding bit line at a boosted voltage level only for a predetermined time and outputs the power supply voltage level at the time of bit line equalization, thereby minimizing the current consumption and the las signal The timing margin until the bit line is normally selected after application and the timing margin until the next Lath signal is applied are secured, thereby preventing data from being burned out.

Claims (2)

A first mismatch gate for mismatching the first block selection signal and the sensing signal; A second mismatch gate for mismatching the second block selection signal and the sensing signal; Third and fourth mismatched gates that receive feedback from the output signals of the first and second mismatched gates and the respective output signals; The output signals of the first and second inverters inverting the output signals of the third and fourth mismatched gates and the output signals of the third and fourth inverters inverted from the third and fourth mismatched gates are respectively input. First and second level shifters which level-shift the output signal to a boosted voltage level and output the level signal; Fifth and sixth inverters for respectively inverting output signals of the first and second level shifters to a boosted voltage level; A seventh and eighth inverters for respectively inverting the output signals of the fifth and sixth inverters to a boosted voltage level; A fifth mismatch gate configured to mismatch the output signals of the fifth and sixth inverters; Ninth and tenth inverters for respectively inverting output signals of the eighth and seventh inverters to a boosted voltage level; First and second NMOS transistors, each being electrically controlled by an output signal of the fifth mismatch gate and outputting a power supply voltage as first and second selection signals; Third and fourth NMOS transistors electrically connected to each other by the output signals of the ninth and tenth inverters to ground the first and second selection signals; First and second PMOS transistors respectively connected to and controlled by the output signals of the seventh and eighth inverters and outputting a boosted voltage to the first and second selection signals; First and second equalized voltage controllers respectively configured to receive output signals of the first and second level shifters to control voltage levels of the first and second equalized signals; Third and fourth PMOS transistors respectively connected to and controlled by the first output signal of the first and second equalized voltage controllers to output a boosted voltage as the first and second equalized signals; Fifth and sixth NMOS transistors respectively connected to each other by the second output signal of the first and second equalized voltage controllers and output a power supply voltage as the first and second equalized signals; And a seventh and eighth NMOS transistors which are electrically controlled by the output signals of the fifth and sixth inverters and output ground voltages to the first and second equalized signals, respectively. Line equalization control circuit. 2. The apparatus of claim 1, wherein the first and second equalizing voltage controllers include: a delay unit configured to delay a predetermined time by receiving an output signal of an input level shifter; A first inverter for respectively inverting the output signal of the level shifter to a boosted voltage level; A second inverter for inverting the output signal of the delay unit to a boosted voltage level; A multiply gate configured to perform a multiplicative operation on the output signal of the level shifter and the output signal of the second inverter to output the first output signal; And a mismatch gate for mismatching an output signal of an output signal of the first and second inverters.