KR100336761B1 - Stacked buttom lead package and manufacturing method thereof - Google Patents
Stacked buttom lead package and manufacturing method thereof Download PDFInfo
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- KR100336761B1 KR100336761B1 KR1019990043622A KR19990043622A KR100336761B1 KR 100336761 B1 KR100336761 B1 KR 100336761B1 KR 1019990043622 A KR1019990043622 A KR 1019990043622A KR 19990043622 A KR19990043622 A KR 19990043622A KR 100336761 B1 KR100336761 B1 KR 100336761B1
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- chip
- lead
- package
- pad
- pads
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- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000000465 moulding Methods 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000005452 bending Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
Abstract
본 발명은 적층형 버틈리드패키지 및 제조방법에 관한 것으로서, 종래의 적층형 버틈리드패키지는 동일한 위치의 칩패드에 엔시리드가 연결되거나 시에스리드가 선택적으로 연결되어 공용으로 사용되므로 메모리 용량이 증대될 경우에는 상기 공용으로 사용되는 칩패드로는 적층할 수 없는 문제점이 있었으나, 본 발명에 의한 적층형 버틈리드패키지 및 제조방법은 반도체칩의 상면에 옵셔널패드와 상부리드 및 칩패드를 형성하고, 시에스칩패드와 엔시칩패드를 전기적으로 연결시키는 옵셔널패드를 설치함으로써, 버틈리드패키지의 적층시 리드프레임과의 와이어본딩을 선택적으로 연결하여 메모리 용량을 증대시킬 수 있다.The present invention relates to a stacked buried lid package and a manufacturing method, and a conventional stacked buried lid package is used in common when an nsi lead is connected to a chip pad at a same position or a sess lead is selectively used. Although there was a problem in that the chip pad used in common cannot be stacked, the stacked buried lid package and manufacturing method according to the present invention form an optional pad, an upper lead, and a chip pad on the upper surface of the semiconductor chip, and a sheath chip pad. By installing an optional pad electrically connecting the chip chip and the chip chip, the memory capacity can be increased by selectively connecting the wire bonding with the lead frame when stacking the gap lead package.
Description
본 발명은 적층형 버틈리드패키지에 관한 것으로서, 보다 상세하게는 옵셔널패드를 구비하여 리드프레임과의 와이어본딩을 선택적으로 함으로써, 메모리 용량을 증대시킬 수 있는 적층형 버틈리드패키지 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked buried lid package, and more particularly, to a stacked buried lid package and a manufacturing method capable of increasing memory capacity by selectively providing wire bonding with a lead frame by providing an optional pad.
최근 많은 투자 없이도 시스템이 요구하는 고집적 메모리 및 다기능 디바이스 등을 출현시키고 있는 적층형 패키지 기술이 크게 부각되고 있는 바, 일반적인 적층형 패키지는 기존의 TSOP, SOJ, BLP 등의 단품 패키지를 적층한 후, 외부에 노출된 리드를 전도성 재료로 연결하는 방법으로 제조되고 있다.Recently, the stacking package technology, which has emerged the high-integrated memory and multifunction devices required by the system without much investment, has been highlighted. In general, the stacking package is laminated with a single package such as TSOP, SOJ, and BLP. It is manufactured by connecting exposed leads with a conductive material.
도 1은 종래의 적층형 버틈리드패키지의 구조를 나타내 보인 단면도로서, 도시된 바와 같이, 상부 반도체칩(1)의 하면 양측에 상부리드(2)들이 나열되어 설치되어 있고, 상기 상부리드(2)들과 상기 칩(1)의 칩패드(1a)들은 상부와이어(3)로 각각 연결되어 있으며, 상기 상부리드(2)들의 하면이 외부로 노출됨과 아울러 상기 상부와이어(3), 칩(1)을 감싸도록 에폭시로 상부몰딩부(4)가 형성되어 상부패키지(5)를 구성하고, 상기 상부패키지(5)의 하측에는 상기 상부리드(2)와 대응되도록 내측에 위치되는 인너리드(2a')와 외측에 위치되는 아웃리드(2b')로 형성된 하부리드(2')와, 하부 반도체칩(1')과, 하부와이어(3')와, 하부몰딩부(4')가 동일한 구조로 하부패키지(5')를 구성하여 솔더(6)에 의하여 서로 대향하도록 접합되어 적층형 버틈리드패키지를 구성한다.1 is a cross-sectional view illustrating a structure of a conventional stacked buried lid package. As illustrated, upper leads 2 are arranged on both sides of a lower surface of the upper semiconductor chip 1, and the upper leads 2 are disposed. And the chip pads 1a of the chip 1 are connected to the upper wires 3, respectively, and the lower surfaces of the upper leads 2 are exposed to the outside and the upper wires 3 and 1 are exposed to the outside. An upper molding part 4 is formed of epoxy to surround the upper package 5, and an inner lead 2a ′ positioned inside the upper package 5 to correspond to the upper lead 2. ) And the lower lead 2 'formed of the outer lead 2b' located outside, the lower semiconductor chip 1 ', the lower wire 3', and the lower molding part 4 'have the same structure. The lower package 5 'is configured to be bonded to each other by the solder 6 to form a stacked buried lid package.
도 2a는 상기 상부패키지(5)의 와이어본딩된 상태를 나타내 보인 저면도이고, 도 2b는 상기 하부패키지(5')의 와이어본딩된 상태를 나타내 보인 평면도로서, A 및 A'는 반도체칩(1,1')의 칩패드(1a,1a')와 결합되지 않는 엔시리드(NC LEAD; No Connection Lead)이며, 나머지는 반도체칩(1,1')의 칩패드(1a,1a')와 결합되는 시에스리드(CS LEAD; Chip Select Lead)이다.2A is a bottom view showing a wire bonded state of the upper package 5, and FIG. 2B is a plan view showing a wire bonded state of the lower package 5 ', where A and A' are semiconductor chips ( NC LEAD (No Connection Lead), which is not coupled to the chip pads 1a and 1a 'of the 1,1', and the rest are the chip pads 1a and 1a 'of the semiconductor chip 1 and 1'. It is a bonded lead (CS LEAD; Chip Select Lead).
도 2c는 상기 엔시리드(A,A')가 형성된 적층형 버틈리드패키지의 종단면도로서, 도시된 바와 같이 상부패키지(5) 및 하부패키지(5')에 형성된 엔시리드(A,A')는 시에스리드와 대향하여 솔더(6)에 의하여 접합되도록 구성된다.FIG. 2C is a longitudinal cross-sectional view of the stacked buried lid package in which the encapsulations A and A 'are formed, and as shown, the encapsulations A and A' formed in the upper package 5 and the lower package 5 'are shown in FIG. It is configured to be joined by the solder 6 opposite the sheath lead.
상기 종래의 적층형 버틈리드패키지의 제조공정을 순차적으로 설명하면 다음과 같다.Referring to the manufacturing process of the conventional laminated buried lid package sequentially as follows.
먼저, 도 3a와 같이 상부패키지(5)를 완성하고 그와 동일한 방법으로 도 3b와 같이 하부패키지(5')를 완성한 후, 도 3c와 같이 하부패키지(5')를 뒤집어 놓은 상태에서 상부패키지(5)를 상측에 대행하도록 얼라인 한 다음, 각각의 상,하부리드(2,2')를 각각 솔더(6)로 부착하여 적층시킨다.First, the upper package 5 is completed as shown in FIG. 3a, and the lower package 5 'is completed as shown in FIG. 3b in the same manner, and then the upper package is turned upside down as shown in FIG. 3c. (5) is aligned so as to face the upper side, and then each of the upper and lower leads (2, 2 ') are attached with a solder (6) and laminated.
그런 다음, 하부패키지(5')의 돌출된 아웃리드(2b')를 하측으로 절곡하여 적층형 버틈리드패키지를 완성한다.Then, the protruding outlead 2b 'of the lower package 5' is bent downward to complete the stacked buried lid package.
그러나, 종래의 적층형 버틈리드패키지는 도 2a 및 도 2b에 도시된 바와 같이, 동일한 위치의 칩패드(B)에 엔시리드(A,A')가 연결되거나 시에스리드가 선택적으로 연결되어 공용으로 사용되므로 메모리 용량이 증대될 경우에는 상기 공용으로 사용되는 칩패드(B)로는 적층할 수 없는 문제점이 있었다.However, the conventional stacked buried lid package is commonly used because the ensirides (A, A ') are connected to the chip pads (B) at the same position or the sislead is selectively connected as shown in FIGS. 2A and 2B. Therefore, when the memory capacity is increased, there is a problem that cannot be stacked by the chip pad B commonly used.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 메모리 용량이 증가될 경우에도 효율적으로 적층할 수 있는 칩패드가 적용된 적층형 버틈리드패키지 및 제조방법을 제공하는 데 있다.The present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to provide a stacked buried lid package and a manufacturing method applied chip pad that can be efficiently stacked even when the memory capacity is increased There is.
도 1은 종래의 적층형 버틈리드패키지의 구조를 나타내 보인 단면도.1 is a cross-sectional view showing the structure of a conventional stacked buried lid package.
도 2a는 종래 적층형 버틈리드패키지에서 상부패키지의 와이어본딩 상태를 나타내 보인 저면도.Figure 2a is a bottom view showing a wire bonding state of the upper package in a conventional stacked buried lid package.
도 2b는 종래 적층형 버틈리드패키지에서 하부패키지의 와이어본딩 상태를 나타내 보인 평면도.Figure 2b is a plan view showing a wire bonding state of the lower package in a conventional stacked buried lid package.
도 2c는 종래 적층형 버틈리드패키지에서 엔시리드가 형성된 부분의 종단면도.Figure 2c is a longitudinal cross-sectional view of the portion where the enciride is formed in a conventional stacked buried lid package.
도 3a 내지 도 3c는 종래 적층형 버틈리드패키지의 제조공정을 순차적으로 나타내 보인 단면도.3A to 3C are cross-sectional views sequentially illustrating a manufacturing process of a conventional stacked buried lid package.
도 4는 본 발명에 따른 적층형 버틈리드패키지의 단면도.Figure 4 is a cross-sectional view of a laminated buried lid package according to the present invention.
도 5a는 본 발명에 따른 적층형 버틈리드패키지에서 상부패키지의 와이어본딩 상태를 나타내 보인 저면도.Figure 5a is a bottom view showing a wire bonding state of the upper package in the laminated buried lid package according to the present invention.
도 5b는 본 발명에 따른 적층형 버틈리드패키지에서 하부패키지의 와이어본딩 상태를 나타내 보인 평면도.Figure 5b is a plan view showing a wire bonding state of the lower package in the laminated buried lid package according to the present invention.
도 5c는 본 발명에 따른 적층형 버틈리드패키지에서 엔시리드가 형성된 부분의 종단면도.Figure 5c is a longitudinal cross-sectional view of the portion formed encirid in the stacked buried lid package according to the present invention.
도 6a 내지 도 6c는 본 발명에 따른 적층형 버틈리드패키지의 제조공정을 순차적으로 나타내 보인 단면도.6a to 6c are cross-sectional views sequentially showing a manufacturing process of the stacked buried lid package according to the present invention.
〈 도면의 주요부분에 대한 부호설명〉<Code Description of Major Parts of Drawings>
11,11' : 반도체칩 11a,11a': 칩패드11,11 ': semiconductor chip 11a, 11a': chip pad
12,12' : 상부 및 하부리드 12a' : 인너리드12,12 ': upper and lower lead 12a': inner lead
12b' : 아웃리드 13,13' : 와이어12b ': out lead 13,13': wire
14,14' : 몰딩부 15,15' : 상부 및 하부패키지14,14 ': molding part 15,15': upper and lower package
16 : 솔더 21a,21a': 엔시칩패드16 solder 21a, 21a ': chip chip pad
21b,21b': 옵셔널패드 22,22' : 엔시리드21b, 21b ': Optional pad 22,22': Ensilead
상기 목적을 달성하기 위하여, 본 발명인 적층형 버틈리드패키지는 다수개의 칩패드가 형성된 상부 반도체칩의 하면 양측에 상부리드들이 나열되고, 상기 상부리드들과 상기 칩패드는 상부와이어로 각각 연결되며, 상기 상부리드들의 하면이 외부로 노출되며 칩을 감싸도록 상부몰딩부가 형성되어 상부패키지를 구성하고, 상기 상부패키지의 하측에는 상기 상부리드와 대응되도록 인너리드와 아웃리드로 형성된 하부리드와, 하부 반도체칩과, 하부와이어와, 하부몰딩부가 동일한 구조로 하부패키지를 구성하여 솔더에 의하여 서로 대향하도록 접합되는 적층형 버틈리드패키지에 있어서, 상기 상부패키지 및 하부패키지는 상기 상,하부와이어로 연결되지 않은 상기 엔시리드와 엔시칩패드가 구비되어 상기 엔시칩패드의 일측과 상기 칩패드의 일측을 전기적으로 연결하는 옵셔널패드가 형성되며, 상기 엔시리드는 상기 상,하부리드와 대향하여 솔더에 의하여 접합되도록 구성된다.In order to achieve the above object, the stacked buried lid package according to the present invention has upper leads arranged on both sides of a lower surface of an upper semiconductor chip on which a plurality of chip pads are formed, and the upper leads and the chip pads are connected to upper wires, respectively. An upper molding part is formed to cover the lower surface of the upper leads and surrounds the chip to form an upper package, and a lower lead formed of an inner lead and an out lead to correspond to the upper lead on the lower side of the upper package, and a lower semiconductor chip. And, the lower wire and the lower molding part constitute a lower package having the same structure and are bonded to face each other by solder, wherein the upper package and the lower package are not connected to the upper and lower wires. The lead and the chip chip pad is provided so that one side of the chip chip pad and one side of the chip pad are An optional pad for electrically connecting is formed, and the enceed lead is configured to be joined by solder to face the upper and lower leads.
그리고, 상기 적층형 버틈리드패키지의 제조방법은 다수개의 상부 칩패드와 상부 엔시칩패드 및 이 상부 엔시칩패드를 상부 칩패드와 전기적으로 연결하는 상부 옵셔널패드를 구비한 상부 반도체칩을 준비하고, 다수개의 시에스리드인 상부리드와 엔시리드를 준비한 다음, 상기 상부 칩패드를 상부 와이어에 의해 상부리드에 와이어본딩하며, 상부리드가 노출되도록 상부몰딩부를 형성하여 상부패키지를 완성하는 단계와; 다수개의 하부 칩패드와 하부 엔시칩패드 및 이 하부 엔시칩패드를 하부 칩패드와 전기적으로 연결하는 하부 옵셔널패드를 구비한 하부 반도체칩을 준비하고, 인너리드와 아웃리드를 가지는 시에스리드인 하부리드와 엔시리드를 준비한 다음, 상기 하부 칩패드를 하부 와이어에 의해 인너리드에 와이어본딩하며, 인너리드가 상부에서 노출되고 아웃리드가 하부에서 노출되도록 하부몰딩부를 형성하여 하부패키지를 완성하는 단계와; 상기 하부패키지를 그 인너리드가 상부로 향하도록 뒤집어 놓은 상태에서 상부패키지와 하부패키지를 얼라인한 다음, 상부리드와 하부리드의 인너리드를 솔더로 부착하여 적층시키는 단계와; 상기 하부패키지의 돌출된 아웃리드를 하측으로 절곡하는 단계의 순서로 제조되는 것을 특징으로 한다.In addition, the method of manufacturing the stacked buried lid package may include preparing an upper semiconductor chip including a plurality of upper chip pads, an upper chip chip pad, and an upper optional pad electrically connecting the upper chip chip pad to the upper chip pad. Preparing a plurality of sheath leads and an upper lead, and then wire bonding the upper chip pad to the upper lead by an upper wire, and forming an upper molding part to expose the upper lead, thereby completing the upper package; A lower semiconductor chip having a plurality of lower chip pads, lower enci chip pads, and lower optional pads electrically connecting the lower chip pads with the lower chip pads, and having a inner lead and an out lead, After preparing the lead and ensiride, wire bonding the lower chip pad to the inner lead by the lower wire, and forming a lower molding portion so that the inner lead is exposed from the top and the outer lead is exposed from the bottom to complete the lower package; ; Aligning the upper package and the lower package with the inner package turned upside down so that the inner package faces upward, and then laminating by attaching the inner lead of the upper lead and the lower lead with solder; It is characterized in that it is manufactured in the order of the step of bending the protruding outlead of the lower package downward.
이하 본 발명의 바람직한 일실시례를 첨부 도면에 의거하여 상세히 설명하면 다음과 같다.BEST MODE Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4는 상기 적층형 버틈리드패키지의 단면도로서, 도시된 바와 같이, 다수개의 칩패드(11a)가 형성된 상부 반도체칩(11)의 하면 양측에 상부리드(12)들이 나열되고, 상기 상부리드(12)들과 상기 칩패드(11a)는 상부와이어(13)로 각각 연결되며, 상기 상부리드(12)들의 하면이 외부로 노출되며 칩(11)을 감싸도록 상부몰딩부(14)가 형성되어 상부패키지(15)를 구성하고, 상기 상부패키지(15)의 하측에는 상기 상부리드(12)와 대응되도록 인너리드(12a')와 아웃리드(12b')로 형성된 하부리드(12')와, 하부 반도체칩(11')과, 하부와이어(13')와, 하부몰딩부(14')가 동일한 구조로 하부패키지(15')를 구성하여 솔더(16)에 의하여 서로 대향하도록 접합된다.FIG. 4 is a cross-sectional view of the stacked buried lid package, and as shown, upper leads 12 are arranged on both sides of a lower surface of the upper semiconductor chip 11 on which a plurality of chip pads 11a are formed, and the upper leads 12 ) And the chip pad 11a are connected to the upper wire 13, respectively, and the upper molding part 14 is formed to cover the lower surface of the upper leads 12 and to surround the chip 11. The lower lead 12 'formed of an inner lead 12a' and an out lead 12b 'to correspond to the upper lead 12 is formed on the lower side of the upper package 15, and a lower portion of the upper package 15, The semiconductor chip 11 ', the lower wire 13', and the lower molding portion 14 'form the lower package 15' in the same structure and are bonded to each other by the solder 16.
상기 적층형 버틈리드패키지에서 상기 상부패키지(15) 및 하부패키지(15')는 도 5a와 도 5b에서 와이어본딩된 상태를 도시한 바와 같이, 상기 상,하부와이어(13,13')로 연결되지 않은 상기 엔시리드(22,22')와 엔시칩패드(21a,21a')가 한쌍씩 구비되어 상기 엔시칩패드(21a,21a')의 일측과 시에스리드와 연결된 칩패드(11a,11a')의 일측을 전기적으로 연결하는 옵셔널패드(21b,21b')가 형성되며, 도 5c에 도시된 바와 같이, 상부패키지(15) 및하부패키지(15')에 형성된 엔시리드(22,22')는 시에스리드인 상기 상,하부리드(12,12')와 대향하여 솔더(16)에 의하여 접합되도록 구성된다.In the stacked buried lid package, the upper package 15 and the lower package 15 'are not connected to the upper and lower wires 13 and 13' as shown in FIG. 5A and FIG. 5B. And the chip pads 11a and 11a 'which are connected to one side of the chip chip pads 21a and 21a' and the sheath lead. Optional pads 21b and 21b 'are formed to electrically connect one side of the end pads, and as shown in FIG. 5C, the encides 22 and 22' formed in the upper package 15 and the lower package 15 'are formed. Is configured to be joined by the solder 16 to face the upper and lower leads 12 and 12 'which are sheath leads.
이하, 상기와 같이 구성된 본 발명에 따른 적층형 버틈리드패키지의 제조방법을 설명하면 다음과 같다.Hereinafter, the manufacturing method of the laminated buried lid package according to the present invention configured as described above are as follows.
먼저, 하면에 칩패드(11a)와 엔시칩패드(21a)와 욥셔널패드(21b)가 형성된 상부 반도체칩(11)과 상면에 칩패드(11a')와 엔시칩패드(21a')와 욥셔널패드(21b')가 형성된 하부 반도체칩(11')를 준비하고, 상부 반도체칩(11)은 상부리드(12)에, 하부 반도체칩(11')은 하부리드(12')의 인너리브(12a')에 다이본딩한 한 다음, 상부 반도체칩(11)의 칩패드(11a)와 상부리드(12)를 상부 와이어(13)로 와이어 본딩하고, 하부 반도체칩(11')의 칩패드(11a')와 하부리드(12')의 인너리드(12a')를 하부 와이어(13')로 와이어 본딩한다.상기 상부리드(12)와 하부리드(12')에는 칩패드(11a,11a')에 와이어 본딩되지 않는 엔시리드(22,22')가 구비된다.또한 상기 엔시칩패드(21a,21a')는 욥셔널패드(21b,21b')에 의하여 자체적으로 칩패드(11a,11a')에 전기적으로 연결된 상태로 형성되는 것이다.상,하부 반도체칩(11,11')와 상,하부리드(12,12')가 와이어 본딩된 후 상부 반도체칩(11)은 상부리드(12)가 저면에서 노출되도록 상부 몰딩부(14)로 몰딩하고, 하부 반도체칩(11')은 하부리드(12')의 인너리드(12a')가 상면에서 노출됨과 아울러 아웃리드(12b')가 측부와 하면에서 노출되도록 하부 몰딩부(14')로 몰딩하여 상,하부 패키지(15,15')를 제조한다.다음, 도 6c와 같이 하부패키지(15')를 아웃리드(12b')가 하부를 향하고 인너리드(12a'가 상부를 향하도록 한 상태에서 상부 패키지(15)의 하면에서 노출된 상부리드(12)와 하부 패키지(15')의 상면에서 노출된 인너리드(12a')를 얼라인한 다음 이드르 상부리드(12)와 인너리드(12a')를 솔더(16)에 의하여 본딩하여 서로 전기적으로 접속되면서 적층된 하나의 반도체 패키지가 이루어지도록 한다.이때, 상,하부 패키지(15,15')를 구성하는 상,하부 반도체칩(11,11')의 상기 엔시칩패드(21a,21a')는 옵셔널패드(21b,21b')에 의하여 칩패드(11a,11a')에 전기적으로 접속된 상태로 된다.First, the upper semiconductor chip 11 having the chip pad 11a, the nsi chip pad 21a, and the job pad 21b formed on the lower surface thereof, and the chip pad 11a ', the nsi chip pad 21a', and the job formed on the upper surface thereof. A lower semiconductor chip 11 'having a national pad 21b' is prepared, and the upper semiconductor chip 11 is on the upper lead 12, and the lower semiconductor chip 11 'is on the inner rib of the lower lead 12'. After die bonding to 12a ', the chip pad 11a and the upper lead 12 of the upper semiconductor chip 11 are wire-bonded with the upper wire 13, and the chip pad of the lower semiconductor chip 11'. 11a 'and the inner lead 12a' of the lower lead 12 'are wire bonded to the lower wire 13'. The chip pads 11a and 11a are attached to the upper lead 12 and the lower lead 12 '. 'Are provided with ensileads 22 and 22' which are not wire bonded. The enci chip pads 21a and 21a 'are themselves chip pads 11a and 11a by job pads 21b and 21b'. ') Is electrically connected to the upper and lower semiconductor chips 11 and 11. ') And the upper and lower leads 12 and 12' are wire-bonded, and the upper semiconductor chip 11 is molded into the upper molding part 14 so that the upper lead 12 is exposed from the bottom, and the lower semiconductor chip 11 ') Is molded into the lower molding part 14' such that the inner lead 12a 'of the lower lead 12' is exposed from the upper surface and the outlead 12b 'is exposed from the side and the lower surface. Next, the upper package 15 with the lower package 15 'with the outlead 12b' facing downward and the inner lead 12a 'facing upward as shown in FIG. 6C. The inner lead 12a 'exposed at the upper surface of the upper lead 12 and the lower package 15' exposed at the bottom of the aligner is aligned, and then the upper lead 12 and the inner lead 12a 'are soldered. Bonded to each other to be electrically connected to each other to form a stacked semiconductor package. At this time, the upper and lower peninsula constituting the upper and lower packages (15, 15 ') Chip (11,11 ') they dont the chip pads (21a, 21a') of is in a state of being electrically connected to the optional pad (21b, 21b ') (chip pads 11a, 11a) by a'.
그런 다음, 하부패키지(15')의 돌출된 아웃리드(12b')를 하측으로 절곡하여 적층형 버틈리드패키지를 완성한다.Then, the protruding outlead 12b 'of the lower package 15' is bent downward to complete the stacked buried lid package.
이상에서 설명한 바와 같이, 본 발명에 의한 적층형 버틈리드패키지 및 제조방법은 반도체칩의 상면에 옵셔널패드와 상부리드 및 칩패드를 형성하고, 시에스칩패드와 엔시칩패드를 전기적으로 연결시키는 옵셔널패드를 설치함으로써, 버틈리드패키지의 적층시 리드프레임과의 와이어본딩을 선택적으로 연결하여 메모리 용량을 증대시킬 수 있는 효과가 있다.As described above, in the stacked buried lid package and the manufacturing method according to the present invention, an optional pad and an upper lead and a chip pad are formed on the upper surface of the semiconductor chip, and the optional chip electrically connects the chip chip pad and the chip chip pad. By providing the pad, there is an effect that the memory capacity can be increased by selectively connecting the wire bonding with the lead frame when stacking the gap lead package.
Claims (2)
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