KR100335401B1 - Forming method for overlay vernier of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a supervisor of a semiconductor device, wherein an overlay vernier for measuring an overlap between an upper electrode and a lower electrode and a metal wiring contact in a ferroelectric RAM (FeRAM) manufacturing process is scribe lane. Formed by the same process, but using the upper electrode as a mother, and forming a metal wiring contact mask of the intaglio pattern on the upper portion so that the adhesive layer and the lower electrode is not exposed on the upper part to form the son to the adhesive layer during the cleaning process after forming the superimposed It is a method of improving the process yield and device operation reliability by preventing the penetration of the cleaning liquid and the lifting of the superpositioner to facilitate the alignment and superposition of wafers.

Description

Forming method for overlay vernier of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a superimposed layer of a semiconductor device, and in particular, an upper electrode is used as a mother during a FeRAM forming process, and a lower cross during a cleaning process is performed by using a cross-shaped metal wiring contact mask having a central portion formed of a chromium pattern as a son. A method of preventing the electrode and the adhesive layer from being exposed by lifting.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size, which makes it difficult to secure device characteristics and high integration such as refresh time. Background Art A method of using a film, forming a thin film of a dielectric film, or increasing the surface area of a storage electrode has emerged.

However, all of these methods have their respective problems.

In other words, in order to increase the storage electrode surface area of the capacitor, a polysilicon layer is formed in a multi-layer, and a pin structure is formed to penetrate and connect them to each other, or a cylindrical storage electrode is formed on the contact. Although a method of increasing the level of the capacitor, as described above, increases the level between the cell area and the peripheral circuit area by the capacitor, which adversely affects the subsequent process, and thinning the thickness of the dielectric film is a uniformity of the film. It is difficult to secure the properties, and there is a problem that the dielectric film is destroyed during operation of the device, which seriously affects the reliability of the capacitor.

In addition, dielectric materials having high dielectric constants of several hundreds to thousands of dielectric constants, such as Ta ₂ O ₅ , TiO ₂ or SrTiO ₃ , have been studied for use as dielectric films. Many studies are necessary because the same reliability and thin film characteristics are not clearly confirmed.

A ferroelectric film, a material with a high dielectric constant, is a nonvolatile memory that stores data even when the power is turned off by thinning it into a ferroelectric having a dielectric constant ranging from several hundreds to thousands at room temperature and having two stable polarization states. It is applied to the development of FeRAM capacitors.

On the other hand, as the design rule becomes smaller, the overlay accuracy in the photographic process becomes more and more important. The overlay measurement error includes factors derived from equipment called TIS (tool induced shift) and factors called wafer induced shift (WIS) resulting from the process. The factor caused by the WIS is pointed out mainly by the geometric pattern distortion due to non-uniform matrial deposition on the wafer.

In addition, as the number of metal layers increases, the introduction of a chemical mechanical polishing (CMP) process and the study of new materials are accelerated, resulting in a problem that the overlap measurement error exceeds the overlay budget. The metal layer deposited at high temperature is composed of large size grains, which appear as noise in the overlapping equipment, which is an optical metrolgy, which is an obstacle in measuring accurate overlap. A typical case of the overlap measurement error by the WIS is metal layer deposition by a sputtering method. Overlapping error due to process varies depending on the type of superposition. The shape, size, and area of the superposition differs depending on how the design of the superposition is applied. It is possible to prevent the lifting of the thin film due to chemical attack of the cleaning solution. In particular, the lifting of the overlapper not only has a great effect on the characteristics of the device, but also has a huge effect on the yield.

Hereinafter, a method of forming a superposed layer of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a method of forming a superposed layer on a metal wiring contact during a FeRAM manufacturing process in a method of forming a superposed layer of a semiconductor device according to the related art.

First, a planarization layer 12 having a storage electrode contact plug (not shown) is formed on a semiconductor substrate 11 having a cell region and a scribe lane region in which a predetermined substructure is formed.

Next, an adhesive layer 13 is formed on the planarization film 12 by using a Ti film.

Next, the lower electrode thin film 14, the ferroelectric film 15, and the upper electrode thin film 16 are sequentially stacked on the adhesive layer 13.

Next, a first photoresist layer 17 pattern is formed on the upper electrode thin film 16 to protect a portion of the semiconductor substrate 11 that is intended as the upper electrode.

In this case, the first photoresist layer 17 pattern is formed by an exposure and development process using an upper electrode mask (not shown).

Subsequently, the upper electrode thin film 16, the ferroelectric film 15 and the lower electrode thin film 14 are etched using the first photoresist film 17 as a mask, and the first photoresist film 17 pattern. Remove it. (See FIG. 1A, FIG. 1B)

Next, a second photoresist layer (not shown) is formed on the cell region and the scribe lane region to protect a portion intended as a lower electrode, and the adhesive layer 13 is etched using the mask as a mask (see FIG. 1C).

Next, an interlayer insulating film 18 is formed over the entire surface.

A third photoresist layer 19 pattern is formed on the interlayer insulating layer 18 to expose a portion of the interlayer insulating layer 18. In this case, the third photoresist layer pattern 19 is formed by an exposure and development process using a metal wiring contact mask (not shown). (See FIG. 1D, FIG. 1E)

Next, the interlayer insulating layer 18 on the cell region and the interlayer insulating layer 18 on the scribe lane region are etched using the third photoresist layer 19 as a mask.

Then, the third photoresist film 19 pattern is removed, and then a cleaning process is performed.

The pattern formed by the process is used as a superimposition, and the superimposition is formed in the form of a box in a box in which a small rectangular box is placed inside a large rectangular box.

As described above, in the method of forming a superimposition of a semiconductor device according to the related art, the superimposition is simultaneously formed in a scribe lane area during a manufacturing process of a FeRAM in a cell region, and the lower electrode and the adhesive layer pattern used as a mother in forming the superimposition are formed. Exposed during the etching process using a third photosensitive film pattern used as an etching mask, the cleaning liquid penetrates into the adhesive layer pattern during the subsequent cleaning process to weaken the adhesive force of the adhesive layer, as shown in FIG. There is a problem that the lifting phenomenon occurs.

The present invention is to solve the above problems of the prior art, by using a metal wiring contact mask of the cathode pattern during the FeRAM manufacturing process as son son to prevent the adhesive layer and the lower electrode is exposed after the etching process to lift the superimposed after the cleaning process It is an object of the present invention to provide a method for forming a superimposition of a semiconductor device, which prevents and improves characteristics and reliability of the device.

1A to 1G are cross-sectional views illustrating a method of forming a supervisor of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of forming a superposed layer of a semiconductor device according to an embodiment of the present invention.

3A-3C are plan views of overlay vernier formed in accordance with the present invention.

<Description of Signs of Major Parts of Drawings>

11, 21: semiconductor substrate 12, 22: planarization film

13, 23: adhesive layer 14, 24: lower electrode

15, 25: ferroelectric film 16, 26: upper electrode

17, 27: first photosensitive film 18, 29: interlayer insulating film

19,28: second photosensitive film 30: third photosensitive film

Ⓐ: Chrome pattern ⓑ: Transparent window

In order to achieve the above object, a method of forming a superimposed member of a semiconductor device according to the present invention,

In the method of forming a superimposition of a semiconductor device having a mother and a son,

Sequentially forming a planarization film, an adhesive layer, a thin film for lower electrode, a ferroelectric film, and a thin film for upper electrode in a scribe lane region on a semiconductor substrate;

A process of forming an upper electrode to be used as a mother by etching the thin film for the upper electrode by a photolithography process using a top electrode mask having a square transparent window at the center to protect a predetermined portion as the upper electrode;

Etching the dielectric film, the lower electrode, and the adhesive layer by a photolithography process using a lower electrode mask;

Forming an interlayer insulating film over the entire surface;

Forming a photoresist pattern having a shape to be used as a son in an exposure and development process using a metal wiring contact mask on the interlayer insulating film, wherein the metal wiring contact mask is formed of a transparent window provided with a chrome pattern of a cross shape in the center; ,

Etching the interlayer insulating layer by using the photoresist pattern as an etching mask to form a son-son;

Removing and cleaning the photoresist pattern is characterized in that it comprises a superimposed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method of forming a superposed layer of a semiconductor device in accordance with the present invention, and FIGS.

First, a planarization layer 22 having a storage electrode contact plug (not shown) is formed on a semiconductor substrate 21 having a cell region and a scribe lane region in which a predetermined substructure is formed.

Next, an adhesive layer 23 is formed on the planarization layer 22 to a thickness of 10 to 2000 micrometers using a Ti or TiN film.

Next, the lower electrode thin film 24, the ferroelectric film 25 and the upper electrode thin film 26 are sequentially stacked on the adhesive layer 23.

Here, the lower electrode thin film 24 and the upper electrode thin film 26 are formed to have a thickness of 10 to 10000 Å using a Pt, Ir, IrO ₂ , Ru, or RuO ₂ film, and the ferroelectric film 25 is formed of PZT ( It is formed to a thickness of 10 to 20000 GPa using Pb (Zr _x Ti _1-x ) O ₃ ) or SBT film (SrBi ₂ Ta ₂ O ₉ ).

Next, a portion of the first photoresist layer 27 is formed by an exposure and development process using a top electrode mask (not shown) having a square transparent window at the center thereof, while protecting a portion intended to be an upper electrode. The upper electrode thin film 26 is etched to form an upper electrode.

In this case, as shown in FIG. 3B, the first photoresist layer 27 has a small square transparent window ⓑ formed inside a large square of a chrome pattern ⓐ.

Next, the first photoresist layer 27 pattern is removed. (See FIGS. 2A, 2B, 3B)

Then, the second photosensitive film 28 is applied over the entire surface.

The second photoresist layer 28 pattern is formed by an exposure and development process using a lower electrode mask (not shown).

Next, the ferroelectric layer 25, the lower electrode thin film 24, and the adhesive layer 23 are etched using the second photoresist layer 28 as a mask, and then the second photoresist layer 28 pattern is removed. .

Thereafter, an interlayer insulating film 29 is formed over the entire surface. (See FIG. 2C, FIG. 2D)

In addition, a third photoresist layer 30 pattern is formed on the interlayer insulating layer 29 to expose a portion of the interlayer insulating layer 29.

In this case, the third photoresist layer 30 pattern is formed by an exposure and development process using a metal wiring mask (not shown). Here, the metal wire contact mask (not shown) is used as the son as the reference to the upper electrode and the cross-shaped central portion is formed in a chrome pattern, each formed of a transparent window separated in four directions.

In addition, the process of forming the third photoresist layer 30 pattern is performed using g-line, I-line, KrF, ArF, E-beam or X-ray as a light source, and the photoresist layer is a no-block type, a positive chemically amplified type. Or negative chemical amplification. (See Figure 2E)

Subsequently, the interlayer insulating layer 28 on the cell region and the interlayer insulating layer 28 on the scribe lane region are etched using the metallization contact mask 29 as an etching mask.

Next, the third photoresist layer 29 pattern is removed and a cleaning process is performed.

The cleaning process is carried out using a dip or spray method on an acid solution containing amine, a basic solvent for removing a polymer, a basic solvent for a positive resist strip, and a fluoride.

The superimposed by the superimposed method of the semiconductor device is formed as shown in Fig. 3c.

The width z of the upper electrode used as the mother and the width x of the transparent window are each 0.2-200 μm, and the portion y having the chrome pattern in the center of the metal wiring contact mask, which is the son, is 0.2-200 μm, and the width w of the transparent window in the son. And the distance v at which the son and the mother overlap each other are 0.2 to 100 µm.

As described above, in the method of forming a supervisor of a semiconductor device according to the present invention, the FeRAM is formed on a scribe lane while forming the FeRAM in order to measure the overlap between the upper electrode and the lower electrode and the metal wiring contact in the FeRAM manufacturing process. The formation process is performed in the same manner so that the center layer is formed in the shape of a crisscross-shaped transparent window formed by a chrome pattern so that the adhesive layer and the lower electrode are not exposed. By preventing self-lifting to facilitate wafer alignment and overlay measurement, there is an advantage of improving process yield and device operation reliability and reliability of semiconductor devices.

Claims (9)

In the method of forming a superimposition of a semiconductor device having a mother and a son, Sequentially forming a planarization film, an adhesive layer, a thin film for lower electrode, a ferroelectric film, and a thin film for upper electrode in a scribe lane region on a semiconductor substrate; Forming a top electrode to be used as a mother by etching the thin film for the top electrode by a photolithography process using a top electrode mask having a square transparent window at the center to protect a portion intended to be an upper electrode; Etching the dielectric film, the lower electrode, and the adhesive layer by a photolithography process using a lower electrode mask; Forming an interlayer insulating film over the entire surface; Forming a photoresist pattern having a shape to be used as a son in an exposure and development process using a metal wiring contact mask on the interlayer insulating film, wherein the metal wiring contact mask is formed of a transparent window provided with a chrome pattern of a cross shape in the center; , Etching the interlayer insulating layer by using the photoresist pattern as an etching mask to form a son-son; Removing the photoresist pattern and cleaning to form a superimper. The method of claim 1, The width of the transparent window of the upper electrode mask is 0.2 to 200㎛ each method of forming a superimposed semiconductor device. The method of claim 1, The center of the metal wiring contact mask has a chrome pattern of 0.2 ~ 200㎛ size, the superimposed method of forming a semiconductor device, characterized in that. The method of claim 1, The transparent window of the metallization contact mask has a width of 0.2 to 100㎛, the method of forming a superposed semiconductor device. The method of claim 1, And a distance between the transparent window and the upper electrode mask of the metal wiring contact mask is 0.2 to 100 µm. The method of claim 1, The adhesive layer is formed using a Ti or TiN film of 10 ~ 2000Å thick layered semiconductor device, characterized in that formed. The method of claim 1, And forming the lower electrode thin film and the upper electrode thin film to a thickness of 10 to 10000 microns using any one of Pt, Ir, IrO ₂ , Ru, and RuO ₂ films. The method of claim 1, The ferroelectric film is formed using a PZT or SBT film with a thickness of 10 to 20000 Å, the superimposed method of forming a semiconductor device. The method of claim 1, The cleaning process is a method of forming a superimposed semiconductor device, characterized in that the dipping or spraying method using an acid solution containing a basic solvent for removal of polymer, a basic solvent for positive resist styrene or fluorine containing amine.