KR100331464B1 - Arbitration Apparatus And Method Of First In First Out Menory - Google Patents

Abstract

In the arbitration apparatus of the receiving FIFO for a plurality of ATM cell high-speed communication channels, even if there are several receiving cells in each of the plurality of receiving FIFOs, the FIFOs are read one by one in turn, thereby losing data received due to flooding of cells stored in the FIFO. To prevent it.

The present invention includes a process of checking a flag signal of a FIFO in charge of its own by operating a priority counter by a synchronization signal according to a main clock signal; If the checked flag signal is in an activated state, applying a read signal to a corresponding FIFO side for one period of a main clock to output received and stored cell information; Determining whether an activation state is detected in a flag signal of another FIFO while the output of cell information received and stored in the corresponding FIFO is in progress; When the activation state is detected in the flag signal of the other FIFO, applying a control signal for transitioning to inactivation to the FIFO outputting the current cell information and taking over the possession right to the next counter side; And when the output of the cell information received by the FIFO in charge of the next counter is completed during one period of the main clock, taking over the possession right to the other next counter.

Accordingly, the problem of overflowing the cell information received and stored by sequential reading of the cell information received and stored in the FIFO is eliminated, thereby providing reliability to the operation of the system.

Description

Arbitration Apparatus And Method Of First In First Out Menory}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an arbitration apparatus of a first in first out (FIFO) receiver for a plurality of ATM (Asynchronous Transfer Mode) cell high speed communication channels. First-in, first-out memory arbitration apparatus and method to prevent the data received due to overflow of the cell stored in the FIFO by allowing each FIFO to be sequentially read once even if there are multiple receiving cells from each communication channel. It is about.

A matching device of a receiving FIFO for a plurality of ATM cell high speed communication channels, which typically receives ATM cells through a plurality of high speed communication channels and multiplexes them into a single link matching means, as shown in FIG. And a plurality of FIFOs 20a-20d, a reception arbitration unit 30, a cell shift module 40, and a link matching unit 50. The plurality of high-speed bus matching units 10a. -10d) matches the high speed communication channels (TAXI1-TAXI4) in 8-bit parallel through each high speed serial bus.

FIFOs 20a-20d are connected to the four high-speed bus matching units 10a-10d through 8-bit parallels ((CA0-CA7), (CB0-CB7), (CC0-CC7), (CD0-CD7)). Cell information connected to each of the high speed bus matching units 10a-10d and synchronized with the main clock signal MCLK is stored in synchronization with the main clock signal MCLK, and the cells of each FIFO 20a-20d are stored through the flag signals FLG1-FLG4. Information about the state is applied to the reception arbitration unit 30, and first-in, first-out output of the stored cell information according to the read signal / RD1- / RD4 applied from the reception arbitration unit 30.

The FIFOs 20a-20d are deactivated when output is performed even with one byte of information of one cell consisting of 53 bytes according to the read signal / RD1- / RD4 of the reception arbitration unit 30. Transition.

The reception arbitration unit 30 analyzes the flag signals FLG1-FLG4 applied from the FIFOs 20a-20d and outputs cell information stored in the FIFOs 20a-20d according to the main clock signal MCLK. The read signal / RD1- / RD4 is outputted.

The cell shift module 40 is connected in parallel with the FIFOs 20a-20d and 8-bit (FCELL0-FCELL7) and multiplexes cell information applied from the FIFOs 20a-20d to the link matching unit 50. .

The link matching unit 50 is physically matched to the 155 Mbps STM-1 link, and transmits cell information applied from the cell shift module 40 in units of ATM cells according to a synchronization signal / MCS and a reference clock MCLK. Process and send on matched STM-1 link.

As shown in FIG. 2, the reception arbitration unit 30 includes a plurality of counters 31a-31d and a synchronization signal generator 32, each of which includes a plurality of counters 31a-31d. The flag signals FLG1-FLG4 of 20a-20d and the main clock signal MCLK are applied, and output a read signal / RD1- / RD4 for outputting cell information to the FIFO 20a-20d. The cell information read signal / RD1- / RD4 is applied to the next counter side.

The synchronization signal generator 32 generates a synchronization signal / MCS for the cell information read signal / RD1- / RD4 according to the main clock signal MCLK applied to the counters 31a-31d. Is authorized.

The sync signal / MCS maintains a 'low' state for one clock every 53 clock cycles of the main clock signal MCLK.

The plurality of counters 31a to 31d operate in association with each other, and the cell information read signal / RD1- / RD4 is activated by any one of four, and once activated, the corresponding FIFO 20a. The read signal / RD1-RD4 applied to the corresponding FIFOs 20a-20d is active while the received and stored cell is present at -20d, i.e., while the flag signals FLG1-FLG4 remain high. It keeps 'low' continuously.

At this time, no other counter can activate the cell information read signal and maintain the standby state.

In the conventional ATM cell fast communication channel receiving FIFO matching device configured as described above, the operation of arbitrating the output of the cell information received and stored in the plurality of FIFOs is as follows.

As shown in FIG. 4, the synchronization signal generator 32 generates the synchronization signal / MCS in a 'low' state for one clock period starting from the 53 clock periods of the main clock signal MCLK, which is the reference clock signal. When the first counter 31a is supplied to the plurality of counters 31a to 31d, the first counter 31a is operated first according to the priority of the operation (S10).

At this time, the first counter 31a detects and analyzes the flag signal FLG1 applied to notify the cell reception state information from the FIFO 20a connected thereto.

In the case where information of one cell (53 bytes) or more is stored from the high speed bus matching unit 10a through the 8-byte parallel bus CA0-CA7 in the FIFO 20a connected to the first counter 31a. Since the FIFO 20a connected to the first counter 31a outputs the flag signal FLG1 of its state as 'high', the read signal (/ RD4) applied from the fourth counter 31d, which is the previous counter. ) Determines whether the state of the deactivation (S20).

In order to shift the read signal / RD4 output from the fourth counter 31d, which is the previous counter of the first counter 31a, from the activated state to the deactivated state, the second and third counters 31b and 31c. This is possible when the read signal / RD2 (/ RD3) outputted from the PDP is already inactive.

When the read signal / RD4 output from the fourth counter 31d, which is the previous counter of the first counter 31a, is in an inactive state, the first counter 31a is applied from the synchronization signal generator 32. In synchronization with the synchronization signal / MCS, the read signal / RD1 for outputting the cell information stored on the FIFO 20a side is driven to a low state of being activated.

Accordingly, the FIFO 20a is activated for 53 clocks so as to read information of one cell by the main clock signal MCLK (S30).

When 53 bytes of information about a cell stored in the FIFO 20a are output by the above operation, the first counter 31a receives the flag signal FLG1 applied from the FIFO 20a connected thereto. If it is recognized that the received stored cell is in an active state where the stored cell continues to exist, the read signal / RD1 for outputting the received cell information is continuously maintained as 'low' as the activated state, and the corresponding FIFO 20a It continues until the flag signal FLG1 applied in transitions to 'low', which is an inactive state (S40) (S50).

At this time, when the flag signal FLG1 for the received cell information applied to the first counter 31a in the FIFO 20a becomes inactive, the read signal / RD1 for outputting the received cell information is a synchronization signal (/ In synchronism with MCS), the state becomes inactive and the next counter 31b takes over the priority right, and notifies the state of inactivation (S60).

The second counter 31b having the next priority proceeds in the same manner as the operation of the first counter 31a as described above, and the flag signal FLG2 from the FIFO 20b connected to the second counter 31b. ) Becomes the deactivated state from the activated state, the priority is passed to the third counter 31c.

As described above, the operation of arbitrating the plurality of FIFOs to output the cell information stored in the FIFOs 20a-20d through the high speed bus matching units 10a-10d to a single link matching unit is performed by the counters 31a-31d. Repeating in an endless loop according to the priority of, the information of one 53-byte cell output from each FIFO (20a-20d) through the cell shift module 40 to physically match the 155Mbps class STM-1 link The link matching unit 50 transmits the applied cell information in units of ATM cells according to a main clock and a synchronization signal.

As described above, in the conventional apparatus for arbitrating a plurality of ATM FIFO reception FIFOs, when a plurality of cells are stored in one FIFO, and a flag output from the FIFO remains active, the reception arbitration means has a corresponding FIFO. Since the read signal is kept in the active state until the output of the cell information stored in the FIFO is activated, a time delay occurs in outputting the cell information stored in the other FIFO. There is a problem that the cell information is lost because the received cell information overflows.

In addition, in the process of outputting cell information received in one FIFO, a large amount of FIFO must be applied to stably store cell information received in another FIFO. There was this.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described general problems, and its object is to arbitrate so that the cell information stored in each FIFO is sequentially outputted once to the FIFO even if a plurality of cells are received and stored in a plurality of ATM cell reception FIFOs. It is to provide reliability and stability to the transmission processing of ATM cell information by excluding flooding of cell information received and stored.

In addition, by controlling the cell information received and stored in a plurality of FIFOs sequentially one by one according to the priority, by applying a FIFO having a small memory to maintain a stable transmission process of the cell information to reduce the production cost in the implementation of the system I did it.

1 is a block diagram showing a conventional first-in, first-out first memory matching device for a plurality of AT cells.

FIG. 2 is a detailed block diagram of the reception arbitration unit shown in FIG. 1; FIG.

3 is a flowchart illustrating an operation of performing reception cell information arbitration in a conventional first-in first-out memory matching device for a plurality of AT cells.

4 is an operation timing diagram for performing reception cell information arbitration in a conventional first-in, first-out memory arbitration apparatus.

5 is a block diagram of a first-in, first-out memory arbitration apparatus according to the present invention;

6 is a flowchart illustrating an operation of performing reception cell information arbitration in a first-in, first-out memory arbitration apparatus according to the present invention.

7 is an operation timing diagram for performing reception cell information arbitration in a first-in, first-out memory arbitration apparatus according to the present invention.

<Description of the symbols for the main parts of the drawings>

300a-300d; Counters 310a-310d; Arbitrator

400; Synchronization signal generator

In order to achieve the above object, the present invention provides a mediation apparatus for an ATM cell information receiving FIFO, comprising: a plurality of bus matching means for matching each of a plurality of communication channels with a serial bus, and through each bus matching means; A plurality of FIFOs for storing the received cell information, multiplexing means for multiplexing the cell information output from the plurality of FIFOs, and link matching means for processing the multiplexed cell information as a physical layer and transmitting it through a physical link. However, each of the plurality of FIFOs is sequentially read to mediate the output of stored cell information, and if cell information is stored in another FIFO after cell information stored in a certain FIFO is read at a predetermined period, the current FIFO is read. And an arbitration means for handing over the possession right to the FIFO in which the cell information is stored.

Another feature of the present invention is a method of arbitrating a first-in, first-out memory that arbitrates the output of ATM cell information received and stored in a plurality of FIFOs, wherein a priority counter is operated by a synchronization signal according to a main clock signal. Checking a flag signal of a FIFO being performed; If the checked flag signal is in an activated state, applying a read signal to a corresponding FIFO side for one period of a main clock to output received and stored cell information; Determining whether an activation state is detected in a flag signal of another FIFO while the output of cell information received and stored in the corresponding FIFO is in progress; When the activation state is detected in the flag signal of the other FIFO, applying a control signal for transitioning to inactivation to the FIFO outputting the current cell information and taking over the possession right to the next counter side; If the output of the cell information received to the FIFO in charge of the next counter is completed during one period of the main clock, the step of taking over the right to occupy the other next counter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Since the matching apparatus of the receiving FIFO for the plurality of ATM cell high speed communication channels according to the present invention is implemented in the same manner as the structure of FIG. 1, description thereof will be omitted, and a single link matching means may be used to store cell information received and stored in the plurality of FIFOs. Only the implementation of an arbitration device that arbitrates to be output on a physical link will be described.

As can be seen in FIG. 5, the FIFO arbitration apparatus according to the present invention includes a plurality of counters 300a-300d, an arbiter 310a-310d, and a synchronization signal generator 400. -300d) is implemented in a number corresponding to the FIFO to handle each of a plurality of FIFO for receiving and storing the cell information applied through the high-speed communication channel, the plurality of arbitrators (310a-310d) are the plurality of counters Only one cell consisting of 53 bytes is output to the control signal (/ RD1- / RD4) implemented one by one at 300a-300d to output the cell information received and stored in the FIFO in charge of each counter 300a-300d. It then takes over the function of taking over the priority of channel occupancy to the counter of the next rank.

The synchronization signal generator 400 outputs a 'low' state for one clock every main clock signal (MCLK) cycle of the system applied to 53 clocks to match the output synchronization of the cell information received and stored in the FIFO.

Each of the counters 300a-300d includes a flag signal FLG1-FLG4 corresponding to a storage state of a cell received and stored in a FIFO, a main clock signal MCLK of the system applied to the 53 clock, and a synchronization signal generator ( A synchronization signal (/ MCS) output from 400, a signal for controlling the FIFO in charge from the arbitrators 310a-310d in charge of it and a signal for controlling the FIFO from the arbiter in charge of the previous counter are connected. According to each signal, a read signal (/ RD1- / RD4) for controlling whether or not the cell information received and stored in the FIFO in charge is outputted.

The arbiter 310a-310d implemented in each of the plurality of counters 300a-300d analyzes a flag signal of another FIFO not owned by its counters 300a-300d to determine its counter and the next counter. Apply a signal.

Through the arbitration apparatus of the present invention implemented as described above, the operation of arbitrating such that ATM cell information received and stored in a plurality of FIFOs is transmitted through one link matching means is as follows.

5 is implemented as shown in FIG. 5 in a state in which cell information applied through the express bus matching unit 10a-10d corresponding to each of the reception FIFOs 20a-20d for the ATM cell high speed communication channel formed as shown in FIG. 1 is stored. As shown in FIG. 7, the synchronization signal generator 400 in the reception arbitration apparatus generates the synchronization signal / MCS in the 'low' state during one clock of the main clock signal MCLK period applied in 53 clock periods. And the first and fourth counters 300a and 300d configured to correspond to the FIFOs 20a and 20d, respectively (S110).

In this case, the first to fourth counters 300a to 300d may first operate the first counter 300a according to the internal priority, so as to flag a cell reception storage state applied from the FIFO 20a in charge of the first to fourth counters 300a to 300d. When the signal FLG1 is checked and the flag signal FLG1 to be checked is recognized as 'high', which is a state of receiving and storing information of one cell (53 bytes), the arbiter 310d of the previous counter 300d. Check whether the read occupancy rights (input and output ports Q2, A) are taken over (S120).

When the read occupancy right is determined to be taken over from the arbiter 310d of the fourth counter 300d, which is the previous counter, the first counter 300a outputs the cell information received to the FIFO 20a in charge. As shown in the timing diagram of FIG. 7, the read signal / RD1 is driven to 'low' as an activation, and the 'low' signal of the driven activation is driven by the main clock signal MCLK. Hold for 53 clocks so that it can be read (S130).

At this time, when the read signal / RD1 for outputting the cell information received and stored in the FIFO 20a is activated once, the first mediator 310a operates to apply the flag signal FLG2 applied from another FIFO 20b-20d. -Checks the FLG4) to check whether any of the 'high' states of activation is detected (S140). In step S140, the flag signals FLG2-FLG4 applied from the other FIFOs 20b-20d are checked. When no high is detected, the first mediator 310a determines whether the current FIFO 20a is in an active state based on the read signal / RD1 (S170). When the current FIFO 20a is in an activated state, the first counter 300a is controlled to maintain the read signal / RD1 of the FIFO 20a in an activated state (S180), and the current FIFO 20a is controlled. If it is in an inactive state, the first mediator 310a takes over the possession right to the next counter (S160).

In step S140, when any one of the flag signals FLG2-FLG4 of the other FIFOs 20b-20d is detected by the first mediator 310a, the first mediator 310a detects a high state. A control signal is applied to the first counter 300a to cause the read signal / RD1 outputted to the responsible FIFO 20a to be inactivated (S150).

Accordingly, the first counter 300a synchronizes the read signal / RD1 outputted to the FIFO 20a to which the first counter 300a is applied, according to the control signal applied from the first mediator 310a. Transitioning from the low state of the active state to the high state of the deactivation state according to the synchronization signal applied from the first moderator 310a, the first mediator 310a receives the flag signals FLG2-FLG4 from the other FIFOs 20b-20d. Occupancy is transferred to the next counter in order to output the cell information received and activated in the next FIFO 20b-20d due to the detection of the activation state (S160).

As described above, when the first counter 300a takes over the possession right to the second counter 300b, which is the next counter, when the flag signal FLG2 is detected as 'high', the second counter 300b is activated. Sets the read signal / RD2 to output the received and stored cell information to the FIFO 20b in charge thereof as 'low' as an active state, and detects the flag signal FLG2 as 'low' as a deactivated state. If the second mediator 310b immediately transfers the possession right to the third counter 300c, which is the next counter.

In addition, the second counter 300b is detected by the second mediator 310b while applying the read signal / RD2 for outputting the received and stored cell information to the FIFO 20b side in charge of the second counter 300b. When there is a signal detected in the activated state among the flag signals FLG3, FLG4, and FLG1, the second mediator 310b deactivates the output of the read signal / RD2 on the side of the second counter 300b. At the same time as the 'high' output is transferred to the third counter 300c side occupancy right.

The third counter 300c, when the detected flag signal FLG3 is detected to be 'high' in an activated state, the third counter 300c outputs a read signal / RD3 for outputting cell information received and stored to the FIFO 20c in charge of the third counter 300c. In synchronism with the synchronization signal / MCS, when the flag signal FLG3 is detected as low when the flag signal FLG3 is inactivated, the third mediator 310c immediately moves to the next counter. The possession right is handed over to the counter 300d side.

As described above, the counter controls the cell information received and stored in its FIFO to be output only for one clock cycle, and then transfers the occupancy right to the next counter and detects the cell information received and stored in the FIFO in charge of the next counter. If not, the action to immediately transfer the title to the next counter is to be executed repeatedly.

As described above, the present invention controls only one cell information (53 bytes) among the cell information stored in the FIFO in arbitrating the received and stored cell information so that the cell information stored in the plurality of FIFOs is outputted through one link matching unit. After taking over the occupancy right, if the cell information stored in the FIFO is not detected, the control right is taken over immediately so that the stored cell information is output to the next FIFO. This eliminates the problem of flooding cell information received and stored by sequential reading of cell information received and stored in the FIFO, thereby providing reliability in the operation of the system, and applying cell capacity by applying a small amount of FIFO due to the sequential reading operation. It keeps stable and reduces manufacturing cost.

Claims (5)

In the arbitration apparatus of ATM cell information receiving FIFO, Multiplexing a plurality of bus matching means for matching each of the plurality of communication channels to a serial bus, a plurality of FIFOs storing cell information received through the respective bus matching means, and multiplexing cell information output from the plurality of FIFOs. And multiplexing means and link matching means for processing the multiplexed cell information into a physical layer and transmitting the same through a physical link. Reads each of the plurality of FIFOs sequentially to mediate the output of stored cell information, and outputs the cell information stored in a certain FIFO at a predetermined period, and if the cell information is stored in another FIFO, the read occupancy right of the FIFO currently in progress. And an arbitration means for taking over the FIFO in which the cell information is stored. The method of claim 1, The arbitration means is implemented in a number corresponding to each of the plurality of FIFO, the plurality of outputting a read signal for controlling the output of the received and stored cell information according to the flag signal in the FIFO in charge for one clock period A counter; If an activation is detected in a flag signal of another FIFO in a state in which a read signal for controlling cell information output is output to any counter means among the plurality of counter means, the right of occupancy is transferred to the next counter means and the read signal currently output. A plurality of arbiters for transitioning to a state of inactivation; And a synchronization signal generator for generating a synchronization signal for outputting a read signal to the plurality of counters according to a main clock signal. In the mediation method of the first-in, first-out memory to mediate the output of ATM cell information received and stored in a plurality of FIFO, Checking a flag signal of a FIFO in charge of the counter by operating a priority counter according to a synchronization signal according to a main clock signal; If the checked flag signal is in an activated state, applying a read signal to a corresponding FIFO side for one period of a main clock to output received and stored cell information; Determining whether an activation state is detected in a flag signal of another FIFO while the output of cell information received and stored in the corresponding FIFO is in progress; When the activation state is detected in the flag signal of the other FIFO, applying a control signal for transitioning to inactivation to the FIFO outputting the current cell information and taking over the possession right to the next counter side; And if the output of the cell information received in the FIFO in charge of the next counter is completed during one period of the main clock, taking over the right to occupy the next next counter side. The method of claim 3, wherein In accordance with detection of a flag of another FIFO maintaining the activation, reading only one cell information stored in the corresponding FIFO, and reacquiring the right to occupy the first-in first-out memory. The method of claim 3, wherein If a flag signal is detected that a plurality of cells are stored in a plurality of FIFO at the same time, the first-in, first-out memory arbitration method characterized in that to read sequentially one cell from each FIFO according to the arbitration of the possession.