KR100329609B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR100329609B1
KR100329609B1 KR1019950050456A KR19950050456A KR100329609B1 KR 100329609 B1 KR100329609 B1 KR 100329609B1 KR 1019950050456 A KR1019950050456 A KR 1019950050456A KR 19950050456 A KR19950050456 A KR 19950050456A KR 100329609 B1 KR100329609 B1 KR 100329609B1
Authority
KR
South Korea
Prior art keywords
metal
forming
semiconductor device
insulating film
metal wiring
Prior art date
Application number
KR1019950050456A
Other languages
Korean (ko)
Other versions
KR970052797A (en
Inventor
박흥락
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019950050456A priority Critical patent/KR100329609B1/en
Publication of KR970052797A publication Critical patent/KR970052797A/en
Application granted granted Critical
Publication of KR100329609B1 publication Critical patent/KR100329609B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to block the absorption of moisture into a planarized insulating layer by remaining a metal film as a passivation layer at outline of die. CONSTITUTION: A lower insulating layer(2) and the first metal line(3) are sequentially formed on a silicon substrate(1). The first insulating layer(4), a planarized insulating layer(5) and the second insulating layer(6) are sequentially formed on the resultant structure. A contact hole is formed to expose the first metal line(3) by etching the insulating layers. The second metal line(7) is formed in the contact hole so as to connect the first metal line. At this time, the second metal film(11) as a passivation layer remains at an outline(10) of a die in order to block the absorption of moisture into the planarized insulating layer(5).

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 고집적 반도체 소자의 제조공정에 있어서 반도체 소자 다이(Die) 최외곽면에 노출되어 있는 평탄화 절연막인 에스.오.지(Spin-On-Glass; 이하 SOG 라 칭함.)나 폴리마이드(Polyimide) 면을 금속박막으로 막아 대기중의 수분이 상기 평탄화 절연막 내부로 침투하는 것을 방지하여 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있게하는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the manufacturing process of a highly integrated semiconductor device, S. O. (Spin-On-Glass), which is a planarization insulating film exposed on the outermost surface of a semiconductor device die, is described below. SOG.) Or a polyimide surface by using a metal thin film to prevent moisture in the air from penetrating into the planarization insulating film to improve the yield and reliability of semiconductor devices. It is about.

일반적으로 반도체 소자 제조공정중에서 금속배선의 층수가 2층이상이 될 경우에는 1층금속과 2층금속사이에 전기절연막이 사용되며, 이때 2층배선의 용이한 형성을 위해 층간 절연막의 평탄화 공정이 필연적이다.In general, when the number of layers of metal wiring becomes more than two layers in the semiconductor device manufacturing process, an electrical insulating film is used between the one-layer metal and the two-layer metal, and in this case, the planarization of the interlayer insulating film is performed to facilitate the formation of the two-layer wiring. It is inevitable.

상기 층간 절연막의 평탄화 방법에는 여러가지 방법이 있는데 그중에서 SOG 나 Polyimide 등과 같은 재료들을 화학증착으로 증착된 절연막과 공동으로 사용하는 층간 절연막 형성방법이 가장 널리 사용되고 있다.There are various methods of planarization of the interlayer insulating film. Among them, an interlayer insulating film forming method using materials such as SOG or polyimide in combination with an insulating film deposited by chemical vapor deposition is most widely used.

제 1 도는 종래의 기술에 따른 다층금속배선 구조의 단면도이다.1 is a cross-sectional view of a multilayer metallization structure according to the prior art.

상기 제 1 도에 도시된 바와같이, 종래의 다층금속배선 공정에 있어서는 SOG 나 Polyimide과 같은 재료가 금속배선공정이 완료된 후 다이의 최외각변, 즉 반도체 소자의 스크라이브 영역(10)과 반도체 다이 영역(9)과의 접합부에 노출이 된다. 이때 상기 노출된 표면의 SOG나 Polyimide 절연막(5)은 흡습성 및 통습성이 매우 크기 때문에 노출된 부위를 통해 대기중의 수분이 도시된 침투경로(8)를 따라 흡습 및 소자 내부로 전달되어 소자의 부식 및 소자 특성의 악화를 유발하게 되는 문제점이 있다.As shown in FIG. 1, in the conventional multilayer metallization process, a material such as SOG or Polyimide is the outermost side of the die, that is, the scribe region 10 and the semiconductor die area of the semiconductor device after the metallization process is completed. It exposes to the junction part with (9). At this time, since the SOG or the polyimide insulating film 5 of the exposed surface is very hygroscopic and hygroscopic, moisture in the air is transferred to the inside of the device according to the penetration path 8 where the moisture in the air is exposed through the exposed part. There is a problem that causes corrosion and deterioration of device characteristics.

따라서 본 발명은 상기의 문제점을 해결하기 위한 것으로, 반도체 소자의 다이 외곽면에 노출되어 있는 평탄화 절연막을 금속박막으로 막아 대기중의 수분이 막 내부로 침투 하는 것을 방지함으로써 수분침투로 인한 반도체 소자의 특성저하를 예방할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above problems, by blocking the planarization insulating film exposed to the die outer surface of the semiconductor device with a metal thin film to prevent the moisture in the air to penetrate into the film of the semiconductor device due to moisture penetration It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing the deterioration of characteristics.

상기 목적을 달성하기 위한 본 발명은 실리콘 기판 상부에 하부 절연막과 제1금속배선을 차례로 형성하는 단계와,The present invention for achieving the above object comprises the steps of sequentially forming a lower insulating film and a first metal wiring on the silicon substrate;

상기 제1금속배선 상부에 제1절연막을 형성하는 단계와,Forming a first insulating layer on the first metal wiring;

상기 제1절연막 상부에 평탄화 절연막을 형성하는 단계와,Forming a planarization insulating film on the first insulating film;

전체구조 상부에 제2절연막을 형성하는 단계와,Forming a second insulating film on the entire structure;

상기 제1금속배선의 상부에 위치한 상기 제2절연막과 평탄화 절연막 및 제1절연막을 차례로 식각하여 콘택홀을 형성하는 단계와,Forming a contact hole by sequentially etching the second insulating layer, the planarizing insulating layer, and the first insulating layer on the first metal wiring;

상기 전체구조 상부에 제2금속층을 형성하는 단계와,Forming a second metal layer on the entire structure;

상기 제2금속층을 노광 및 식각하여 제2금속배선을 형성하는 단계를 구비하는 반도체 소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device comprising the step of exposing and etching the second metal layer to form a second metal wiring,

상기 제2금속배선 형성을 위한 제2금속층 식각시, 반도체 소자 다이 외곽변에 위치한 부위의 금속은 식각되지 않고 금속 보호막으로 잔류시켜 상기 평탄화 절연막을 통한 수분의 흡수를 차단시키는 것을 특징으로 한다.When the second metal layer is etched to form the second metal wiring, the metal of the portion located at the outer edge of the semiconductor device die is not etched and remains as a metal protective film to block absorption of moisture through the planarization insulating film.

이하, 첨부 도면을 참조하여 본 발명의 상세한 설명을 하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 2 도는 본 발명에 따른 다층금속배선 구조의 단면도이다.2 is a cross-sectional view of a multi-layered metal wiring structure according to the present invention.

상기 제 2 도에 도시된 바와같이, 본 발명에서는 반도체 소자의 다이 외곽면(10)에 노출되어 있는 SOG나 Polyimide 면(5)을 제2금속 보호막(11)으로 막아 대기중의 수분이 SOG 나 폴리마이드막(5) 내부로 침투하는 것을 방지한다.As shown in FIG. 2, in the present invention, the SOG or polyimide surface 5 exposed to the die outer surface 10 of the semiconductor device is blocked by the second metal protective film 11 so that moisture in the air is reduced to SOG or Penetration into the polyamide film 5 is prevented.

제2금속배선(7)을 형성하는 공정에 있어서, 제1금속배선(3)과 제2금속배선(7)의 전기 통전을 위한 콘택을 형성 할 때 다이의 외곽면(10)도 제2도와 같이 형성한다. 그후 SOG 박막(5)의 디개싱((degassing) 과정과 사전 크리닝(pre-cleaning) 과정을 거쳐서 제2금속배선(7)을 증착시키게 된다. 그후 제2금속배선(7)에 대한 노광과 식각 공정을 거쳐서 제2금속배선(7)을 제2도와 같이 형성하게 되는데, 이때 다이 외곽의 에지(edge) 부분을 식각하지 않고 남겨둠으로써 SOG가 노출되는 외곽면(10)을 금속박막(11)으로 덮게 된다.In the process of forming the second metal wiring 7, the outer surface 10 of the die when forming a contact for the electrical conduction between the first metal wiring 3 and the second metal wiring 7 is also shown in FIG. Form together. Thereafter, the second metal wiring 7 is deposited through degassing and pre-cleaning of the SOG thin film 5. The exposure and etching of the second metal wiring 7 are then performed. Through the process, the second metal wiring 7 is formed as shown in FIG. 2, in which the edge 10 of the die is left without etching, thereby leaving the outer surface 10 on which the SOG is exposed. Will be covered.

이때 상기 제2금속배선(7)은 알루미늄, 타이타늄, 타이타늄 나이트라이드, 텅스텐 등의 금속박막이 될 수 있으며, 상기 금속들을 조합한 복층, 3층 구조일 수도 있다.In this case, the second metal wiring 7 may be a metal thin film of aluminum, titanium, titanium nitride, tungsten, or the like, and may have a multi-layered and three-layered structure combining the metals.

이상, 상술한 바와같이 본 발명의 기술에 따라 반도체 소자의 최외곽면에 노출되어 있는 흡습성이 강한 평탄화 절연막의 SOG 나 폴리마이드를 금속박막으로 막으므로써 대기중의 수분이 절연막 내부로 침투되는 것을 막을 수 있고, 이로인해 반도체 소자의 특성저하를 방지할 수 있다.As described above, according to the technique of the present invention, by blocking the SOG or polyamide of the highly hygroscopic planarization insulating film exposed to the outermost surface of the semiconductor device with a metal thin film, it is possible to prevent the moisture in the atmosphere from penetrating into the insulating film. This can prevent the deterioration of the characteristics of the semiconductor device.

제 1 도는 종래의 기술에 따른 다층금속배선 구조의 단면도1 is a cross-sectional view of a multi-layered metal wiring structure according to the prior art.

제 2 도는 본 발명에 따른 다층금속배선 구조의 단면도2 is a cross-sectional view of a multi-layered metal wiring structure according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 하부 절연막1: silicon substrate 2 lower insulating film

3 : 제1금속배선 4 : 제1절연막3: first metal wiring 4: first insulating film

5 : 제2절연막(SOG 또는 Polyimide)5: second insulating film (SOG or Polyimide)

6 : 제2절연막 7 : 제2금속배선6: second insulating film 7: second metal wiring

8 : 수분침투경로 9 : 다이(Die)영역8: moisture penetration path 9: die area

10 : 최외곽영역10: outermost zone

Claims (5)

실리콘 기판 상부에 하부 절연막과 제1금속배선을 차례로 형성하는 단계와,Sequentially forming a lower insulating film and a first metal wiring on the silicon substrate; 상기 제1금속배선 상부에 제1절연막을 형성하는 단계와,Forming a first insulating layer on the first metal wiring; 상기 제1절연막 상부에 평탄화 절연막을 형성하는 단계와,Forming a planarization insulating film on the first insulating film; 전체구조 상부에 제2절연막을 형성하는 단계와,Forming a second insulating film on the entire structure; 상기 제1금속배선의 상부에 위치한 상기 제2절연막과 평탄화 절연막 및 제1절연막을 차례로 식각하여 콘택홀을 형성하는 단계와,Forming a contact hole by sequentially etching the second insulating layer, the planarizing insulating layer, and the first insulating layer on the first metal wiring; 상기 전체구조 상부에 제2금속층을 형성하는 단계와,Forming a second metal layer on the entire structure; 상기 제2금속층을 노광 및 식각하여 제2금속배선을 형성하는 단계를 구비하는 반도체 소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device comprising the step of exposing and etching the second metal layer to form a second metal wiring, 상기 제2금속배선 형성을 위한 제2금속층 식각시, 반도체 소자 다이 외곽변에 위치한 부위의 금속은 식각되지 않고 금속 보호막으로 잔류시켜 상기 평탄화 절연막을 통한 수분의 흡수를 차단시키는 것을 특징으로 하는 반도체 소자의 제조방법.In the etching of the second metal layer for forming the second metal wiring, the metal of the portion located on the outer edge of the semiconductor device die is not etched and remains as a metal protective film to block absorption of moisture through the planarization insulating film. Manufacturing method. 제 1 항에 있어서The method of claim 1 상기 평탄화 절연막은 흡습성이 큰 SOG 또는 Polyimide 같은 재료로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The planarization insulating film is a method of manufacturing a semiconductor device, characterized in that formed of a material such as SOG or polyimide having high hygroscopicity. 제 1 항에 있어서The method of claim 1 상기 제2금속배선 재료는 알루미늄, 타이타늄, 타이타늄 나이트라이드, 텅스텐중 어느 하나인 것을 특징으로 하는 반도체 소자의 제조방법.The second metal wiring material is a method of manufacturing a semiconductor device, characterized in that any one of aluminum, titanium, titanium nitride, tungsten. 제 1 항에 있어서The method of claim 1 상기 제2금속배선 형성시 금속입자를 물리증착법이나 화학증착법으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.When the second metal wiring is formed, the metal particles are formed by physical vapor deposition or chemical vapor deposition. 제 1 항에 있어서The method of claim 1 상기 금속 보호막의 형성은 3층 이상의 다층배선 공정에서 최고층 금속배선 형성공정에서 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.Forming the metal protective film is a semiconductor device manufacturing method, characterized in that formed in the uppermost metal wiring forming process in a multi-layer wiring process of three or more layers.
KR1019950050456A 1995-12-15 1995-12-15 Method for manufacturing semiconductor device KR100329609B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950050456A KR100329609B1 (en) 1995-12-15 1995-12-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050456A KR100329609B1 (en) 1995-12-15 1995-12-15 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR970052797A KR970052797A (en) 1997-07-29
KR100329609B1 true KR100329609B1 (en) 2002-11-07

Family

ID=37479141

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950050456A KR100329609B1 (en) 1995-12-15 1995-12-15 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR100329609B1 (en)

Also Published As

Publication number Publication date
KR970052797A (en) 1997-07-29

Similar Documents

Publication Publication Date Title
US7553756B2 (en) Process for producing semiconductor integrated circuit device
US7732897B2 (en) Methods of die sawing and structures formed thereby
US5659201A (en) High conductivity interconnection line
US7999382B2 (en) Semiconductor device and fabrication method for the same
JPH08191104A (en) Semiconductor integrated circuit device and manufacturing method thereof
US20070042600A1 (en) Method for fabricating semiconductor device
US5900644A (en) Test site and a method of monitoring via etch depths for semiconductor devices
JPH11330231A (en) Metal coat structure
US5702956A (en) Test site and a method of monitoring via etch depths for semiconductor devices
JP3530073B2 (en) Semiconductor device and manufacturing method thereof
US20040033685A1 (en) Aluminum/copper clad interconnect layer for VLSI applications
JPH04167449A (en) Semiconductor device
KR900007757B1 (en) Semiconductor device and the manufacturing method
KR100329609B1 (en) Method for manufacturing semiconductor device
KR100459723B1 (en) Method for fabricating semiconductor device having metal interconnections of different thickness
JPH0677315A (en) Semiconductor device
US6897136B2 (en) Method for forming fuse in semiconductor device
KR0137434B1 (en) Semiconductor device & process for manufacturing the same
KR100467815B1 (en) Semiconductor device and fabrication method thereof
KR100613384B1 (en) Method of forming interconnection line for semiconductor device
KR100418920B1 (en) Method for forming interconnection of semiconductor device
KR100613382B1 (en) Method of manufacturing semiconductor device
KR100193889B1 (en) Via hole formation method of semiconductor device
KR20050032305A (en) Method of forming metal line in semiconductor devices
JPH09326433A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110222

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee