KR100327332B1 - Embedded self repair method and apparatus for embedded memory - Google Patents

Abstract

An integrated self-recovery method and apparatus for an internal memory capable of recovering all of the bad cell (s) present in the internal memory using a plurality of redundant rows (or columns) and at least one redundant row (or rows). To start. M (≥1) redundancy minors and N (N≥M≥1) redundancy majors that replace the bad cell (s) of the memory embedded in the microcomputer, The method includes determining that if a plurality of defective cells each having the same major direction address (hereinafter referred to as a major hit bad cell) is detected, the plurality of major hit bad cells are recovered using an available redundant major. If more than N bad cells (hereinafter, referred to as minor hit bad cells) each having an address in the same minor direction are detected, using redundant redundancy miner capable of using more than N minor hit bad cells The redundancy may be used to determine which ones to recover and to which bad cells (hereinafter referred to as non-hit bad cells) that do not have the same major address or minor address to each other are available. When the number of surges and the number of usable redundancy miners are detected equal to or less than the sum of the numbers, determining that non-hit bad cells are recovered first using available redundancy major and then using available redundancy minor later. It is characterized by including.

Description

Embedded self repair method and apparatus for embedded memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the repair of bad cells in a memory, and more particularly, to a self-healing method and apparatus for an internal memory capable of recovering all recoverable bad cell (s) present in the memory.

For example, memory embedded in a circuit is more integrated than other logic devices and is more likely to fail due to more shared signals. Therefore, by using redundant cells provided to improve the yield of such a memory, it is possible to recover the cells of the bad memory. Built-in self repair (BISR) circuitry provides for the software to recover the bad cells of the memory within the circuit, and recovers the bad cell (s) according to the memory bad cell recovery method. Therefore, compared to the case of searching for and recovering a defective cell by an external test equipment, the time and cost required for the memory test and the defective cell recovery can be reduced. The conventional memory bad cell recovery method and the BISR circuit performing the same can be best applied only when one redundant row and one redundant column are used to recover the defective cell (s). That is, in the conventional memory bad cell recovery method, when a plurality of redundant rows or columns are used to recover a bad cell, the bad cell (s) may be recovered, but as described later, a situation in which it cannot be recovered is described. Can be generated.

Meanwhile, terms used in the method for recovering a defective cell of a memory will be briefly described as follows.

A repair is a replacement of rows and columns of memory with redundant or redundant columns to increase memory yield. The redundancy row or the redundancy column refers to rows and columns that are additionally made to replace rows or columns to which a bad cell belongs when a bad cell is detected during a memory test. The bad cell recovery method of the memory refers to a method of determining an order of replacing a row or column of a memory to which a bad cell belongs with a redundant row and a redundant column. Depending on the order of replacing a bad cell with a redundant cell array by a bad cell recovery method, the recoverable memory may or may not be recovered. An entry refers to a register that stores information about a bad cell, that is, row and column addresses of a bad cell, in a memory test. A hit means that the row address or column address of the currently detected bad cell matches the row address or column address of the previously detected bad cell.

The conventional bad cell recovery method recovers existing bad cells by using one redundant row and one redundant column. Table 1 below shows the types of data stored in entries.

Entry 0 Entry 1 valid 0 valid 1 row0 must row1 must column0 must column1 must row0 address row1 address column0 address column1 address unrepairable

Here, 'valid0' is a bit indicating whether data written in the first entry (Entry0) is valid, and 'row0 must' indicates that the row address of the currently detected bad cell is equal to the row address (row0 address) of the first entry (entry0). If hit, a bit that is '1' means to use redundancy row to recover bad cell, and 'column0 must' means that the column address of currently detected bad cell is the column address of the first entry (entry0). ) And a bit that becomes '1' when hit, meaning that the redundancy column is to be used to recover a bad cell, and 'row0 address' means the row address of the first bad cell that occurred, and 'col0 address' 'Is the column0 address of the first bad cell,' valid1 'is a bit indicating whether the data stored in the second entry (entry1) is valid data, and' row1 mu ' st 'is a bit that becomes' 1' when the row address of the currently detected bad cell is hit with the row address of the second entry entry1, and 'column1 must' means that the column address of the currently detected bad cell is '1' is a bit that becomes '1' when hit with the column address of the second entry (entry1), and 'row1 address' is the row of the next detected bad cell in which the row address and the first detected bad cell do not match. The col1 address means a column address of a first bad cell detected and a next bad cell detected when the column address does not match. In addition, 'unrepairable' is a bit that becomes '1' when a bad cell cannot be recovered with two redundant cell arrays, that is, redundant rows and redundant columns.

Hereinafter, a bad cell recovery method of a conventional memory will be described as follows.

First, when a bad cell FO is detected, the row and column addresses of the FO are stored in the first entry (entry0). Next, if a bad cell F1 is detected, it is determined whether the row and column addresses of F1 match the row or column addresses of the FO stored in the entryent0. If the row addresses match, row0 must be set to '1' and the first operation described below is performed. If the column addresses match, column0 must be set to '1' and the second operation described below is performed. If they do not coincide with the row and column addresses of F0 respectively stored in entryent0, the third operation described later is performed after storing the column and row addresses of F1 in entry1.

Referring to the first operation, if row0 must becomes '1', it is determined whether the row address of the detected bad cell F2 matches the row address stored in the entryent0, and if it matches, the next bad cell is detected. However, if the row address of F2 does not match the row address stored in entryent0, after storing the row and column addresses of F2 in entry1, the row address of the next bad cell F3 is stored in entryent0. If it does not match by matching the row address or the column address of F3 with the column address stored in entry1, F3 determines that it cannot be recovered, and if it matches, then detects the next bad cell. At this time, if the failure of all the cells of the memory is detected, the method of detecting a defective cell of the memory is terminated.

Referring to the second operation, if a bad cell F2 is detected after column0 must becomes '1', it is determined whether the column address of F2 matches the column address stored in the entry (entry0), and if it matches, the next bad cell is detected. However, if the column address of F2 does not match the column address stored in entryent0, then the row and column addresses of F2 are stored in entry1, and then the row address of the next bad cell F3 is stored in entry1. If it does not match by determining whether it matches the row address or the column address of F3 matches the column address stored in entry0, F3 determines that it cannot be recovered, and if it matches, then detects the next bad cell. At this time, if the failure of all the cells of the memory is detected, the method of detecting a defective cell of the memory is terminated.

Referring to the third operation, after storing the column and row addresses of F1 in the entry1, the order of detecting the bad cell F2 and replacing the bad cell F2 with the redundant cell array is determined according to two conditions as follows. do.

As a first condition, if the row address of F2 matches the row address stored in entryent0 or the column address of F2 matches the column address stored in entry1, row0 must be set to '1' or column1 must set to '1'. Next, if the row address of the bad cell F3 matches the row address stored in the entry entry0 or the column address of the F3 matches the column address stored in the entry entry1, the next bad cell is matched. If it detects or terminates the method of detecting bad cells in the memory, but does not match, F3 determines that it cannot be recovered.

As a second condition, if the row address of F2 matches the row address stored in entry1 or the column address of F2 matches the column address stored in entry0, row1 must be set to '1' or column0 must set to '1'. If the row address of the bad cell F3 matches the row address stored in the entry1 or the column address of the F3 matches the column address stored in the entry0, the next bad cell is detected. Or, if the method of detecting bad cells in the memory is terminated but does not match, F3 determines that it cannot be recovered.

Hereinafter, a conventional memory bad cell recovery method for recovering bad cells existing as shown in FIG. 1 will be described as follows to help understanding a conventional memory bad cell recovery method.

FIG. 1 is a diagram for explaining a conventional method for recovering a defective memory cell, and includes a memory 10, a redundancy row 12, and a redundancy column 14.

In the conventional memory bad cell recovery method, when bad cells are located as shown in FIG. 1, first, the bad cell F0 is detected and the row and column addresses of the detected F0 are stored in an entry0. Next, the detected row and column addresses of F1 are compared with the row and column addresses of F0 stored in entry0, and row0 must is set to '1 since the row address of F1 is hit with the row address of the FO stored in entry0. ' Next, the detected row and column addresses of F2 are compared with the row and column addresses of F0 stored in entryent0, and F2 because the row and column addresses of F2 are not hit with the row and column addresses of F0, respectively, Stores row and column addresses in entry1. The detected row and column addresses of F3 are then compared with the row and column addresses stored in entries 0 and 1. Since column address of F3 is hit with column address of F2, column1 must be set to '1'.

As such, the conventional memory bad cell detection method may be usefully applied to recover the bad cells F0, F1, F2 and F3 using one redundant column 14 and one redundant row 12. . That is, the defective cells that have not yet recovered after making a hit must occur first are recovered using the remaining redundant row or redundant column.

However, in the conventional memory bad cell recovery method, when the bad cells are recovered using one redundant row and two redundant columns, the following problems may occur.

FIG. 2 is another diagram for explaining an application example of a conventional memory failure cell recovery method, and includes a memory 20, one redundant row 22, and two redundant columns 24 and 26.

In order to recover the bad cells present in the memory 20 shown in FIG. 2, the number of entries used is four. This is because the number of entries required for repairing bad cells is generally 2 * m * n (where m means the number of redundant rows and n means the number of redundant columns).

First, the detected row and column addresses of F0 are stored in entryent0, and then the detected column and row addresses of F1 are compared with the column and row addresses stored in entryent0. At this time, since the row address of F1 matches the row address of F0 stored in the entry entry0, row0 must be set to '1'. That is, redundancy row 22 is used to recover F0 and F1. Next, the column and row addresses of the detected bad cell F2 are compared with the column and row addresses of F0 stored in the entry0, and are not matched. Therefore, the column and row addresses of F2 are stored in the entry1. . Then, the detected row and column addresses of F3 match the row addresses stored in the entryent0 and the column addresses stored in the entryent1, respectively, and do not match. Therefore, the row and column addresses of F3 are not matched. Store in Next, compare the detected row address of F4 with the column address stored in entryent0 and whether the column address of F4 matches the column address stored in entriesent1 and 2, and do not match. The column and row addresses of F4 are stored in the entry entry3. Therefore, in the conventional bad cell detection method of the memory, the columns to which the bad cells F2 and F3 belong can be replaced with the redundant columns 24 and 26, respectively, using the column and row addresses stored in the entries entries1 and entry2. However, it is determined that the bad cells F4 and F5 cannot be recovered.

As a result, F0 and F5 shown in FIG. 2 can be recovered by replacing with redundant columns 24, F1 and F2 can be recovered by replacing with one redundant array of columns 26 and F3 and F4 In spite of being able to recover by replacing the old row 22, the conventional memory bad cell detection method has a problem that only F0, F1, F2 and F3 shown in Fig. 2 can be recovered.

That is, the conventional memory bad cell recovery method can be usefully applied when there are one redundant row and one redundant row, and according to the presence pattern of the defective cell existing in a situation in which there are a plurality of redundant rows and / or redundant columns. There is a problem that recoverable bad cells cannot be recovered.

In addition, when there are a plurality of redundant columns and one redundant row, or a plurality of redundant columns and a redundant column, a pair of two redundant arrays of cells is used to recover bad cells. Although there are methods for recovering bad cells in memory, the cell recovery of this conventional method is quite low.

SUMMARY OF THE INVENTION The first technical problem to be solved by the present invention is to provide a self-healing method for an internal memory capable of recovering all the defective cell (s) present in the internal memory by using a plurality of redundant rows and at least one redundant column. To provide.

A second technical problem to be solved by the present invention is to provide a self-healing method for an internal memory capable of recovering all the defective cell (s) present in the internal memory using a plurality of redundant columns and at least one redundant row. To provide.

A third technical object of the present invention is to use a plurality of redundant rows and at least one redundant row or at least one redundant row and a plurality of redundant columns to identify bad cell (s) present in an embedded memory. It is to provide a built-in self-healing device for all the recoverable internal memory.

1 is a view for explaining a conventional memory bad cell recovery method.

FIG. 2 is another diagram for explaining an application example of a conventional memory failure cell recovery method.

3 is a flowchart illustrating a built-in self-healing method for an internal memory according to the present invention.

4 is a view for explaining a built-in self-healing method for an internal memory according to the present invention.

5 is a block diagram of a built-in self-healing device for an embedded memory according to the present invention for performing the method shown in FIG.

In order to achieve the above object, the built-in memory has M (≥ 1) redundancy minor and N (N≥M≥ 1) redundancy major to replace the defective cell (s) of the memory embedded in the microcomputer, The microcomputer performing the method for recovering the bad cells of the plurality of micro-computers uses the plurality of the major hit bad cells when a plurality of bad cells (hereinafter, referred to as major hit bad cells) each having an address in the same major direction is detected. Determining to recover using the redundancy major if possible, and if more than N bad cells (hereinafter referred to as minor hit bad cells) each having the same minor direction address are detected, more than N Determining to recover the minor hit bad cells using the redundant redundancy miner and the same major address or minor major When non-bad bad cells (hereinafter referred to as non-heat bad cells) are detected as less than or equal to the sum of the number of available redundancy majors and the number of available redundancy miners, the non-heat bad cells are used. It is desirable to perform a built-in self-healing method, which comprises using the redundancy major as possible first and then deciding to use the redundancy minor available later to recover. The built-in self-healing device for recovering the bad cell (s) present in the memory using one redundant row and a plurality of redundant columns or one redundant column and a plurality of redundant rows is initialized in response to an initialization signal. To store the row and column addresses of the currently detected bad cell in response to a valid signal. An entry register that stores row and column addresses of the valid signal and previously detected bad cells and row and column must signals allowing use of the redundant row and the redundant column, and the current detection A row signal generator and row and column hits for comparing the row and column addresses of the bad cells that have been detected previously with the row and column addresses stored in the entry register, and outputting the compared results as row and column hit signals, respectively. In response to the signals, generate the valid signal and the row and column must signals, output the generated valid signal and the row and column must signals to the entry register, and determine whether the bad cell is recoverable. A signal stored in the entry register, comprising a recovery logic section for outputting a recovery status signal indicating To recover the bad cells using preferred.

Hereinafter, a built-in self-healing method for an embedded memory according to the present invention will be described with reference to the accompanying drawings. FIG. 3 is a flowchart illustrating a built-in self-healing method for an internal memory according to the present invention. Determining which redundant cell array is used to recover the defective cells in the redundant column or redundant row according to the respective conditions (steps 30 to 56).

First, at least one row-oriented redundancy cell array (hereinafter, referred to as redundant row) and at least one column-oriented redundant cell array (hereinafter, redundant) are used to recover bad cells existing in a memory. Can be applied to the case of using heat. In particular, the present invention is usefully used when using one redundant row and a plurality of redundant columns or using one redundant column and a plurality of redundant columns to recover a defective cell. A major means a row or a column having a relatively large number of redundant cell arrays, and a minor means a row or a column having a relatively small number of redundant cell arrays. For example, if there is one redundancy column and there are a plurality of redundancy rows, the major becomes a row and the minor becomes a column. Hereinafter, for the understanding of the present invention, the redundancy minor is M (where M is one or more). An integer), and a redundant major number is N (N ≧ M ≧ 1). In the built-in self-healing method for built-in memory according to the present invention, first, values stored in entries are initialized (step 30). At this time, 2 * M * N entries are required as described above. After the thirtieth step, it is determined whether a failure of all cells present in the memory has been examined (step 32). If the defects of all the cells in the memory have not been checked, it is determined whether the defective cells are detected by scanning the cells of the memory, and if the defective cells are not detected, the process proceeds to the thirty-second step (step 34).

However, if a bad cell is detected in the memory, a major address corresponding to the major direction address (hereinafter referred to as a major address) of the currently detected bad cell F _t is stored in the entry, and the redundancy major is previously detected. In step 36, it is determined whether all other bad cell (s) F _t-1 , F _t-2 ,... That is, it is determined whether the major of the currently detected bad cell F _t is a hit and the redundancy major can be used to recover the currently detected bad cell F _t .

If the major address corresponding to the major address of the currently detected bad cell F _t is stored in the entry, and the redundancy major is different, the bad cell (s) (F _t-1 , F _t-2 , ...) If all have not been used to recover, it is determined to recover the currently detected bad cell F _t using a redundant redundancy major and proceed to step 32 (step 38). That is, if the major of the currently detected bad cell F _t is a hit and the redundant major is available, the redundant major must be Musted, and then the process proceeds to step 32. Here, 'must redundancy major' indicates that a defective cell is replaced with a redundancy major and this information is stored in the entry.

However, no major address that matches the major address of the currently detected bad cell F _t is stored in the entry or the other bad cell (s) F _t-1 , F _t-2 , ... ) Is used to recover the detected bad cells, which correspond to the minor address (hereinafter referred to as the minor address) of the currently detected bad cell (F _t ) and stored in the entry (s). It is determined whether there is no redundancy major that can be used to recover (step 40). That is, if the major of the currently detected bad cell F _t is not a hit or the redundant major is not available, the minor of the currently detected bad cell F _t is a hit and the redundant major for cell recovery. Determine if all have been used.

If, the minor address matching the minor address of the bad cell (F _t) of the current detection is stored in the entry (s) and the wall imager that none exists for that it may be used to recover the bad cell (F _t) of the current detection Otherwise, it is determined to recover the bad cell F _t using redundant redundancy and proceeds to step 32 (step 42). That is, if the minor of the currently detected bad cell F _t is a hit and the redundancy major is used to recover the previously detected bad cells F _t-1 , F _t-2 ,... After making the redundancy miner must to recover the detected bad cell F _t , the process proceeds to step 32. Here, 'must redundancy miner' indicates that a defective cell is replaced with a redundancy miner, and this information is stored in the entry.

However, if minor address matching the minor address of the bad cell (F _t) of the current detection does not stored in the entry wall imager for that may be used to recover the bad cells are detected (F _t) is present, the current The minor address matching the minor address of the detected bad cell F _t is stored in the entry (s) and the minor address matching the minor address of the currently detected bad cell is stored in the entries by the number N of redundant majors. In step 44, it is determined. That is, if the minor number of the currently detected bad cell F _t is not a hit or the number of redundancy majors must be less than N, the minor number of the currently detected bad cell F _t is a hit and is hit until now. Determine if the minor is N + 1.

If a minor address that matches the minor address of the currently detected bad cell F _t is stored in the entry (s), and there are N stored minor entries in the entries that match the minor address of the detected bad cell. Then, it is determined to recover the defective cell F _t currently detected using the redundant minus and proceeds to step 32 (step 46). That is, if the miner of the currently detected bad cell F _t is a hit and there are N + 1 miners hit so far, the redundant miner is used as a must to recover the bad cell F _t currently detected, and the thirty-second Proceed to step.

However, than N in the minor address an entry that minor address matching the minor address of the bad cell (F _t) of the current detection does not stored in the entry matches the minor address of the bad cell (F _t) of the current detection If less is stored, it is determined that there is at least one entry that can be used to store the column address and row address of the currently detected bad cell F _t (step 48).

If, the entry is empty for the storage of the column address and row address of the bad cell (F _t) of the current detection does not exist, none, poor cell (F _t) of the current detection is determined to be unable to be restored (the 50 step).

However, a minor address an entry that the entry is empty for the storage of the column address and row address of the bad cell (F _t) of the current detecting when, consistent with a minor address of the bad cell (F _t) of the current detecting at least one presence In order to recover other bad cells (F _t-1 , F _t-2 , ...) that are not stored in the entry and the major address that matches the major address of the currently detected bad cell F _t is not stored in the entry. It is determined whether both redundant major and redundant minor are used (step 52). That is, the number of redundant cell array (s) available to date among the bad cells detected so far that have no corresponding minor or major address (hereinafter referred to as non-hit bad cells). Determine more.

If, when it satisfies the 52 phase that is, major to minor address is not stored in the entry matches the major address of a bad cell (F _t) of the current detecting matching minor address of the bad cell (F _t) of the current detection The redundancy majors and redundancy miners are both used to recover the other bad cells (F _t-1 , F _t-2 , ...) without the address stored in the entry, thus recovering the currently detected non-hit bad cells. If there is no redundant cell array to replace, it is determined that the currently detected bad cell F _t cannot be recovered (step 50). That is, if the number of non-hit bad cell (s) detected to date is greater than the number of available redundant cell arrays, it is determined that the memory containing the bad cells currently detected cannot be recovered. is not satisfied that is, is the minor address matching the minor address of the bad cell (F _t) of the current detection is stored in the entry, or major address that matches the major address of a bad cell (F _t) of the current detection is stored in the entry Or if there is a redundant major or redundant minor to be used to recover the currently detected bad cell F _t , the bad cell currently detected in an empty entry that does not store any column address and row address in the entry (s) The column address and the row address of (F _t ) are stored, and the flow proceeds to step 32 (step 54). That is, if the number of non-hit bad cells F _t detected so far is equal to or less than the number of available redundant cell arrays, the row and column addresses of the currently detected bad cells F _t are stored in an entry.

On the other hand, if it is determined in step 32 that the failure of all cells has been examined, and if the failure of all cells has been examined, it is not the defective cell (s) that have not yet been determined the redundant cell array to recover using which redundant cell array. Determine the redundant cell array (step 56).

The 56th step will be described in detail as follows. First, the minor addresses of the bad cell (s) that have not yet been determined which redundant cell array to recover are grouped together in a match. At this time, if there is one bundled combination, it is decided to recover the bad cell (s) belonging to the combination to an available redundancy miner. However, if there are several bundled combinations, the combination with the most bad cells among the multiple combinations is selected and the decision is made to recover the bad cell (s) belonging to the selected combination to a usable redundancy minor. Next, each of the bad cell (s) not yet allocated the redundant cell array is recovered to a redundant major. At this time, if there are bad cell (s) that are still not allocated the redundant cell array to be replaced, the bad cells are determined to be unrecoverable.

Hereinafter, referring to FIG. 4, a method of allocating a redundant cell array to be replaced to recover the bad cells shown in FIG. 2 using the built-in self-healing method for the embedded memory according to the present invention shown in FIG. 3 is described. Explain as follows. Here, it is assumed that the major is column, the minor is row, the redundant minus is one (M = 1), and the redundant major is two (N = 2).

4 is a view for explaining a built-in self-healing method for an embedded memory according to the present invention, which is composed of a memory 80, one redundant row 82, and two redundant columns 84 and 86. Referring to FIG.

The built-in self-healing method for the built-in memory according to the present invention is to allocate redundant cell arrays 82, 84, and 86 to the bad cells F0, F1, F2, F3, F4, and F5 shown in FIG. The four entries shown in Table 2 are used.

entry0 entry1 entry2 entry3 valid0 valid1 valid2 valid3 row0 must row1 must row2 must row3 must column0 must column1 must column2 must column3 must row0 address row1 address row2 address row3 address column0 address column1 address column2 address column3 address unrepairable

Referring to FIG. 4, the built-in self-healing method for the built-in memory according to the present invention first initializes four entries (entry0, entry1, entry2 and entry3) shown in Table 2 (step 30). After the thirtieth step, the cells are scanned from the lower left (row number: column number = 0: 0) to the upper right (15: F) direction of the memory 80 to determine whether or not the defects of all the cells have been checked. Step 32). If the defects for all the cells have not been checked, it is determined whether the defective cells have been detected (step 34). If the bad cell F0 is detected, it is determined whether a column address matching the detected column address of the bad cell F0 is stored in the entry (step 36). However, since no address is stored in the entry, the column of FOs is not hit. Therefore, it is determined whether a row address matching the row address of the FO is stored in the entry (step 40). Since the rows of the FO are also not hit, the process proceeds to step 44 where it is determined whether the row addresses matching the row address of the bad cell FO are stored in the entry, and whether the two matching row addresses are stored in the entry (step 44). ). At this time, since the row address corresponding to the row address of the FO is not stored in the entry, it is determined whether there is an empty entry for storing the row and column addresses of the FO (step 48). Since there is an empty entry, it is determined whether the FO is a non-hit bad cell and the number of non-hit bad cells detected so far including F0 is greater than 3 (step 52). However, since all redundant cells arrays 82, 84, and 86 have not been used, store the row and column addresses of the FO as row0 address and column0 address in Table 2 in the first entry (entry0), and proceed to step 32. Proceed (step 54).

In a thirty-second step, it is again determined whether the defects for all the cells have been examined. However, since the failure of the cell present in the right edge 15: F of the memory 80 shown in FIG. 4 has not yet been detected, it is determined that the failure for all cells has not been inspected. If a bad cell F1 is detected after F0, it is determined whether the column of F1 is a hit (step 36). Since the column of F1 has not been hit, it is determined whether the row of F1 is a hit and both redundant columns 84 and 86 have been used to recover F1 (step 40). Since the row of F1 is a hit but neither the redundant columns 84 and 86 are used, it is determined whether the row of F1 is a hit and F1 and the hit row are stored in the entry (step 44). The row of F1 is a hit, but since no two hit rows are stored, it is determined whether there is an entry for storing the column and row address of F1 (step 48). Since there is an entry for storing the column and row addresses of F1, it is determined whether the columns and rows of F1 are not hits and all redundant cell arrays 82, 84, and 86 have been used (step 52). That is, it is determined whether F1 is a non-hit bad cell and there are more non-hit bad cells detected up to now including F1 than an available redundant cell array. Since the column of F1 is not a hit and none of the redundant cell arrays 82, 84, and 86 are used, that is, F1 is not a non-hit bad cell and the number of currently available redundant cell arrays is greater than that of a non-hit bad cell. In many cases, the row address and column address of F1 are stored in the entry entry1 as row1 address and column1 address of Table 2, and the flow proceeds to step 32 (step 54).

By the same method, when the defective cell F2 is detected, it is judged whether the column of F2 is a hit and the redundant column 84 or 86 is available (step 36). Since the column of F2 is a hit, that is, the column address of F2 and the column address of F1 both coincide as '5' and the redundant columns 84 and 86 are available, use one of the redundant columns 84 and 86. To recover F2 (step 38). That is, in order to replace column 5 to which F1 and F2 belong to redundancy columns 84 or 86, column1 must of entry 1 of Table 2 is set to '1', and the flow proceeds to step 32.

If the bad cell F3 is detected while scanning the memory 80 by the same method, the column and row addresses of the bad cell F3 are stored in the entry 2 of Table 2, similar to the method of storing the column and row addresses of the bad cell F0. After storing as column2 address and row2 address in step 32 proceeds to,

Next, if a bad cell F4 is detected, it is determined whether the column of F4 is a hit and the redundant columns 84 and 86 are available (step 36). However, since the column of F4 is not a hit, it is determined whether the row of F4 is a hit and both redundant columns 84 and 86 are used (step 40). At this time, even if the row of F4 is a hit, one of the redundant columns 84 and 86 may still be used, so it is determined whether the row of F4 is a hit and F4 and the hit row are stored (step 44). ). Even if the row of F4 is a hit, since only one address of F3 exists in the address of the row hit with F4, it is determined whether there is an entry for storing the row and column addresses of F4 (step 48). Here, since there is an empty entry (entry3) for storing the row and column address of F4, it is determined whether the column and row of F4 are not hits and all redundant cell arrays 82, 84, and 86 are used. (Step 52). That is, F4 is a non-hit bad cell and determines whether the number of non-hit bad cell (s) detected to date is larger than the available redundant cell array. At this time, since the row of F4 is a hit and there are two redundant cell arrays available, the column address and row address of F4 are stored in the entry3 as column3 address and row3 address, and the process proceeds to step 32. Step 54).

Similarly, when testing the memory 80 and detecting a bad cell F5, it is determined whether the column of F5 is a hit and the redundant columns 84 and 86 are available (step 36). Since the column of F5 is a hit and the redundant column 84 or 86 is available, it is decided to use the redundant column 84 or 86 to recover the defective cells F0 and F5 and proceed to step 32. Step 38). At this time, column0 must becomes '1' in the entry (entry0) of Table 2.

After testing the memory 80 by the above-described method, if the end of checking whether the cells in the row 15 and the column F are bad or not is bad, that is, if all the cells of the memory 80 have been checked, the test still fails. Bad cells F3 and F4 located at each of the addresses stored in the entries entries2 and entry3 unrecovered are recovered using the redundant row 82 (step 56). That is, in the self-healing method for the internal memory according to the present invention, it is determined that F0 and F5 of the bad cells shown in FIG. 4 are recovered by the redundancy column 86 and F1 and F2 are the redundancy columns 84. ) And F3 and F4 are determined by redundancy row 82.

As a result, the embedded self-healing method for the internal memory according to the present invention determines that the bad cells belonging to the hit major address are first recovered by using the redundant major, and then the defective cells that have not been allocated the redundant cell array yet. You decide to use the redundancy miner later to recover. And if there are still bad cells that have not been allocated a redundant cell array, the existing bad cells are determined to be unrepairable.

In the self-healing method for the internal memory according to the present invention, when no hit occurs in a situation where there are three or fewer bad cells, all musts are '0', that is, either the redundancy column or the redundancy row is bad. It does not decide whether it will be used to recover the cell, but stores the row address and column address for each of the three bad cells in entries. At this time, all the information stored in the entries is read out to recover three defective cells by an external laser zapping program. In this case, the laser zapping program means that when three bad cells are addressed, the redundant cells are addressed instead of the bad cells. It cannot be recovered.

As a result, the built-in self-healing method for the internal memory according to the present invention detects bad cells in the memory, and if the major of the detected cells is a hit, the major must be unconditionally, that is, the bad cells hit by using a redundant redundancy major. If you decide to recover, and the minor is a hit, you must make the minor a must only if there are N + 1 hits. That is, it is decided to use one redundancy miner to recover bad cells belonging to N + 1 hit addresses. Thus, bad cells located in the same minor are all recovered using one redundant minus.

FIG. 5 is a block diagram of a built-in self-healing device for an embedded memory according to the present invention for performing the method shown in FIG. 3, which includes a hit signal generator 90, an entry register 92, and a recovery logic 94 It consists of.

The entry register 92 of the device shown in FIG. 5 is initialized in response to an initialization signal reset, and in response to a valid signal validi ', the row and column addresses row_add and col_add of the currently detected bad cell are responded to. Row and column must signals (ri_must and ci_must) that allow the use of valid signals (valid ') and row and column addresses (row_add' and col_add ') and redundant and redundant columns Save it. That is, in the entry register 92, steps 30 and 54 shown in FIG. 3 are performed. At this time, the data output from the entry register 92 through the output terminal OUT, that is, valid signals validi ', must signals ri_must and ci_must, and row and column addresses row_add' and col_add 'are used. The defective cells are recovered using the redundant cell arrays determined in steps 38, 42, 46, and 56 shown in FIG. For example, when the defective cell FO shown in FIG. 4 is addressed, the controller (not shown) causes the redundant cell array 86 to be addressed using data output through the output terminal OUT.

The hit signal generator 90 detects the row and column addresses (row_add and col_add) of the currently detected bad cell and stores the row and column addresses (row_add 'and col_add') previously stored in the entry register 92, respectively. The comparison result is output to the recovery logic unit 94 as row and column hit signals rih and cih.

On the other hand, the recovery logic unit 94, in response to the row and column hit signals rih and cih output from the hit signal generator 90, the valid signal validi 'and the row and column must signals ri_must'. And ci_must '), and outputs the generated valid signal valid' and the row and column must signals ri_must 'and ci_must' to the entry register 92, and a recovery state indicating whether or not a bad cell is recoverable. Outputs an unrepaiable signal. That is, in the recovery logic unit 94, steps 32 to 48 and step 52 shown in Fig. 3 are performed. The built-in self recovery method for the built-in memory according to the present invention shown in Fig. 3 includes a memory and an entry. It can be performed in a computer system that includes an entry that stores information about. For example, a computer system may correspond to a microcomputer, in which case the memory may be a cache.

As described above, the embedded self-recovery method and apparatus for the internal memory according to the present invention can be applied to the pattern of the bad cell (s) that exist even if the bad cell (s) of the memory exist on the memory in any pattern. Regardless, there is an effect that can recover all the Northern cell possible defective cell (s). That is, the recovery coverage capable of recovering the defective cells of the built-in self-healing method and apparatus for the built-in memory according to the present invention has an advantage of 100%.

Claims (4)

An embedded self-healing apparatus for recovering bad cell (s) present in a memory embedded in a microcomputer using at least one redundant row and a plurality of redundant columns or at least one redundant column and a plurality of redundant rows. , Initializes in response to an initialization signal and stores the row and column addresses of the currently detected bad cell in response to a valid signal, and stores the valid signal and the row and column addresses of the previously detected bad cell and the redundant row and the An entry register for storing row and column must signals that allow use of redundant columns; A hit signal generator for comparing row and column addresses of the currently detected bad cell with row and column addresses previously detected and stored in the entry register, and outputting the compared results as row and column hit signals; And In response to the row and column hit signals, generate the valid signal and the row and column must signals, output the generated valid signal and the row and column must signals to the entry register, and generate the bad cell. A recovery logic unit for outputting a recovery status signal indicating whether the recovery is possible; And recovering the defective cell by using the signals stored in the entry register. M (≥1) redundancy minor and N (N≥M≥1) redundancy majors to replace the defective cell (s) of the built-in memory in the microcomputer, and recover the bad cells of the embedded memory In the microcomputer performing the method, (a) If a plurality of bad cells (hereinafter, referred to as major hit bad cells) each having an address in the same major direction is detected, a plurality of the major hit bad cells are determined to be recovered using the available redundant major. Making; (b) if more than N bad cells (hereinafter referred to as minor hit bad cells) each having an address in the same minor direction are detected, the redundant redundancy minor available to use more than N minor hit bad cells; Determining to recover using; And (c) Defective cells that do not have the same major address or minor address (hereinafter referred to as non-hit bad cells) are detected as the sum of the number of usable redundancy major and the number of usable redundancy minor be when a microcomputer for performing a built-in self-repair method includes the step of determining that the recovery from the following use the redundancy available for the minor with the major wall as possible for using the non-heat first defective cell later. 5. The microcomputer according to claim 4, wherein the microcomputer has S (where S is twice as large as M and N) registers and performs a method for recovering a defective cell of the memory. (d) initializing the S entry registers and proceeding to step (a); (e) after the step (c), the entry register capable of storing the address of the non-hit bad cell or the N or less minor hit bad cells does not exist or the number of the non-hit bad cells is available. Determining that the memory cannot be recovered if it is greater than the sum of the major and major redundancy miners available; And (f) if the entry register capable of storing the address of the non-hit bad cell or the N or less minor hit bad cells exists, the address of the non-hit bad cell or the N or less minor hit bad cells is recalled. A microcomputer performing an embedded self recovery method comprising the steps of storing in an entry register. The method of claim 5, wherein the bad cell recovery method When there are P (N≥P≥2) detected defective cells each having the same minor direction address and there is no available redundancy major, use the redundant redundancy miner capable of using the detected P defective cells And determining to recover, wherein the microcomputer performs the embedded self-recovery method.