KR100325665B1 - Etchant for using for patterning the electrode of source/drain or gate - Google Patents

Abstract

The present invention relates to an etchant for etching a Group 6A metal film during fabrication of a gate or source / drain electrode. When the gate or source / drain electrode is a double film, the present invention relates to an etching solution for a lower metal film as a second metal film. By using (NH ₄ ) _x (NO ₃ ) _y (x, y> 0), HClO ₄ , CH ₃ COOH as an additive, it is possible to improve the etch ratio to the lower metal film and use it as the upper metal film. After etching the Al-Nd alloy film and the like to strip the photoresist to provide an etchant that can etch the lower metal film.

Description

ETCHANT FOR USING FOR PATTERNING THE ELECTRODE OF SOURCE / DRAIN OR GATE}

Industrial use field

The present invention relates to an etchant used to prepare a pattern of a gate or source / drain electrode, and more particularly, a double layer structure in which a gate line of a gate electrode of a thin film transistor (TFT) is a double layer. In the process of etching the double layer of the gate (Etching), it is possible to simplify the process using the etching solution according to the present invention, to selectively etch the lower double layer and to provide an etching solution with improved etching efficiency.

Conventional technology

In manufacturing a gate or source / drain electrode pattern used as a thin film transistor liquid crystal display element used as one of the flat panel display device, in the case of using a gate line or source / drain electrode as a double layer, Al-Nd alloy first The upper layer was etched using an etchant to etch the alloy, followed by a hard baking and ashing process, followed by etching the chromium metal layer used as an etch solution with a mask and then using a mask. The photoresist used was prepared by stripping.

In this process, Ce (NH ₄ ) ₂ (NO ₃ ) ₆ and nitric acid (HNO ₃ ) were used as etching liquids for the chromium metal film. In this case, Ce ³⁺ + NO was used due to the very high charge density of Ce. ₃ ^- → Ce (NO ₃₎ up the reaction, such as _n ^m- Ce (NO _{3) n,} because the presence (steric effect) due to the steric hindrance effect of the oxidizing power of ^m- Ce ³⁺ weakened problem that the etching efficiency is lowered There was this.

In addition, since nitric acid is more likely to react with Al than Cr, a problem arises in that, in the absence of a photoresist mask, only Al is etched and Cr is not etched. In order to prevent the photoresist lifting (lifting) between Al etching and Cr etching, a hard bake must be performed, and since the organic film is formed at the interface between Al and Cr, an ashing process is added to remove the process, which is complicated. Due to the reaction between the photoresist and the etchant, there was a problem that a chemical substance, that is, a foreign substance, remained on the metal surface.

In order to solve the above problems, the present invention is a process using an etchant consisting of Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0), HClO ₄ , CH ₃ COOH, H ₂ O To provide an etchant for Group 6A metals that can simplify the process, improve the etching efficiency and leave no foreign matter on the surface of the film after etching.

1 is a bar graph showing the etch ratios according to Examples 1, 2 and Comparative Examples for Cr films in Cr monolayers and Al-Nd / Cr bilayers.

2 is a SEM image of the surface after etching of the source / drain pattern film. The left side is the case using the etchant of the present invention and the right side is using the conventional etchant.

3 shows a profile of a Cr film after etching the source / drain pattern film.

4 is a layout plan view of a thin film transistor substrate.

5 is a cross-sectional view taken along the line V to V ′ of FIG. 4.

6 is a cross-sectional view of a pattern of gate or source / drain electrodes made in accordance with the present invention.

7A through 7F are cross-sectional views of a process of manufacturing a pattern of a gate or source / drain electrode according to an embodiment of the present invention.

8 to 10 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate.

The present invention is an etching solution of the Group 6A metal used as the lower layer to achieve the above object, Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) and HClO ₄ , additive Etch using CH ₃ COOH.

The etching solution is preferably used Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) 10 to 13% by weight, HClO ₄ 4 to 6% by weight, CH ₃ COOH 1 to 3% by weight Preferably Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) 11-13 wt%, HClO ₄ 4-5 wt%, CH ₃ COOH 1-2 wt%. Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) is preferably x = 2 and y = 6.

In addition, according to FIGS. 7A to 7F, the method for manufacturing a pattern of a gate or source / drain electrode including a double metal film formed by connecting an upper first metal film and a lower second metal film in contact with each other is described below.

a) laminating a double metal film on an insulating substrate;

b) applying a photoresist on the double metal film;

c) exposing the photoresist film through a mask;

d) developing the photoresist;

e) etching the first metal film with a first etching solution;

f) stripping the photoresist film;

g) A second metal film is used as the mask of the first metal film.

Etching using Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) and HClO ₄ , CH ₃ COOH as an additive

It provides a method of manufacturing a gate or source / drain electrode pattern comprising a.

Hereinafter, the present invention will be described in more detail.

The mixture of Ce (NH ₄ ) _x (NO ₃ ) _y and HClO ₄ , CH ₃ COOH used as an etchant for Group 6A metals has the following reaction mechanism:

Ce ⁴⁺ + e ^- → Ce ³⁺

_{^{ClO 4 - + 2H + + 2e}} - → ClO 3 - + H 2 O

_{^{2ClO 4 - + 18H + + 14e}} - → Cl 2 + 8H 2 O

_{^{ClO 4 - + 8H + + 8e}} - → Cl - + 4H 2 O

M → M ³⁺ + 3e ^-

The net reaction is shown below.

3Ce ⁴⁺ + M → 3Ce ³⁺ + M ³⁺ (where M is a Group 6A metal)

The etching solution of the above metals has a high reducibility of ClO ₄ ^- ions because ClO ₄ ^- is one of the weakest complex anions because ClO ₄ ^- ions in HClO ₄ solution are reduced and oxidize M. Since the oxidizing power to oxidize is large, the etch rate is increased.

In addition, nitric acid is more likely to react with Al, which is used as the upper layer, which is the first metal layer, than metal M, but since nitric acid is not used in the etching solution, the Al-Nd layer, which is the upper layer of the double layer, hardly oxidizes and only the lower metal layer. This oxidation takes place. Therefore, since only the lower metal film is selectively etched, the lower metal film can be etched after stripping the photoresist, so that foreign matters are rarely generated due to the reaction between the etchant and the photoresist.

In addition, CH ₃ COOH, which is an additive contained in the etchant, is adsorbed on a metal surface such as Al used as an upper layer, thereby passively acting on the Al-Nd alloy film surface to screen H ⁺ ions of HClO ₄ . This prevents oxidation of the Al-Nd film by H ⁺ ions, thus increasing the etching ratio.

Due to this effect, the hard baking and ashing processes of the manufacturing process may be omitted, and the etching process of the lower metal film may be performed after stripping the photoresist used as a mask. It is possible.

Hereinafter, a method of manufacturing the gate or source / drain electrode pattern will be described with reference to FIGS. 4 to 10.

FIG. 4 is a layout plan view of the thin film transistor substrate, and FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 4.

As shown in FIGS. 4 to 5, a gate pattern including a gate line 20 and a branched gate electrode 21 is formed on the substrate 10. The lower film 211 of the gate electrode 21 is made of a Group 6A metal and the upper film 212 is formed of an alloy film of Al / Nd. Although not shown in the drawing, the gate line 20 also includes a double film of a Group 6A metal film and an Al / Nd alloy film. A gate insulating layer 30 is formed on the gate patterns 20, 21, and 22, and a hydrogenated amorphous silicon (a-Si: H) layer 40 and a gate insulating layer 30 on the gate electrode 21. Hydrogenated amorphous silicon layers 51 and 52 that are heavily doped with n + impurities are formed on both sides of the gate electrode 21.

A data line 60 is also formed vertically on the gate insulating layer 30, and although not shown in the figure, a data pad 63 is formed at one end thereof to transmit an image signal from the outside. A drain electrode 62 is formed on the amorphous silicon layer 52 where one side of the source electrode 61, which is a branch of the data line 60, is doped. The data pattern including the data line 60, the source and drain electrodes 61 and 62, and the data pad 63 is made of a molybdenum-tungsten alloy film.

The passivation layer 70 is formed on the data patterns 60, 61, 62, and 63 and the amorphous silicon layer 50 not covered by the data pattern, and the drain electrode 62 is formed on the passivation layer 70. .

Finally, on the passivation layer 70, a pixel electrode 80 made of ITO is connected to the drain electrode 62 through a contact hole 71 not shown in the drawing.

Now, a method of manufacturing a thin film transistor substrate as shown in FIGS. 6 to 10 will be described. 6 to 10 are cross-sectional views and layout plan views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

As shown in FIGS. 7A to 7F, the lower layer (Group 6A metal) 211 and the upper layer (Al / Nd alloy) 212 are sequentially stacked on the transparent insulating substrate 10, and a photoresist is formed using a mask. (4) is developed and etched to form a gate pattern made of a double film including a gate line (not shown) and a gate electrode 21.

The gate pattern may be formed using a double film made of one material of aluminum or an aluminum alloy and one material of an alloy of a Group 6A metal or a Group 6A metal. Preferably, chromium is used as the lower film.

7A to 7F are cross-sectional views illustrating an etching process of upper and lower layers. First, a double metal film 211 and 212 is coated on a substrate (FIG. 7A), and a photoresist is applied on the applied double metal film 211 and 212. (4) is applied (FIG. 7B), and the photoresist is developed using a mask (FIG. 7C). The first metal film, i.e., the upper film 212, is etched using an etching solution (FIG. 7D), and the remaining photoresist 4 is stripped (FIG. 7E). The second metal film, that is, the lower film 211 is etched using Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0), HClO ₄ , and CH ₃ COOH, which is an etching solution of the present invention ( 7f).

In the conventional process, since the lower metal film 211 is etched and the photoresist 4 is stripped, foreign substances may be generated due to the reaction between the etching solution and the photoresist. Since the metal film is etched, there is no possibility of reacting with the etchant and the photoresist. Thus, as shown in the micrograph (SEM) of FIG. 2, the use of the etchant of the present invention significantly reduces the generation of foreign substances than when using the conventional etchant.

In addition, in the case of the etchant according to the present invention, the amount of residual chemicals decreases due to the chemical properties of the substances forming the etchant.

The etchant uses Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) 10-13 wt%, HClO ₄ 4-6 wt%, CH ₃ COOH 1-3 wt%, preferably Ce (NH ₄ ) ₂ (NO ₃ ) ₆ 11-13 wt%, HClO ₄ 4-5 wt%, CH ₃ COOH 1-2 wt% is used. Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) is preferably x = 2 and y = 6.

As shown in FIG. 8, after the gate insulating layer 30 made of silicon nitride, the hydrogenated amorphous silicon layer 40, and the hydrogenated amorphous silicon layer 50 doped with a high concentration of n-type impurities are sequentially stacked, The doped amorphous silicon layer 50 and the amorphous silicon layer 40 are developed and etched using the second mask.

As shown in FIG. 9, molybdenum is deposited on the doped amorphous silicon layer 50.

Alternatively, a metal film such as a molybdenum-tungsten alloy is laminated, and then wet-etched using a mask to form a data pattern including a data line (not shown), a source electrode 61, and a drain electrode 62.

The data pattern may be made of various conductive materials such as chromium and tantalum, and may be formed of a double layer in which chromium and molybdenum or molybdenum alloy are combined.

The exposed doped amorphous silicon layer 50 is then plasma dry etched using the source / drain electrodes 61 and 62 as a mask to separate the gate electrode 21 from both sides, while the positively doped amorphous silicon layer The amorphous silicon layer 40 between 51 and 52 is exposed.

Finally, as shown in FIG. 10, ITO is laminated and dry etched using a fourth mask to form a pixel electrode (not shown) connected to the drain electrode 62 through the contact hole 71. .

Hereinafter, preferred examples and comparative examples are presented to help understand the present invention. However, the following examples are only for the understanding of the present invention and the present invention is not limited to the following examples.

Example 1

12.0% by weight of Ce (NH ₄ ) ₂ (NO ₃ ) ₆ , 5.0% by weight of HClO ₄ , 1.0% by weight of CH ₃ COOH as an additive, and 82.0% by weight of distilled water were used as an etching solution of Cr.

Example 2

10.0% by weight of Ce (NH ₄ ) ₂ (NO ₃ ) ₆ , 5.0% by weight of HClO ₄ , 1.0% by weight of CH ₃ COOH as an additive, and 84.0% by weight of distilled water were used as an etchant.

Comparative Example 1

Ce (NH ₄ ) ₂ (NO ₃ ) ₆ 10.0% by weight, HNO ₃ 8.0% by weight, distilled water 92.0% by weight was used as an etchant.

The etching efficiency of the Cr single layer and the double layer consisting of the Cr film and the Al / Nd alloy film were evaluated as follows.

Etching ratio (Å / min) Target value (Å / min) Etch solution of Comparative Example Etching solution of Example 1 Etching solution of Example 2 Cr monolayer etch rate (at 1500 μs) 500-700 522 511 634 Cr etch rate (at 500µs) on Al-Nd / Cr bilayer S Cr / S Al = 1 200-700 43 226 276 S Cr / S Al = 8 500-700 444 604 701

( S Cr / S Al = 1, S Cr / S Al = 8 represents the expressed area ratio of the Cr film and the Al film.)

Evaluation of Etch Efficiency

The etching efficiency was evaluated for Cr monolayer and Al-Nd / Cr bilayer.

Evaluation conditions were carried out by dip etching at 33 ℃ using the etching solution prepared in Examples 1,2 and Comparative Example 1.

In the case of Cr single layer, the target etch rate was 500 to 700 Å / min, which is the same as that of the conventional etching solution.

In the case of the Al-Nd / Cr double layer, the exposed area ratios of Cr and Al-Nd films of the gate pattern substrate were different for each point, and the Cr etch ratio was greatly different according to the ratio.

As shown in Table 1 and FIG. 1, the evaluation result is that the etching ratio of the etching solution according to Comparative Example 1 and the etching ratio of the etching solution prepared according to Example 1 were almost the same in Example 1, but according to Example 2 In the case of the etchant, the etching rate was improved by about 21.3%. It can be seen that the etching ratio of the Cr monolayer increases as the amount of Ce (NH ₄ ) ₂ (NO ₃ ) ₆ increases.

In case of the Al-Nd / Cr double layer, the etching ratio of Example 1 was increased by about 428% and the example of Example 2 was increased by about 547% when the area ratio was 1 compared to the etching solution prepared by the comparative example. It was.

In addition, when the area ratio is 8, the etching ratio of the etching solution prepared in Example 1 was increased by 36% and 58% by the etching solution prepared in Example 1, compared to the etching solution prepared in Comparative Example. In the case of the double film, the increase in the etch ratio by the etchant according to Examples 1 and 2 was greater than that of the comparative example when the area ratio was 1, and the Cr film was larger than that of the Al alloy film. It can be seen that the selective etching with respect to. In other words, the larger the Cr area, the larger the etch rate.

In addition, according to the SEM analysis picture shown in FIG. 2, in the case of the etchant prepared according to Examples 1 and 2 according to the present invention, almost no residual chemicals are present on the surface of the source / drain pattern layer after etching (FIG. 2). Left photo), when using the conventional etchant prepared by the comparative example can be seen that a lot of residual chemicals remain (picture on the right in Figure 2) when using the etchant prepared according to the present invention the source / It is judged that the electrical properties of the drain pattern film are excellent.

3 is a view illustrating a profile of a Cr film after etching a source / drain pattern layer with an etchant according to the present invention, showing that the left profile according to the embodiment of the present invention is the same as the existing one (the right profile). Confirmed.

When the etchant according to the present invention is used, the Cr film can be selectively etched, and since there is almost no residual chemical component after etching, the Cr film can be etched immediately after the Al alloy film is etched and the photoresist is stripped. Therefore, the conventional hard bake process and ashing process can be omitted, and the process can be simplified, and the etching rate is improved from about 40% to 550% in the case of the double layer than the conventional etching solution, so that the mass production can be sufficiently applied in the actual process.

Claims (4)

(Correction) A Group 6A metal etchant comprising Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0), HClO ₄ , CH ₃ COOH, H ₂ O. (Correction) The method according to claim 1, Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) is 10-13 wt%, HClO ₄ is 4-6 wt% and CH ₃ COOH is 1-3 wt% Family metal etchant. (Correction) The method according to claim 1, Ce (NH ₄ ) _x (NO ₃ ) _y (x> 0, y> 0) is a Group 6A metal etchant with x = 2 and y = 6. The method according to any one of claims 1 to 3, Group 6A metal is a metal etchant.