KR100324819B1 - Refresh device of a semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refreshing device of a semiconductor memory device capable of variably adjusting the refresh interval. When performing refreshing on a semiconductor memory device such as a DRAM, a burst refresh is performed using a mode register to increase efficiency in terms of design. The refresh can be changed from the user's point of view or during use. In addition, the time for controlling the refresh interval in the system can be adjusted by 2 to 4 times longer, and the number of refreshes within the adjusted refresh interval can also be adjusted to increase the efficiency of the design.

Description

Refresh device of a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh device for a semiconductor memory device, and more particularly, to a refresh device for a semiconductor memory device that refreshes periodically to preserve cell data, such as a DRAM.

In general, unlike a SRAM, a semiconductor memory device, such as a DRAM, needs to be refreshed periodically to preserve data stored in a cell.

Conventionally, when a constant refresh cycle and interval are determined externally, the refresh operation is performed according to the determined matter.

FIG. 1 is a conventional refresh block diagram, in which a command bar 10 receives a ras bar signal RASb, a cas bar signal CASb, a chip select bar signal CSb, and a write enable bar signal WEb. To generate a refresh signal.

The system timer 12 determines a refresh interval for the cell data (for example, 15.6 ms; see FIG. 3), and the refresh request generator 14 refreshes the refresh signal from the command decoder 10 and the system. A time from the timer 12 is input to generate a refresh request signal.

The output unit 16 receives the refresh request signal request and outputs a refresh performing pulse signal new_request every 15.6 ms when the refresh signal requires the enable state at a high level. Accordingly, the corresponding system performs refresh according to the pulse signal new_request. Reference numeral 18 is a refresh performing pulse signal generator.

Here, the refresh request generator 14 is implemented with delay logic and end logic of a plurality of inverters connected in series as illustrated in FIG.

As described above, according to the conventional configuration, the refresh is performed once according to the time (15.6 ms) determined by the system.

Such refreshes are determined by refresh cycles and intervals determined externally, and the refresh characteristics are determined by changing design circuits or adjusting options.

However, this method is disadvantageous in terms of design efficiency and has to be performed in the system when the refresh characteristic is to be changed from the user's point of view. In addition, in terms of system design, there is a disadvantage in that the time that can be controlled in the conventional refresh method is fixed at a constant T1 (see FIG. 3).

Accordingly, the present invention has been made in view of the above-described conventional circumstances, and an object of the present invention is to provide a refreshing device of a semiconductor memory device capable of variably adjusting the refresh interval.

In order to achieve the above object, a refreshing apparatus for a semiconductor memory device according to a preferred embodiment of the present invention includes a command decoder for generating a refresh signal and a mode register set signal by combining control signals input from the outside;

A mode register for selecting one of a plurality of burst refresh length signals by combining the mode register set signal and an address signal from an outside;

Refresh interval generating means for generating mutually different clock signals;

And a refresh pulse signal generating means for determining a clock signal corresponding to the selected burst refresh length signal at refresh intervals and generating a refresh pulse signal at each of the determined refresh intervals.

1 is a conventional refresh block diagram;

2 is a circuit diagram of a conventional refresh request generator;

3 is a conventional refresh timing diagram;

4 is a block diagram of a refresh apparatus according to an embodiment of the present invention;

5 is a circuit diagram of a mode register according to an embodiment of the present invention;

6 is a circuit diagram of a refresh request generator according to an embodiment of the present invention;

7 is a refresh timing diagram when the burst refresh length is 1 in the embodiment of the present invention;

8 is a refresh timing diagram when the burst refresh length is 2 in the embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 20: command decoder 12, 22: system timer

14, 26: refresh request generator 16, 28: output unit

18, 50: refresh pulse signal generator 23, 24: counter

30: mode register 40: refresh interval generating means

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the refresh apparatus according to the embodiment of the present invention, as shown in FIG. 4, a refresh signal and a mode register set signal mregset are combined by combining control signals RASb, CASb, WEb, and CSb input from the outside. A command decoder 20 for generating a signal and selecting one of a plurality of burst refresh length signals BRL 1,2 and 4 by combining the mode register set signal mregset and a predetermined bit of address signals Address_1 and Address_b. Refresh interval generating means 40 for generating different clock signals, that is, signals for refresh intervals 15.6 ms, 31.2 ms, 62.4 ms, using the mode register 30, the system timer 22, and the counters 23, 24; And a refresh pulse signal for determining a clock signal corresponding to the selected burst refresh length signal (one of BRL 1,2,4) at a refresh interval and generating a refresh pulse signal (new_request) at each of the determined refresh intervals. It includes a production means (50).

Here, the mode register 30 is a decoder 32 for receiving and decoding the mode register set signal mregset and external address signals Address_a and Address_b as shown in FIG. 5, and the decoder 32. And an output signal (Address_az, Address_ad, Address_bz, Address_bd) in combination with each other, and a selector 34 for designating any one of the different burst refresh length signals BRL1, 2, and 4.

The decoder 32 receives the mode register set signal mregset and the address signal Address_a from the outside and outputs a signal Address_az and a delayed signal Address_ad that are in phase opposite to the address signal Address_a. The logic registers ND1 and IV1 and the mode register set signal mregset and an external address signal Address_b are received, and a signal (Address_bz) and a delayed signal Address_bd that are in phase opposite to the address signal Address_b are output. It consists of AND logics ND2 and IV2.

The selector 34 performs an AND processing on the signals Address_az and Address_bz to end-process the AND logics ND3 and IV3 for selecting a burst refresh length signal BRL1 and an processing of the signals Address_ad and Address_bz to burst burst length. AND logics ND4 and IV4 for selecting the signal BRL2, AND logics ND5 and IV5 for selecting the burst refresh length signal BRL2 by AND processing the signals Address_az and Address_bd, and the signals Address_ad, And AND logics ND6 and IV6 for AND processing Address_bd to select the burst refresh length signal BRL4.

The mode register 30 having the above configuration has a burst refresh length signal by a combination of two address signals Address_a and b which are not used for the mode register setting operation in a state where the mode register set signal mregset is input at a high level. Select (BRL1, 2, 4).

That is, when both of the address signals Address_a and b are at the low level, the burst refresh length signal BRL1 is selected. If the address signal Address_a is at the low level and the address signal Address_b is at the high level, the burst refresh length signal BRL2 is selected. Selects the burst refresh length signal BRL2 when the address signal Address_a is at a high level and the address signal Address_b is at a low level, and selects the burst refresh length signal when both of the address signals Address_a and b are at a high level. BRL4).

The refresh pulse signal generating unit 50 receives signals from the command decoder 20, the mode register 30, and the refresh interval generating unit 40, respectively, and has different refresh request signals request1, request2, and request4. A refresh request generator 26 for generating a signal, and outputs different refresh pulse signals new_request1, new_request2 and new_request4 by receiving the different refresh request signals request1, request2 and request4 and the refresh signal refresh. The part 28 is provided.

The refresh request generator 26 has output signals BRL1, BRL2, BRL4 of the mode register 30 and clock signals 15.6 ms, 31.2 ms from the refresh interval generating means 40, as shown in FIG. , A plurality of first decoders 60, 62, 64 for receiving and decoding 62.4 kHz, respectively, and output signals of the first decoders 60, 62, 64, the refresh signal, and the respective decoders. And a plurality of second decoders 66, 68, and 70 for receiving and decoding a signal obtained by delaying the output signals of the first decoders 60, 62, and 64 through the inverters IV9, IV10, and IV11.

The first decoder 60 receives a signal obtained by inverting the clock signal 15.6 ㎲ from the refresh interval generating means 40 through the inverter IV7 and the output signal BRL1 of the mode register 30. And a NAND gate ND7 for NAND processing, and an inverter IV8 for inverting an output signal of the NAND gate ND7. The other first decoders 62 and 64 also have the same configuration as the first decoder 60. The second decoders 66, 68, and 70 are composed of AND logics ND8 and IV12 to output different refresh request signals request1, request2, and request4.

The refresh pulse signal new_request1a output from the output unit 28 maintains the same refresh interval (15.6 ms) as that of the conventional refresh pulse signal new_request, and the refresh pulse signals new_request2a and new_request2b are output from the output unit 28. ), Two refreshes are performed during the refresh interval of 31.2 μs. Perform one refresh.

Referring to the operation of the refresh device of the semiconductor memory device according to the embodiment of the present invention configured as described above are as follows.

The command decoder 20 receives a ras bar signal RASb, a cas bar signal CASb, a chip select bar signal CSb, and a write enable bar signal WEb and receives a mode register set signal mregset. 30, and the mode register 30 selects a burst refresh length signal (i.e., one of BRL1, BRL2, and BRL4) and sends it to the refresh request controller 26.

The refresh request generator 26 selects refresh intervals (15.6 ms, 312. Ms, 624. Ms) from the refresh interval generating means 40 according to the burst refresh length signal selectively input. For example, 15.6 ms is selected for BRL1, 31.2 ms is selected for BRL2, and 62.4 ms is selected for BRL4. The refresh request generator 26 generates a refresh request signal (one of request1, request2, and request4) according to the selected refresh interval.

Accordingly, the output unit 28 performs a NAND process of the refresh request signal (request1, request2, or request4) and the high level refresh signal (refresh) when the current refresh is in progress, and outputs a corresponding refresh pulse signal (new_request). Done.

For example, in the burst refresh length BRL1, as shown in the timing diagram of FIG. 7, the refresh pulse signal new_request1a is generated once every 15.6 ms to activate the word line to refresh the memory cell of the activated word line acid.

In the burst refresh length BRL2, as shown in the timing diagram of FIG. 8, the refresh pulse signal new_requst2 is generated once every 31.2 ms to activate the word line. The refresh pulse signal new_request2a is generated first, and the 'tRC' degree is generated. The refresh pulse signal new_request2b is enabled with a delay of to perform the refresh.

In the burst refresh length BRL4, the refresh pulse signal new_request4 is enabled every 62.4 ms. The refresh pulse signal new_request4a is enabled first, and the refresh pulse signal continuously has a delay of about tRC. , new_request4c and new_request4d are sequentially enabled to refresh.

According to the present invention as described above, by using a mode register that can select the burst refresh when performing refresh in a semiconductor memory device such as DRAM, the efficiency is improved in terms of design, and from the user's point of view or during the initial use You can change the refresh.

In addition, the time for controlling the refresh interval in the system can be adjusted by 2 to 4 times longer, and the number of refreshes within the adjusted refresh interval can also be adjusted to increase the efficiency of the design.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (6)

In a semiconductor memory device which periodically refreshes, A command decoder for generating a refresh signal and a mode register set signal by combining control signals input from the outside; Refresh interval generating means for generating a plurality of clock signals different from each other; A mode register enabled by the mode register set signal to receive and combine address signals from the outside, thereby generating a burst refresh length signal specifying one of the plurality of clock signals; And And a refresh pulse signal generating means for selecting one of the plurality of clock signals corresponding to the burst refresh length signal and generating a refresh pulse signal using the selected clock signal and the refresh signal. Device refresh device. The method of claim 1, wherein the mode register is A decoder for decoding the mode register set signal and the external address signal; And a selector for combining the output signals of the decoder to output the burst refresh length signal capable of designating one of the plurality of clock signals. The method of claim 2, And the decoder comprises a plurality of AND logics. The method of claim 2, And wherein the selector comprises a plurality of end logics. The method of claim 1, wherein the refresh pulse signal generating means A refresh request generator which receives signals from the command decoder, the mode register, and the refresh interval generating means and generates different refresh request signals; And an output unit configured to receive the different refresh request signals and the refresh signals, and output different refresh pulse signals. 6. The refresh request generator of claim 5 wherein A first decoder for receiving and decoding signals from the mode register and the refresh interval generating means; And a second decoder configured to receive and decode the output signal of the first decoder, the refresh signal, and a signal delayed from the output signal of the first decoder.