KR100321707B1 - method for fabricating gate electrode in semiconductor device - Google Patents
method for fabricating gate electrode in semiconductor device Download PDFInfo
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- KR100321707B1 KR100321707B1 KR1019980024722A KR19980024722A KR100321707B1 KR 100321707 B1 KR100321707 B1 KR 100321707B1 KR 1019980024722 A KR1019980024722 A KR 1019980024722A KR 19980024722 A KR19980024722 A KR 19980024722A KR 100321707 B1 KR100321707 B1 KR 100321707B1
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 32
- 239000010937 tungsten Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012790 adhesive layer Substances 0.000 claims abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000006866 deterioration Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 10
- 230000008021 deposition Effects 0.000 abstract description 9
- 238000010405 reoxidation reaction Methods 0.000 abstract description 5
- 230000006911 nucleation Effects 0.000 abstract description 3
- 238000010899 nucleation Methods 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 57
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- -1 sputtering Chemical compound 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
본 발명은 CVD에 의한 텅스텐(W)으로 게이트전극을 형성하는 방법을 제공하고자 하는 것으로, 반도체기판 상에 게이트절연막을 형성하는 단계; 게이트전극이 형성될 영역의 상기 게이트산화막 상에 희생막패턴을 형성하는 단계; 층간절연막을 형성하고 상기 희생막패턴의 표면이 노출되어 기판이 평탄화되도록 상기 층간절연막을 식각하는 단계; 상기 노출된 희생막패턴을 식각하여 요부를 형성하는 단계; 기판 전면에 접착층으로서 물리적증착법으로 텅스텐막(PVD-W)을 형성하는 단계; 및 화학기상증착법으로 상기 요부내에 매립된 텅스텐(CVD-W)을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하며, 이에 의해 본 발명은 첫째로 텅스텐 증착 전에 재산화공정을 실시하므로써 텅스텐 전극의 산화로 인한 게이트전극의 패턴 불량을 방지할 수 있으며, 둘째로 PVD-W을 CVD-W의 접착층 및 핵생성 층으로 사용하므로써 게이트절연막과 텅스텐이 직접 접촉한 게이트전극 구조를 형성하는 것이 가능하여 고속동작을 낼 수 있으며, 셋째, 스텝커버리지와 매립특성이 우수한 CVD-W을 사용하여 안정한 게이트전극 패턴을 형성할 수 있다.The present invention provides a method of forming a gate electrode from tungsten (W) by CVD, comprising the steps of: forming a gate insulating film on a semiconductor substrate; Forming a sacrificial layer pattern on the gate oxide layer in a region where a gate electrode is to be formed; Forming an interlayer dielectric layer and etching the interlayer dielectric layer to expose the surface of the sacrificial layer pattern to planarize the substrate; Etching the exposed sacrificial layer pattern to form recesses; Forming a tungsten film (PVD-W) by physical vapor deposition as an adhesive layer on the entire surface of the substrate; And forming tungsten (CVD-W) embedded in the recess by chemical vapor deposition, whereby the present invention firstly performs oxidation of the tungsten electrode by performing a reoxidation process prior to tungsten deposition. It is possible to prevent the pattern defect of the gate electrode caused by this. Second, by using PVD-W as an adhesive layer and a nucleation layer of CVD-W, it is possible to form a gate electrode structure in which the gate insulating film and tungsten are in direct contact with each other. Third, a stable gate electrode pattern can be formed using CVD-W having excellent step coverage and buried characteristics.
Description
본 발명은 1 기가비트(giga bit)급 이상의 디램(DRAM)과 같은 고집적과 고속도를 요구하는 반도체소자에서의 게이트전극(워드라인) 형성방법에 관한 것이다.The present invention relates to a method of forming a gate electrode (word line) in a semiconductor device that requires high integration and high speed, such as DRAM of 1 gigabit or more.
현재까지 반도체소자의 게이트전극은 도핑된 폴리실리콘을 사용하거나 전극의 비저항을 낮추기 위하여 폴리실리콘 상에 텅스텐실리사이드(WSix)를 적층하여 사용하고 있다. 그러나 텅스텐실리사이드 박막의 비저항은 약 100μΩ-㎝으로 여전히 큰 비저항을 나타내고 있어 1Gb DRAM 이상 소자의 가는 선폭에서 고속으로 동작하는 소자를 얻기 위해서는 게이트전극의 저항을 더욱 감소시켜야 한다. 따라서 비저항이 약 10μΩ-㎝인 텅스텐(W)으로 워드라인을 형성하려는 연구가 꾸준히 진행되고 있다.Until now, a gate electrode of a semiconductor device has been used by stacking tungsten silicide (WSix) on polysilicon in order to use doped polysilicon or to lower specific resistance of the electrode. However, the specific resistance of the tungsten silicide thin film is still about 100 μΩ-cm, and thus the resistivity of the gate electrode must be further reduced in order to obtain a device that operates at high speed at a thin line width of a device larger than 1Gb DRAM. Therefore, studies are being made to form word lines with tungsten (W) having a specific resistance of about 10 μΩ-cm.
그러나 텅스텐을 사용하여 게이트전극을 형성할 경우 다음과 같은 근본적인 문제를 안고 있다. 즉, 게이트산화막(gate oxide)위에 텅스텐 또는 텅스텐 및 폴리실리콘을 증착한 후, 게이트 마스크를 이용하여 식각할 때 게이트산화막의 열화가 발생하기 때문에 이것을 보상하기 위해 그리고 이후의 LDD 이온주입시 기판을 보호하기 위해 재산화(Re-oxidation) 공정을 실시하는데, 이때, 텅스텐이 산화되어 부도체를 형성하고 패턴된 게이트(워드라인)의 모양을 파괴하는 문제가 있다.However, when forming the gate electrode using tungsten has the following fundamental problems. In other words, after deposition of tungsten or tungsten and polysilicon on the gate oxide, the gate oxide film is deteriorated when etching using the gate mask to compensate for this and to protect the substrate during subsequent LDD ion implantation. In order to perform a re-oxidation process, there is a problem in that tungsten is oxidized to form an insulator and destroy the shape of a patterned gate (word line).
그밖에 텅스텐과 산화층과의 계면 안정성이 열악하기 때문에 텅스텐 게이트전극을 사용하기 위해서는 게이트산화막과 텅스텐 사이에 별도의 접착층(glue layer)를 사용하여야 하는데, 이로 인해 텅스텐 단일 전극 구조에 비하여 워드라인 저항이 상승하는 효과가 발생한다.In addition, since the interfacial stability between tungsten and the oxide layer is poor, a separate adhesive layer must be used between the gate oxide film and tungsten in order to use the tungsten gate electrode, which increases the word line resistance compared to the tungsten single electrode structure. Effect occurs.
또한 화학기상증착(CVD) 공정으로 텅스텐을 사용할 경우 증착 소스(WF_6)에 포함된 불소가 게이트산화막을 손상시킬 우려가 있다.In addition, when tungsten is used in the chemical vapor deposition (CVD) process, fluorine contained in the deposition source WF_6 may damage the gate oxide layer.
본 발명은 상기 종래기술의 문제점을 해결하면서 CVD에 의한 텅스텐(이하 "CVD-W"으로 표기한다)을 게이트전극으로 형성하는 방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming tungsten (hereinafter referred to as "CVD-W") by CVD as a gate electrode while solving the problems of the prior art.
도1 내지 도8은 본 발명의 일실시예에 따른 반도체소자 제조 공정도.1 to 8 are semiconductor device manufacturing process diagrams in accordance with one embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 소자분리막1: semiconductor substrate 2: device isolation film
3 : 게이트산화막 4 : 폴리실리콘막3: gate oxide film 4: polysilicon film
5 : 열산화막 6 : 스페이서절연막5: thermal oxide film 6: spacer insulating film
7 : 제1층간절연막 8 : PVD-W7: first interlayer insulating film 8: PVD-W
9 : CVD-W 10 : 제2층간절연막9: CVD-W 10: second interlayer insulating film
11 : 요부11: main part
본 발명에서는 상기 목적을 달성하기 위하여, 다음과 같은 기술적 구성을 갖는다.In the present invention, in order to achieve the above object, it has the following technical configuration.
먼저 반도체기판 상에 게이트절연막을 형성한 다음, 게이트절연막 위에 소정 두께의 희생막을 증착하고 게이트 마스크를 사용하여 상기 희생막을 패터닝한 후, 재산화공정을 실시한다. 희생막은 산화막 및 질화막 등의 절연막과 게이트절연막에 대해 식각선택비를 갖는 물질을 사용한다. 이어서, 희생막패턴 측벽에 스페이서절연막을 형성한 다음, 기판 전면에 층간절연막을 증착하고 희생막패턴의 표면이 노출되도록 층간절연막을 에치백(etchback) 또는 CMP(chemical mechanical polishing)를 이용하여 식각한다. 이후 희생막을 제거하면 이 제거된 자리에 요부를 형성된다. 요부 바닥은 게이트절연막이 될 것이다. 이후 스퍼터링과 같은 물리적인증착법(PVD)에 의해 텅스텐(이하 "PVD-W"으로 표기한다)을 소정 두께 증착하는데, 이 PVD-W은 CVD-W과 층간절연막 또는 게이트절연막 사이에서 접착층 역할을 하고, 또한 CVD-W의 핵생성 층으로서의 역할을 한다. 이후 CVD-W으로 요부를 충분히 매립할 정도 이상의 두께를 증착한다. 이후 CVD-W의 에치백(etchback)또는 CMP공정을 실시하여 요부 내에만 CVD-W이 매립되도록 한다.First, a gate insulating film is formed on a semiconductor substrate, a sacrificial film having a predetermined thickness is deposited on the gate insulating film, and the sacrificial film is patterned by using a gate mask, followed by a reoxidation process. As the sacrificial film, a material having an etch selectivity with respect to an insulating film such as an oxide film and a nitride film and a gate insulating film is used. Subsequently, a spacer insulating film is formed on the sidewalls of the sacrificial film pattern, and then an interlayer insulating film is deposited on the entire surface of the substrate, and the interlayer insulating film is etched using etchback or chemical mechanical polishing (CMP) to expose the surface of the sacrificial film pattern. . The sacrificial film is then removed to form recesses in the removed areas. The bottom of the recess will be a gate insulating film. Thereafter, tungsten (hereinafter referred to as " PVD-W ") is deposited by physical certified deposition (PVD) such as sputtering, which acts as an adhesive layer between the CVD-W and the interlayer or gate insulating film. It also serves as the nucleation layer of CVD-W. CVD-W is then deposited to a thickness sufficient to bury the recess sufficiently. Thereafter, the CVD-W is etched back or the CMP process is performed so that the CVD-W is embedded only in the recess.
이상과 같은 본 발명을 사용하면, 첫째로 텅스텐 증착 전에 재산화공정을 실시하므로써 텅스텐 전극의 산화로 인한 게이트전극의 패턴 불량을 방지할 수 있으며, 둘째로 PVD-W을 CVD-W의 접착층 및 핵생성 층으로 사용하므로써 게이트절연막과 텅스텐이 직접 접촉한 게이트전극 구조를 형성하는 것이 가능하여 고속동작을 낼 수 있으며, 셋째, 스텝커버리지와 매립특성이 우수한 CVD-W을 사용하여 안정한 게이트전극 패턴을 형성할 수 있다. 또한 PVD-W층은 CVD-W증착시 발생가능한 WF_6의 불소 침투로 인한 게이트절연막 및 하지층의 손상을 방지하는 베리어로서의 역할도 하게 된다.By using the present invention as described above, first, by performing the reoxidation process before tungsten deposition, it is possible to prevent the pattern defect of the gate electrode due to the oxidation of the tungsten electrode, and secondly, PVD-W is bonded to the CVD-W adhesive layer and nucleus. By using it as a production layer, it is possible to form a gate electrode structure in which the gate insulating film and tungsten are in direct contact with each other, thereby achieving high speed operation. Third, forming a stable gate electrode pattern using CVD-W having excellent step coverage and buried characteristics. can do. In addition, the PVD-W layer serves as a barrier to prevent damage to the gate insulating layer and the underlying layer due to fluorine infiltration of WF_6 that may occur during CVD-W deposition.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도1 내지 도8은 본 발명의 일실시예에 따른 반도체소자 제조공정을 도시하고 있다.1 to 8 illustrate a semiconductor device manufacturing process according to an embodiment of the present invention.
먼저, 도1에서와 같이 실리콘기판(1)에 트렌치 소자분리(STI ; shallow trench isolation) 공정으로 소자분리막(2)을 형성하고 게이트산화막(3)을 성장시킨다. 그리고 희생막으로서 300∼5000Å 두께의 폴리실리콘막(4)을 증착한 후 게이트(워드라인) 마스크를 이용하여 폴리실리콘막을 패터닝한다.First, as shown in FIG. 1, an isolation layer 2 is formed on a silicon substrate 1 by a shallow trench isolation (STI) process, and a gate oxide layer 3 is grown. After the deposition of the polysilicon film 4 having a thickness of 300 to 5000 희생 as a sacrificial film, the polysilicon film is patterned using a gate (word line) mask.
이후, 도2와 같이 재산화 공정으로 열산화막(5)을 형성하여 폴리실리콘막의 식각시 발생한 게이트산화막의 열화를 회복시킨다. 그리고 기판 전면에 500∼3000Å 두께의 절연막(예컨대 실리콘질화막)을 증착하고 다시 비등방성 전면식각하여 폴리실리콘막(4) 패턴 측벽에 스페이서절연막(6)를 형성시킨다.Thereafter, as shown in FIG. 2, the thermal oxide film 5 is formed by the reoxidation process to recover the degradation of the gate oxide film generated during the etching of the polysilicon film. An insulating film (for example, a silicon nitride film) having a thickness of 500 to 3000 Å is deposited on the entire surface of the substrate, and then anisotropically etched to form a spacer insulating film 6 on the sidewalls of the polysilicon film 4 pattern.
이후 도3과 같이 1000∼5000Å 두께의 제1층간절연막(7)을 증착하고, 도4와 같이 상기 폴리실리콘막(4) 패턴의 표면이 노출될때까지 에치백(etchback) 또는 CMP(chemical mechanical polishing)을 이용하여 제1층간절연막(7)을 식각한다. 제1층간절연막(7)은 300∼2000Å 두께의 실리콘질화막과 잔류두께의 실리콘산화막이 차례로 적층된 이중 절연막을 사용할 수 있다. 제1층간절연막의 에치백은 C_x F_Y 와~~ O_2를 사용하여 5mTorr∼100Torr, 100W∼10KW의 조건에서 진행한다.Thereafter, as shown in FIG. 3, a first interlayer insulating film 7 having a thickness of 1000 to 5000 Å is deposited, and an etchback or chemical mechanical polishing is performed until the surface of the polysilicon film 4 pattern is exposed as shown in FIG. 4. Is used to etch the first interlayer insulating film 7. As the first interlayer insulating film 7, a double insulating film in which a silicon nitride film having a thickness of 300 to 2000 과 and a silicon oxide film having a residual thickness are sequentially stacked may be used. The etch back of the first interlayer insulating film is carried out under conditions of 5 mTorr to 100 Torr and 100 W to 10 KW using C_x F_Y and ~~ O_2.
이어서, 도5와 같이 반응성이온식각에 의한 건식식각 또는 실리콘 에천트에 의한 습식식각을 사용하여 표면이 드러난 부분부터 폴리실리콘막(4) 식각을 실시하여 요부(11)를 형성하여 요부 바닥의 게이트산화막(3)이 드러나게 한다. 이때, 도면에 도시된 바와 같이 열산화막(5)은 함께 제거될 수도 있고, 또는 잔류 할 수도 있다.Subsequently, as shown in FIG. 5, the polysilicon film 4 is etched from the exposed portion using dry etching by reactive ion etching or wet etching by silicon etchant to form recesses 11 to form gates at the bottom of the recesses. The oxide film 3 is exposed. At this time, as shown in the figure, the thermal oxide film 5 may be removed together or may remain.
이후 도6과 같이 기판 전면에 CVD-W의 접착층 및 핵생성층으로서 PVD-W(8)을 50∼2000Å 두께로 증착하고, 계속하여 WF_6와 SiH_4가스 또는 WF_6와 H_2가스를 사용하여 요부(11)가 완전히 매립될 정도의 두께로 CVD-W(9)을 증착한다.Thereafter, as shown in FIG. 6, the PVD-W 8 is deposited to a thickness of 50 to 2000 μs as an adhesive layer and a nucleation layer of the CVD-W, and then the main portion 11 is formed using WF_6 and SiH_4 gas or WF_6 and H_2 gas. CVD-W 9 is deposited to a thickness such that) is completely embedded.
이후 도7과 같이 요부(11) 내부만을 CVD-W(9)이 매립하도록 에치백(etchback) 또는 CMP 공정을 실시한다. 에치백은 SF_6 가스를 사용한다.Thereafter, as shown in FIG. 7, an etchback or CMP process is performed so that the CVD-W 9 is embedded only in the recess 11. The etch back uses SF_6 gas.
끝으로 도8과 같이, 제2층간절연막(10)를 증착하여 텅스텐 게이트전극(워드라인)의 형성을 마친다. 제2층간절연막은 SiH_4또는 TEOS를 원료로 사용하여 플라즈마화학기상증착(RECVD : plasma enhanced chemical vapor deposition)방법으로 증착하며, 이때 증착 온도는 200∼600℃로 한다. 또한 제2층간절연막은 TEOS와 오존(O3)을 원료로 사용하여 화학기상증착 방법으로 형성할 수 있으며 이때 증착온도는 20∼600℃이다. 더욱이 제2층간절연막은 300∼1000Å의 실리콘질화막과 실리콘산화막이 적층된 이중절연막을 사용할 수 있다.Finally, as shown in FIG. 8, the tungsten gate electrode (word line) is formed by depositing the second interlayer insulating film 10. The second interlayer insulating film is deposited by using a plasma enhanced chemical vapor deposition (RECVD) method using SiH_4 or TEOS as a raw material, and the deposition temperature is 200 to 600 ° C. In addition, the second interlayer insulating film may be formed by chemical vapor deposition using TEOS and ozone (O3) as raw materials, and the deposition temperature is 20 to 600 ° C. Further, as the second interlayer insulating film, a double insulating film in which a silicon nitride film and a silicon oxide film of 300 to 1000 GPa is laminated can be used.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 CVD-W을 게이트전극(워드라인)으로 적용 가능하게 하는 기술로서, 종래의 공정으로는 기술적인 문제점으로 남아 있던 재산화시의 문제를 해결하였으며, 텅스텐과 게이트산화막과의 계면 안정성을 향상시키고, 또한 불소 침투로 인한 게이트산화막과 하지층의 손상 등을 해결할수 있다. 경제적인 관점에서는 기존의 폴리실리콘이나 실리사이드 계통의 전극재료보다 전기전도도가 훨씬 우수한 텅스텐(W)으로 게이트전극을 형성함으로써 반도체소자의 신호전달 속도를 극대화하여 부가가치를 높일수 있으며 본 기술을 이용하여 고속소자 시장의 선점에 일조할 수 있다.The present invention is a technology that can be applied to the CVD-W as a gate electrode (word line), solved the problem of reoxidation that remained a technical problem in the conventional process, and improves the interface stability between tungsten and the gate oxide film In addition, damage to the gate oxide film and the underlying layer due to fluorine infiltration can be solved. From an economical point of view, the gate electrode is formed of tungsten (W), which has much higher electrical conductivity than conventional polysilicon or silicide type electrode materials, thereby maximizing the signal transfer speed of semiconductor devices and increasing the added value. It can contribute to preoccupation of the market.
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| KR100939777B1 (en) | 2007-11-30 | 2010-01-29 | 주식회사 하이닉스반도체 | Method for forming tungsten layer and method for forming wiring of semiconductor device using the same |
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| JPS63300535A (en) * | 1987-05-30 | 1988-12-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH05347272A (en) * | 1991-01-26 | 1993-12-27 | Sharp Corp | Manufacture of semiconductor device |
| KR930005118A (en) * | 1991-08-21 | 1993-03-23 | 김광호 | Manufacturing Method of Semiconductor Device |
| JPH05129226A (en) * | 1991-11-01 | 1993-05-25 | Seiko Epson Corp | Manufacture of semiconductor device |
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