KR100319605B1 - Driving circuit for liquid crystal display - Google Patents
Driving circuit for liquid crystal display Download PDFInfo
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- KR100319605B1 KR100319605B1 KR1019990003550A KR19990003550A KR100319605B1 KR 100319605 B1 KR100319605 B1 KR 100319605B1 KR 1019990003550 A KR1019990003550 A KR 1019990003550A KR 19990003550 A KR19990003550 A KR 19990003550A KR 100319605 B1 KR100319605 B1 KR 100319605B1
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- 238000000034 method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
본 발명은 엘씨디 구동 회로에 관한 것으로, 종래 기술에 있어서 소오스 드라이버의 채널이 픽셀의 수에 비례함에 따라 상기 채널이 증가하는 경우 상기 소오스 드라이버내에 상기 증가된 채널수만큼의 버퍼 및 디코더를 구비함으로써, 상기 소오스 드라이버의 설계면적이 커지는 문제점이 있었다. 따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 소오스 드라이버내 하나의 채널 출력신호를 스위칭하여 복수의 픽셀을 구동함으로써, 상기 소오스 드라이버의 전체적인 버퍼 및 디코더의 수를 줄여 칩 설계면적을 최소화하는 효과가 있다.The present invention relates to an LCD driving circuit, and in the prior art, if the channel increases as the channel of the source driver is proportional to the number of pixels, by providing the increased number of buffers and decoders in the source driver, There is a problem in that the design area of the source driver is increased. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and by switching one channel output signal in a source driver to drive a plurality of pixels, thereby reducing the total number of buffers and decoders of the source driver to reduce the chip size. It has the effect of minimizing the design area.
Description
본 발명은 엘씨디 구동 회로에 관한 것으로, 특히 엘씨디 구동 회로에 있어서 소오스 드라이버내 하나의 채널 출력신호를 스위칭하여 복수의 픽셀을 구동하는 스위칭부를 구비하여 상기 소오스 드라이버의 채널수 및 칩 설계면적을 최소화한 엘씨디 구동 회로에 관한 것이다.The present invention relates to an LCD driving circuit. In particular, an LCD driving circuit includes a switching unit for driving a plurality of pixels by switching one channel output signal in a source driver to minimize the number of channels and the chip design area of the source driver. It relates to an LCD drive circuit.
도 1은 종래 엘씨디의 구성을 보인 개략도로서, 이에 도시된 바와 같이 복수의 픽셀(C11∼Cnm)로 구성된 디스플레이 패널(10)과; 상기 디스플래이 패널(10)의 복수의 채널(CH1∼CHm)중 해당 채널을 선택하여 디코딩된 신호를 버퍼(B1∼Bm)를 통해 출력하는 소오스 드라이버(20)와; 상기 소오스 드라이버(20)에서 선택된 채널의 해당 픽셀을 선택하는 게이트 드라이버(30)로 구성되며, 상기 복수의 픽셀(C11∼Cnm)은 게이트에 인가되는 상기 게이트 드라이버(30)의 출력 전압에 의해 드레인의 상기 소오스 드라이버(20)의 출력신호를 전달하는 엔모스 트랜지스터(NM11)와; 상기 엔모스 트랜지스터(NM11)를 통해 인가되는 상기 소오스 드라이버(20)의 출력신호를 저장하는 커패시터(CP11)로 구성되며, 이와 같이 구성된 종래 기술에 따른 동작과정을 상세히 설명한다.1 is a schematic view showing a configuration of a conventional LCD, a display panel 10 composed of a plurality of pixels (C11 to Cnm) as shown therein; A source driver 20 for selecting a corresponding channel among the plurality of channels CH1 to CHm of the display panel 10 and outputting a decoded signal through the buffers B1 to Bm; The gate driver 30 selects a corresponding pixel of a channel selected by the source driver 20, and the plurality of pixels C11 to Cnm are drained by an output voltage of the gate driver 30 applied to a gate. An NMOS transistor NM11 for transferring an output signal of the source driver 20 of the source driver 20; A capacitor CP11 configured to store an output signal of the source driver 20 applied through the NMOS transistor NM11 will be described in detail.
우선, 소오스 드라이버(20)에 인가되는 디지탈 입력 신호들은 복수의 채널(CH1∼CHm) 각각의 디코더(D1∼Dm)에 의해 아날로그 값으로 변환된 후, 각각의 버퍼(B1∼Bm) 입력단으로 입력된다.First, the digital input signals applied to the source driver 20 are converted into analog values by the decoders D1 to Dm of the plurality of channels CH1 to CHm, and then input to the respective inputs of the buffers B1 to Bm. do.
그리고, 상기 소오스 드라이버(20)는 상기 디스플레이 패널(10)의 복수의 채널(CH1∼CHm)중 하나의 채널(CHi)을 선택하여, 상기 복수의 채널(CH1∼CHm)의 출력단을 형성하는 상기 버퍼(B1∼Bm)를 통해 복수의 픽셀(C11∼Cnm)로 구성된 디스플레이 패널(10)로 출력하게 된다.The source driver 20 selects one channel CHi among the plurality of channels CH1 to CHm of the display panel 10 to form an output terminal of the plurality of channels CH1 to CHm. The output is performed to the display panel 10 including the plurality of pixels C11 to Cnm through the buffers B1 to Bm.
여기서, 게이트 드라이버(30)에 의해 선택되는 각 로우 라인으로 상기 소오스 드라이버(20)에 의해 선택된 채널(CHi)내 해당 픽셀(Ci1∼Cim)중 해당 픽셀(Cij)의 엔모스 트랜지스터(NMij)로 고전위를 출력하게 된다.Here, each row line selected by the gate driver 30 to the NMOS transistor NMij of the pixel Cij among the pixels Ci1 to Cim in the channel CHi selected by the source driver 20. Will output a high potential.
따라서, 상기 픽셀(Cij)의 커패시터(CPij)에 상기 소오스 드라이버(20)의 출력신호를 저장하게 된다.Therefore, the output signal of the source driver 20 is stored in the capacitor CPij of the pixel Cij.
상기와 같이 종래의 기술에 있어서 소오스 드라이버의 채널이 픽셀의 수에 비례함에 따라 상기 채널이 증가하는 경우 상기 소오스 드라이버내에 상기 증가된 채널수만큼의 버퍼 및 디코더를 구비함으로써, 상기 소오스 드라이버의 설계면적이 커지는 문제점이 있었다.As described above, when the channel of the source driver increases as the channel of the source driver increases in proportion to the number of pixels, the buffer area and the decoder of the increased number of channels are provided in the source driver. There was this growing problem.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 소오스 드라이버내 하나의 채널 출력신호를 스위칭하여 복수의 픽셀을 구동하는 스위칭부를 구비하여 상기 소오스 드라이버의 채널수 및 칩 설계면적을 최소화한 엘씨디 구동 회로를 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and includes a switching unit for driving a plurality of pixels by switching one channel output signal in a source driver, thereby providing the channel number and chip design area of the source driver. The purpose is to provide an LCD driving circuit that minimizes the
도 1은 종래 엘씨디 구동 회로의 구성을 보인 개략도.1 is a schematic view showing the configuration of a conventional LCD drive circuit.
도 2는 본 발명 엘씨디 구동 회로의 구성을 보인 개략도.Figure 2 is a schematic diagram showing the configuration of the present invention the LCD drive circuit.
도 3은 도 2에서 본 발명의 다른 일실시예를 적용한 스위치의 구성을 보인 개략도.Figure 3 is a schematic diagram showing the configuration of a switch applying another embodiment of the present invention in FIG.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
100 : 소오스 드라이버110 : 스위칭부100: source driver 110: switching unit
NM1∼NMm,NM11 : 엔모스 트랜지스터S1∼S4 : 전송게이트NM1 to NMm, NM11: NMOS transistors S1 to S4: transfer gate
I1,I2 : 인버터I1, I2: Inverter
상기와 같은 목적을 달성하기 위한 본 발명 엘씨디 구동 회로의 구성은 복수의 픽셀로 구성된 디스플래이 패널과; 복수의 디코더에서 디코딩된 신호를 복수의 버퍼를 통해 각기 입력받아 제1,제2 제어신호에 의해 제어를 받는 복수의 스위칭부를 통해 상기 디스플래이 패널내 복수의 채널중 선택된 채널로 출력하는 소오스 드라이버와; 상기 소오스 드라이버에서 선택된 채널의 해당 픽셀을 선택하는 게이트 드라이버로 구성하여 된 것을 특징으로 한다.In order to achieve the above object, a configuration of an LCD driving circuit of the present invention includes a display panel including a plurality of pixels; A source driver configured to receive signals decoded by a plurality of decoders through a plurality of buffers and to output selected channels among a plurality of channels in the display panel through a plurality of switching units controlled by first and second control signals; And a gate driver for selecting a corresponding pixel of a channel selected by the source driver.
상기 스위칭부의 구성은 각각 한쌍의 버퍼의 출력을 제1,제2 제어신호에 의해 두쌍의 채널로 선택하여 출력하는 복수의 스위치로 구성하여 된 것을 특징으로 한다.The switching unit may be configured as a plurality of switches each of which selects and outputs a pair of channels to two pairs of channels by the first and second control signals.
이하, 본 발명에 따른 일실시예에 대한 동작과 작용효과를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.
도 2는 본 발명을 적용한 엘씨디의 구성을 보인 개략도로서, 이에 도시한 바와 같이 복수의 픽셀(C11∼Cnm)로 구성된 디스플래이 패널(10)과; 디코더(D1-)에서 각기 디코딩된 신호를 버퍼(B1∼)를 통해 입력받아 제1,제2 제어신호(OS1)(OS2)에 의해 제어받는 스위칭부(110)를 통해 상기 디스플래이 패널(10)내 복수의 채널(CH1∼CHm)중 선택된 채널로 출력하는 소오스 드라이버(100)와; 상기 소오스 드라이버(100)에서 선택된 채널의 해당 픽셀을 선택하는 게이트 드라이버(30)로 구성하며, 상기 스위칭부(110)는 각각 한쌍의 버퍼의 출력을 제1,제2 제어신호(OS1)(OS2)에 의해 두쌍의 채널로 선택하여 출력하는 복수의 스위치(SW1∼)로 구성한다.Fig. 2 is a schematic view showing the configuration of an LCD to which the present invention is applied, and as shown therein, a display panel 10 composed of a plurality of pixels C11 to Cnm; Decoder (D1- Decoded signals from the buffers B1 to Receiving the input through the first and second control signals (OS1) (OS2) controlled by the switching unit 110 to output to the selected channel of the plurality of channels (CH1 ~ CHm) in the display panel 10 A source driver 100; The gate driver 30 selects a corresponding pixel of a channel selected by the source driver 100, and the switching unit 110 respectively outputs a pair of buffers to the first and second control signals OS1 and OS2. Multiple switches (SW1 to ...) to select and output to two pairs of channels ).
그리고, 상기 복수의 스위치(SW1∼)는 각각 게이트에 인가되는 제1 제어신호(OS1)에 의해 상기 복수의 버퍼(B1∼)의 출력을 각각의채널(CH1,CH2,CH5,CH6,…,CHM-3,CHM-2)로 출력하는 복수의 엔모스 트랜지스터(NM1,NM2,NM5,NM6,…,NMM-3,NMM-2)와; 각각 게이트에 인가되는 제2 제어신호(OS2)에 의해 각각 상기 복수의 버퍼(B1∼)의 출력을 각각의 채널(CH3,CH4,CH7,CH8,…,CHM-1,CHM)로 출력하는 복수의 엔모스 트랜지스터(NM3,NM4,NM7,NM8,…,NMM-1,NMM)로 구성하며, 이와 같이 구성한 본 발명에 따른 동작과정을 상세히 설명한다.The plurality of switches SW1 to ) Are each of the buffers B1 to 1 by the first control signal OS1 applied to the gate. ) And a plurality of NMOS transistors NM1, NM2, NM5, NM6, ..., NM M- outputting the output of each channel to the respective channels CH1, CH2, CH5, CH6, ..., CH M-3 , CH M-2 . 3 , NM M-2 ); Each of the plurality of buffers B1 to 1 by the second control signal OS2 applied to the gate, respectively. ) And a plurality of NMOS transistors NM3, NM4, NM7, NM8, ..., NM M-1 , which output the output of each channel (CH3, CH4, CH7, CH8, ..., CH M-1 , CH M ). NM M ), and the operation process according to the present invention configured as described above will be described in detail.
우선, 복수의 디코더(D1∼)에서 디코딩된 신호는 각각 복수의 버퍼(B1∼)를 통해 스위칭부(110)로 출력되며, 상기 스위칭부(110)는 제1 제어신호(OS1)가 고전위로 인가되면, 각각 게이트에 상기 고전위의 제1 제어신호(OS1)를 인가받은 복수의 엔모스 트랜지스터(NM1,NM2,NM5,NM6,…,NMM-3,NMM-2)가 턴온되어 상기 버퍼(B1∼)의 출력을 각각 복수의 채널(CH1,CH2,CH5,CH6,…,CHM-3,CHM-2)로 출력한다.First, a plurality of decoders D1 to Signal decoded by each of the plurality of buffers B1 to Is output to the switching unit 110, and the switching unit 110 receives the first control signal OS1 of the high potential to the gate when the first control signal OS1 is applied at the high potential, respectively. NMOS transistors NM1, NM2, NM5, NM6, ..., NM M-3 and NM M-2 of the transistors are turned on and the buffers B1 to ) Are output to a plurality of channels CH1, CH2, CH5, CH6, ..., CH M-3 and CH M-2 , respectively.
그리고, 제2 제어신호(OS2)가 고전위로 인가됨에 따라 이를 게이트에 인가받은 복수의 엔모스 트랜지스터(NM3,NM4,NM7,NM8,…,NMM-1,NMM)가 턴온되어 상기 버퍼(B1∼)의 출력을 복수의 채널(CH3,CH4,CH7,CH8,…,CHM-1,CHM)로 출력한다.As the second control signal OS2 is applied at a high potential, a plurality of NMOS transistors NM3, NM4, NM7, NM8,..., NM M-1 , and NM M applied to the gate are turned on and the buffer ( B1- ) Is output to a plurality of channels CH3, CH4, CH7, CH8, ..., CH M-1 and CH M.
그리고, 게이트 드라이버(30) 및 디스플래이 패널(10)의 동작은 종래 도 1과 동일하게 동작한다.The gate driver 30 and the display panel 10 operate in the same manner as in FIG. 1.
여기서, 본 발명에서의 기본적인 구동방식인 도트 인버젼(Dot Inversion) 방식은 2개의 칼럼라인이 하나의 쌍을 이루고, 각 채널의 칼럼 라인들은 서로 엇갈리게 배치되어 양,음,양,음으로 출력한다.Here, the dot inversion method, which is a basic driving method according to the present invention, has two column lines as one pair, and the column lines of each channel are alternately arranged to output positive, negative, positive and negative. .
즉, 상기 디스플래이 패널(10)의 제1∼제4 채널(CH1∼CH4)에서의 구동하는 상기 제1 스위치(SW1)의 동작을 보면, 제1 디코더(D1)의 출력은 양의 값으로써 제1 채널(CH1)과 제2 채널(CH3)내 복수의 픽셀(C11∼Cn1)(C12∼Cn2)중 상기 게이트 드라이버(30)에서 선택된 픽셀에 저장하고, 제2 디코더(D2)의 출력은 음의 값으로써 제2 채널(CH2)과 제4 채널(CH4)내 복수의 픽셀(C11∼Cn1)(C12∼Cn2)중 상기 게이트 드라이버(30)에서 선택된 픽셀에 저장한다.That is, the operation of the first switch SW1 for driving in the first to fourth channels CH1 to CH4 of the display panel 10 shows that the output of the first decoder D1 is a positive value. Among the plurality of pixels C11 to Cn1 (C12 to Cn2) in one channel CH1 and the second channel CH3, the pixels are stored in the pixel selected by the gate driver 30, and the output of the second decoder D2 is negative. As a value of, it is stored in the pixel selected by the gate driver 30 among the plurality of pixels C11 to Cn1 and C12 to Cn2 in the second channel CH2 and the fourth channel CH4.
그리고, 상기 제1,제2 제어신호(OS1)(OS2)를 통해 상기 스위치(SW1)가 구동하는 시간은 종래 기술에서의 구동시간을 분할해서, 즉 전체 구동시간을 t라고 했을 때, t = t1+ t2로 나누어서 t1동안에는 상기 제1 제어신호(OS1)가 상기 스위치(SW1)에 인가되어 상기 채널(CH1)(CH2)의 픽셀(C11∼Cn1)(C12∼Cn2)을 구동하고, t2동안에는 상기 제2 제어신호(OS2)가 상기 스위치(SW1)에 인가되어 상기 채널(CH1)(CH2)의 픽셀(C11∼Cn1)(C12∼Cn2)을 구동한다.In addition, when the switch SW1 is driven through the first and second control signals OS1 and OS2, the driving time in the prior art is divided by, i.e., the total driving time is t. During t 1 divided by t 1 + t 2 , the first control signal OS1 is applied to the switch SW1 to drive the pixels C11 to Cn1 (C12 to Cn2) of the channels CH1 and CH2. During t 2 , the second control signal OS2 is applied to the switch SW1 to drive the pixels C11 to Cn1 and C12 to Cn2 of the channels CH1 and CH2.
도 3은 본 발명의 다른 일실시예의 구성을 보인 것으로, 상기 스위칭부의 구성을 엔모스 트랜지스터의 대신에 전송게이트를 이용하여 구성한 것이다. 즉, 스위칭부(110)내 복수의 스위치의 구성은 제1,제2 제어신호(OS1)(OS2)를 반전하여 출력하는 제1,제2 인버터(I1)(I2)와; 상기 제1 제어신호(OS1)를 비반전단자로 입력받고, 상기 제1 인버터(I1)의 출력신호를 반전단자에 입력받아 각각 제1,제2 버퍼(B1)(B2)의 출력을 제1,제2 채널(CH1)(CH2)로 전달하는 제1,제2 전송게이트(S1)(S2)와; 상기 제2 제어신호(OS2)를 비반전단자로 입력받고, 상기 제2 인버터(I2)의 출력신호를 반전단자에 입력받아 각각 상기 제1,제2 버퍼(B1)(B2)의 출력을 제3,제4 채널(CH3)(CH4)로 전달하는 제3,제4 전송게이트로 구성하며, 그의 동작을 상기 도 2와 동일하게 동작한다.3 shows a configuration of another embodiment of the present invention, in which the switching unit is configured using a transfer gate instead of an NMOS transistor. That is, the configuration of the plurality of switches in the switching unit 110 includes: first and second inverters I1 and I2 inverting and outputting the first and second control signals OS1 and OS2; The first control signal OS1 is input to the non-inverting terminal, the output signal of the first inverter I1 is input to the inverting terminal, and the outputs of the first and second buffers B1 and B2 are respectively first. A first and second transmission gates S1 and S2 for transmitting to the second channel CH1 and CH2; The second control signal OS2 is input to the non-inverting terminal and the output signal of the second inverter I2 is input to the inverting terminal to respectively output the first and second buffers B1 and B2. The third and fourth transmission gates are transmitted to the third and fourth channels CH3 and CH4, and their operations are the same as those of FIG.
상기에서 상세히 설명한 바와 같이, 본 발명은 소오스 드라이버내 하나의 채널 출력신호를 스위칭하여 복수의 픽셀을 구동함으로써, 상기 소오스 드라이버의 전체적인 버퍼 및 디코더의 수를 줄여 칩 설계면적을 최소화하는 효과가 있다.As described in detail above, the present invention has the effect of minimizing the chip design area by reducing the total number of buffers and decoders of the source driver by switching a single channel output signal in the source driver to drive a plurality of pixels.
Claims (4)
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| KR1019990003550A KR100319605B1 (en) | 1999-02-03 | 1999-02-03 | Driving circuit for liquid crystal display |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100674976B1 (en) | 2005-06-03 | 2007-01-29 | 삼성전자주식회사 | Apparatus and method for driving gate lines using shared circuit in flat panel display |
| US7489262B2 (en) | 2006-04-18 | 2009-02-10 | Samsung Electronics Co., Ltd. | Digital to analog converter having integrated level shifter and method for using same to drive display device |
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| JP2002297109A (en) * | 2001-03-30 | 2002-10-11 | Fujitsu Ltd | Liquid crystal display device and driving circuit therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100674976B1 (en) | 2005-06-03 | 2007-01-29 | 삼성전자주식회사 | Apparatus and method for driving gate lines using shared circuit in flat panel display |
| US7489262B2 (en) | 2006-04-18 | 2009-02-10 | Samsung Electronics Co., Ltd. | Digital to analog converter having integrated level shifter and method for using same to drive display device |
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