KR100319381B1 - Apparatus for connecting between inter working function exchanges - Google Patents

Abstract

The present invention relates to a heterogeneous switching period matching device, comprising: a data link matching unit for matching inter-processor communication data and voice data from an internal connection network subsystem; A clock converter for converting a clock ratio for voice data provided from the data link matching unit; A separator for separating interprocessor communication data and voice data provided from the data link matching unit; A transmission memory for storing voice data separated by the separator; A reception memory for receiving voice data stored in a transmission memory of the other matching device; An address generator for generating an address for allocating addresses of transmit and receive memories using the clock frequency converted from the clock converter; Ultra (U) link matching unit for matching to transmit the inter-processor communication data separated in the separator to the upper processor; Reads the voice data of the other matching device stored in the receiving memory, converts the clock ratio of the read voice data, and combines the voice data of the converted clock frequency with inter-processor communication data received from the U link matching unit to match the data link. And a clock conversion and combiner for transmitting to the matched exchange subsystem via the unit. Therefore, there is an effect that can give a big development in the development of the switch system by meeting the needs of advanced and various services.

Description

This model exchange period matching device {APPARATUS FOR CONNECTING BETWEEN INTER WORKING FUNCTION EXCHANGES}

The present invention relates to an interworking function matching device of the same type (Inter Working Function, hereinafter abbreviated as IWF), and in particular, can be interworked between two exchangers having different call processing capabilities, for example, a TDX-10A exchanger and a TDX-100 exchanger. It's about a matching device that makes it possible.

Typically, an electronic switch, e.g., a TDX-10A and a TDX-100 switch, has an Access Switching Subsystem (abbreviated ASS), which performs its respective call processing and self-operation maintenance functions, Interconnection Network Subsystem (abbreviated as INS) that performs centralized functions such as translation, route control, space switch connection, and central control subsystem that performs centralized operation and maintenance functions. subsystem).

In the conventional exchanger configured as described above, the number of channels corresponding to the time slots is different between the heterogeneous exchanges, that is, the TDX-10A and the TDX-100. For example, the TDX-10A exchange uses 32 channels in one time slot, while the TDX-100 exchange uses 64 channels in one time slot, making it impossible to interoperate these exchanges. Therefore, a matching device for stable interworking with each other during this model exchange period was required.

Accordingly, the present invention has been made by the above-described necessity, and an object thereof is to provide a heterogeneous exchange period matching device that enables interworking between the heterogeneous exchange units using a matching device.

In the present invention for achieving this object, the heterogeneous switching period matching device includes a data link matching unit for matching to receive inter-processor communication data and voice data from the internal connection network subsystem; A clock converter for converting a clock ratio for voice data provided from the data link matching unit; A separator for separating interprocessor communication data and voice data provided from the data link matching unit; A transmission memory for storing voice data separated by the separator; A reception memory for receiving voice data stored in a transmission memory of the other matching device; An address generator for generating an address for allocating addresses of transmit and receive memories using the clock frequency converted from the clock converter; Ultra (U) link matching unit for matching to transmit the inter-processor communication data separated in the separator to the upper processor; Reads the voice data of the other matching device stored in the receiving memory, converts the clock ratio of the read voice data, and combines the voice data of the converted clock frequency with inter-processor communication data received from the U link matching unit to match the data link. And a clock conversion and combiner for transmitting to the matched exchange subsystem via the unit.

1 is a block diagram of a heterogeneous switching period matching device according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: INS 200, 300: first and second matching device

201, 301: data link matching section 203, 303: clock converter

205, 305: address generator 207, 307: transmission memory

209, 309: Separator 211, 311: U link matching part

213, 313: reception memory 215, 315: clock conversion and combiner

400: ASS 500, 600: Upper Processor

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.

Figure 1 shows a block diagram of a heterogeneous exchange period matching device that matches different types of exchanges, e.g., TDX-10A and TDX-100 exchanges, according to the present invention. In general, an electronic changer such as a TDX-10A or TDX-100 includes an INS 100, an ASS 400, and higher processor 500, 600. The matching device of the present invention includes a first matching device (200) arranged in relation to an INS or ASS of a first type exchanger and a second type exchanger to match a heterogeneous exchange period such as a TDX-10A or a TDX-100. And a second matching device 300 disposed in association with the ASS or INS.

As described above, the first and second matching devices 200 and 300 of the present invention are disposed in relation to the heterogeneous exchanges, that is, the TDX-10A or the TDX-100 exchanger, thereby inter-processor communication of the TDX-10A. The IPC data and voice data generated in the TDX-100 can be converted into data suitable for the TDX-10A.

Hereinafter, the description of the present invention will explain the matching process performed between the INS 100 of the TDX-100 and the ASS 400 of the TDX-10A. Of course, the reverse is also possible.

The INS 100 is an internal connection network subsystem of the TDX-100 or TDX-10A switch, and transmits 64 channels of IPC data and voice data to the first matching device 200.

ASS 400 is a matching exchange subsystem of a TDX-100 or TDX-10A switch, and transmits 32 channels of IPC data and voice data to second matching device 300.

At each exchange, the upper processor 500, 600 exchanges IPC data with the first and second matching devices 200, 300.

The first matching device 200 is a block for transmitting IPC data and voice data received from the INS 100 to the second matching device 300. The first matching device 200 includes a data link matching unit 201, a clock converter 203, An address generator 205, a transmission memory 207, a separator 209, an ultra (U) link matching section 211, a reception memory 213, and a clock converter and combiner 215 are provided.

The data link matching unit 201 transmits the IPC data and the voice data received from the INS 100 to the separator 209 and extracts only the voice data to the clock converter 203.

The clock converter 203 converts a clock ratio for voice data provided from the data link matching unit 201. For example, since the clock period of the voice data generated by the TDX-100 is 19Mhz, the clock period of the voice data generated by the TDX-10A is converted to 16Mhz, which is required by the TDX-10A. Convert to 19Mhz clock frequency. The converted voice data clock is transmitted to the address generator 205. Thereafter, the clock converter 203 deletes the voice data received from the data link matching unit 201.

The address generator 205 uses the clock frequency converted from the clock converter 203 to generate an address for allocating addresses of the transmission and reception memories 207 and 213.

Separator 209 separates IPC data and voice data received from data link matching section 201. The separated IPC data is transmitted to the U link matching section 211, and the separated voice data is stored in the transmission memory 207 having an address assigned by the address generator 205. FIG. Thereafter, the voice data stored in the transmission memory 207 is transmitted in parallel to the receiving memory 313 in the second matching device 300 by being grouped in units of 8 bits by the separator 209.

The U link matching unit 211 transmits the IPC data received from the separator 209 to the upper processor 500, and transmits the IPC data received from the upper processor 500 to the clock converter and combiner 215.

The clock converting and combining unit 215 reads the voice data stored in the receiving memory 213, converts the clock period of the read 19Mhz voice data into 16Mhz, the voice data of the converted clock frequency, and the U link matching unit 211. Combine the IPC data provided by The IPC data and voice data combined in the clock conversion and combiner 215 are transmitted to the data link matching unit 201.

Meanwhile, the second matching device 300 is a block for transmitting the voice data received from the first matching device 200 to the ASS 400, and includes a data link matching unit 301, a clock converter 303, and an address. A generator 305, a transmission memory 307, a separator 309, a U link matching section 311, a reception memory 313, and a clock converter and combiner 315 are provided.

Since the second matching device 300 is substantially similar in configuration and operation to the above-described first matching device 200, detailed operations of each component except for the clock conversion and combiner 315 are omitted.

The clock converting and combining unit 315 is provided from the transmitting memory 207 of the first matching device 200 and simultaneously reads 16 Mhz voice data stored separately in 32 channels in the receiving memory 313, and simultaneously reads the read voice data. The clock period is converted back to 19 Mhz, and the voice data of the converted clock frequency and the IPC data and voice data received and combined from the U link matching unit 311 are transmitted to the data link matching unit 301. The data link matching unit 301 transmits IPC data and voice data to the ASS 400.

As described above, the process in which IPC data and voice data proceed from the INS 100 to the ASS 400 has been described. Hereinafter, the process in which the IPC data and voice data proceeds from the ASS 400 to the INS 100 is performed. It demonstrates.

The ASS 400 transmits 32 channel IPC data and voice data to the data link matching unit 301 using two time slots, as shown in FIG. 1.

The data link matching unit 301 transmits the IPC data and the voice data received from the ASS 400 to the separator 309 and simultaneously extracts only the voice data and transmits the voice data to the clock converter 303.

The clock converter 303 converts the clock ratio for the voice data provided from the data link matching unit 301. For example, since the clock cycle of the voice data generated by the TDX-10A is 16 MHz, it is converted to 19 MHz required by the TDX-100. The converted voice data clock is transmitted to the address generator 305. Thereafter, the clock converter 303 deletes the voice data received from the data link matching unit 301.

The address generator 305 uses the clock frequency converted from the clock converter 303 to generate an address for allocating addresses of the transmission and reception memories 307 and 313.

Separator 309 separates IPC data and voice data received from data link matching unit 301. The separated IPC data is transmitted to the U link matching section 311, and the separated voice data is stored in an address in the transmission memory 307 allocated by the address generator 305. Thereafter, the voice data stored in the transmission memory 307 are bundled in 8-bit units by the separator 309 and transmitted in parallel to the reception memory 213 in the first matching device 200.

The U link matching unit 311 transmits the IPC data received from the separator 309 to the upper processor 600, and transmits the IPC data received from the upper processor 600 to the clock converter and combiner 315.

The clock converter and combiner 315 reads the voice data stored in the reception memory 313, converts the clock cycle of the read 16Mhz voice data into 19Mhz, the voice data of the converted clock frequency, and the U-link matching unit 311. Combine the IPC data provided by The IPC data and voice data combined in the clock converter and combiner 315 are transmitted to the data link matcher 301.

On the other hand, the clock conversion and combiner 215 in the first matching device 200 is provided from the transmission memory 307 of the second matching device 300 and is coupled to the received memory 213 by 64 channels, respectively, and stored in 19 Mhz voice data. And simultaneously convert the clock period of the read voice data back to 16 Mhz, and convert the voice data of the converted clock frequency and the IPC data and voice data received and combined from the U link matching unit 211 into a data link matching unit. To 201. The data link matching unit 201 transmits IPC data and voice data to the INS 100.

Accordingly, the present invention performs the matching function so that the first and second matching devices 200 and 300 can be stably interlocked with each other during the exchange period of the heterogeneous exchanges, that is, the TDX-10A and the TDX-100.

The present invention as described above has the effect of providing a great development in the development of the switch to meet the advancement and various service needs by interworking the heterogeneous exchange using a matching device.

Claims (2)

The at least two exchanges each having a matching exchange subsystem, an internal network subsystem, and a higher processor, each of which is arranged in relation to the matching exchange subsystem of the first exchange and the internal network subsystem of the second exchange. In the device for matching this type exchanger, Each matching device is: A data link matching unit for matching inter-processor communication data and voice data from the internal connection network subsystem; A clock converter for converting a clock ratio for the voice data provided from the data link matching unit; A separator for separating interprocessor communication data and voice data provided from the data link matching unit; A transmission memory for storing voice data separated by the separator; A reception memory for receiving voice data stored in a transmission memory of the other matching device; An address generator for generating an address for allocating addresses of the transmitting and receiving memories using the clock frequency converted from the clock converter; An ultra link matching unit for matching inter-processor communication data separated by the separator to transmit to the upper processor; Read voice data of the other matching device stored in the receiving memory, convert a clock ratio of the read voice data, and combine voice data of the converted clock frequency with inter-processor communication data received from the U link matching unit; And a clock converter and a combiner for transmitting the data link matching unit to the matching exchange subsystem. The method of claim 1, wherein the clock converter, And a clock period of the voice data provided from the first type switch is converted into a clock frequency required by the second type switch.