KR100319197B1 - Flat panel display apparatus - Google Patents

Abstract

When the number of source drive integrated circuits configured to output data signals is an odd number, the timing for driving the divided screens is controlled by virtually setting the source drive integrated circuits to set the output of the data signals to divide the screen. The present invention relates to a flat panel display device, wherein a driving operation for dividing at least one or more screens is performed for each timing controller, and when the number of source drive integrated circuits does not match for each of them, a virtual source drive integrated circuit is set and virtual data based on a default value. The output is performed.

Accordingly, the present invention can realize a screen having a high resolution by a split driving of a screen, and effectively adjust the timing of data corresponding to the divided screen by applying a virtual source drive integrated circuit to maximize the screen splitting effect. It is possible to solve the pin shortage by designing the number of timing controllers to correspond to the divided screens.

Description

Flat panel display apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device. More particularly, when the number of source drive integrated circuits configured to output data signals is an odd number, the source drive integrated circuit is virtually set to output the data signal in order to divide the screen. The present invention relates to a flat panel display device that adjusts a timing for driving a divided screen by setting.

Recently, a variety of flat panel display technologies have been developed, and the most widely used flat panel display technologies are liquid crystal displays applied to products such as notebook computers and wall-mounted televisions.

In order to realize high resolution and a large screen, flat panel display apparatuses have a problem of gradually processing data at high frequency, and in order to solve problems such as signal delay or EMI generated to process such data at high frequency, A screen division driving method or the like is used.

In the design of a liquid crystal display device having a resolution of 1920 × 1200, if frequency division or screen division is not considered, the pixel frequency must satisfy 198 MHz, and the drive integrated circuit and the timing controller can accommodate it in order to process the pixel frequency. Should be

However, in the case of using a 384 channel source drive integrated circuit to realize a resolution of 1920 × 1200, 15 source drive integrated circuits are required, and the screen is divided left and right, and the screen divided to the left and right is even. The drive can be divided into and odd. Then, the signal input to the source drive integrated circuit has a frequency divided by four, that is, 49.5 MHz, compared to the frequency input to the timing controller. In the case of the timing controller, many pins are around 300 pins, and data input to the timing controller is often divided into two due to an interface problem. Accordingly, a high resolution screen can be realized without the need for a high speed timing controller or a source drive integrated circuit.

However, as described above, in the case of having an odd number of source drive integrated circuits, in order to divide the screen, the number of left and right divided source drive integrated circuits is not the same.

As an alternative to this, a method of adjusting timing may be proposed. However, since it is a significant problem to adjust the timing when the frequency is actually adjusted, development of an effective alternative is desired.

An object of the present invention is to implement a screen in a high resolution of the flat panel display device by splitting the screen.

Another object of the present invention is to apply the virtual source drive integrated circuit to match the number of the source drive integrated circuit for each divided screen to control the timing controller to effectively implement screen division.

Another object of the present invention is to solve the lack of pin number by configuring a plurality of timing controllers to drive the screen is divided to implement a high resolution.

1 is a block diagram showing a first preferred embodiment of a flat panel display device according to the present invention.

FIG. 2 is a waveform diagram illustrating a relationship between a horizontal synchronization signal and input data input to the timing controller of FIG. 1. FIG.

3 is a waveform diagram illustrating a relationship between a horizontal synchronization signal output from the timing controller of FIG. 1 and output data;

4 is a block diagram showing a second embodiment of the present invention;

5 is a waveform diagram illustrating the embodiment of FIG. 4.

6 is a block diagram showing a third embodiment of the present invention.

7 is a block diagram showing a fourth embodiment of the present invention.

8 is a block diagram showing a fifth embodiment of the present invention.

According to an exemplary embodiment of the present invention, a flat panel display apparatus includes a voltage generating means for generating gate on / off voltage and gray scale voltages as a predetermined constant voltage, a liquid crystal panel for forming a predetermined screen, a gate control signal and a gate shift signal as data and control signals input from the outside And a first timing controller for generating a first shift signal, a first data signal, and a first control signal, and generating a second shift signal, a second data signal, and a second control signal using the data and control signals input from the outside. A second timing controller, gate drive integrated circuits providing gate signals to the liquid crystal panel with the gate control signal and the gate shift signal and the gate on / off voltage, the first and second shift signals and the first and second data; The signal and the first and second control signals and gray voltages. In crystal panel is composed of a source driver IC to provide the source signals.

Herein, the connection state of the virtual source drive integrated circuit is set to the second timing controller to maintain the same number as the number of source drive integrated circuits corresponding to the first timing controller, and the second timing controller is configured to control the first timing controller. A default value is output to the virtual source drive integrated circuit at the data output time of the last source drive integrated circuit corresponding to the first timing controller.

The second timing controller may perform the virtual output by setting a time point by a self-counting operation. The second timing controller receives a carry-out signal from the data latched from the last of the corresponding source drive integrated circuits, and receives the virtual output. Can be performed.

The synchronizing unit may further include a synchronizing unit configured to generate a synchronizing signal by comparing the data output of the first timing controller and the second timing controller. When the synchronizing signal is input from the synchronizing unit, the second timing controller may perform the virtual output. Can be.

Each of the timing controllers may be configured to output shift signals, data signals, and control signals for at least two screen divisions.

Hereinafter, exemplary embodiments of the flat panel display device according to the present invention will be described in detail with reference to the accompanying drawings.

The flat panel display device according to the present invention is configured to divide and drive a screen, and is configured to reduce the burden of pin coupling due to an increase in the timing controller input / output channel by disposing a timing controller for each divided-driven screen.

Referring to FIG. 1, according to the first embodiment of the present invention, source drive integrated circuits S1 to S13 for providing a source signal to the liquid crystal panel 10 are configured and a gate drive integrated circuit for providing a gate signal. (G1-G6) are comprised.

The gate drive integrated circuits G1 to G6 are configured to receive a gate on / off voltage from the gate voltage generator 12, and the source drive integrated circuits S1 to S13 are provided with two timing controllers 14 and 16. Are configured to receive the shift signals STH1, STH2 and the data signals D1, D2, and the control signals C1, C2, respectively, from the gray voltage generator 18.

In addition, the voltage supply unit 20 generates a plurality of constant voltages as an electrostatic source to provide the gate voltage generator 12 and the gray voltage generator 18 with a constant voltage at a level necessary to generate the gate on / off voltage and the gray voltages. It is configured to.

The timing controller 14 receives data and a control signal from a predetermined image signal source to generate the above-described shift signals STH1 and STH2, the data signals D1 and D2, and the control signals C1 and C2, together with the gate control signal and the shift signal. It is configured to generate and apply an STV to the gate drive integrated circuits G1 to G6, respectively.

As described above, the liquid crystal panel 10 is driven by splitting the screen to the left and right. For this purpose, the timing controller 14 applies the shift signal STH1, the data signal D1, and the control signal C1 to the source drive integrated circuits S1 to S7. The timing controller 16 is configured to output the shift signal STH2, the data signal D2, and the control signal C2 to the source drive integrated circuits S8 to S13.

In addition, the timing controllers 14 and 16 may divide data into even and odd signals to apply data to the corresponding source drive integrated circuits.

Therefore, the data input to the timing controllers 14 and 16 can be divided into two according to the screen division and processed by the timing controllers 14 and 16, and the timing controllers 14 and 16 output the data when ibn and odd are output. The data can be divided and output by dividing by. Eventually, the frequency of the data applied to the source drive integrated circuits may be divided into four than the frequency of the data input to the original timing controllers 14 and 16, so that the timing controllers and the source drive integrated circuits operate at a lower frequency. In order to drive a screen having a resolution of 1920 × 1200, a timing controller needs to satisfy a frequency of 198/2 MHz, and a source drive integrated circuit needs to satisfy a frequency of 198/4 MHz.

Meanwhile, the specific operation of FIG. 1 described above will be described with reference to FIGS. 2 and 3.

When the constant voltage is supplied to the voltage supply unit 20, the voltage supply unit 20 supplies DC voltages of required levels to the gate voltage generator 12 and the gray voltage generator 18, respectively.

Accordingly, the gate voltage generator 12 generates the gate on / off voltages of voltages of about 20V and about -7V required for turning on / off the gates of the liquid crystal panel 10 as the gate on / off voltages. It provides in the G1-G6.

In addition, the gray voltage generator 18 generates a plurality of levels of gray voltages in consideration of a predetermined gray level, and provides them to the source drive integrated circuits S1 to S13. The gray voltage having the voltage is provided to each of the source drive integrated circuits S1 to S13.

In addition, the timing controller 14 receives data and control signals from a predetermined image signal source, generates a gate control signal and a shift signal STV, and supplies them to the respective gate drive integrated circuits G1 to G6. The circuits G1 to G6 sequentially output gate on / off voltages for each gate line (not shown) of the liquid crystal panel 10 in one direction.

Meanwhile, the timing controllers 14 and 16 select and receive data on a corresponding screen from among data transmitted in serial. The timing controller 14 adjusts the timing format of the data signal D1, the control signal C1, and the shift signal STH1 to be output by the control signal, and then outputs it to the source drive integrated circuits S1 to S7. At this time, the data signal D1 divides the corresponding data into an even and an odd and outputs the data. The timing controller 16 also adjusts the timing format of the data signal D2, the control signal C2, and the shift signal STH2 in the same manner, and outputs the same to the source drive integrated circuits S8 to S13.

At this time, the timing controller 16 counts the virtual source drive integrated circuit S14.

In detail, when the screen of the liquid crystal panel 10 is divided, the screen is divided into source drive integrated circuit units, and since the total number of source drive integrated circuits is an odd number, the seven types of source drives are integrated into the timing controller 14. Circuits correspond, and six source drive integrated circuits correspond to the timing controller 16.

In this case, since the number of the source drive integrated circuits does not match for each of the timing controllers 14 and 16, it is necessary to adjust the output timing of the data signal.

To this end, the above-described virtual source drive integrated circuit S14 is set.

As the virtual source drive integrated circuit S14 is set, the timing controller 16 virtually generates the virtual source drive integrated circuit S14 when the timing controller 14 makes a data input to the source drive integrated circuit S7. Perform a virtual data output operation.

That is, as shown in FIG. 2, the timing controllers S14 and S16 read data about one horizontal line to form a screen as the input horizontal synchronization signal Hsync. The timing controllers S14 and S16 select and input the corresponding data among the input data transmitted through the serial, and then output the output data 1 and the output data 2 based on the output Hsync included in the control signal as shown in FIG. 3.

In this case, since the number of the source drive integrated circuits does not match for each of the timing controllers S14 and S16 as described above, when the data output to the source drive integrated circuit S7 is performed, the timing controller S16 may determine the output data 2 of FIG. 3. Output virtual data as much as hatched.

The virtual data output may be in various forms.

First, the timing controller 16 may be configured to give a default value to output a preset value to the empty output pin after the data output of the source drive integrated circuit S13, wherein the empty pin of the timing controller 16 is It is preferable to set in advance so as to correspond to the virtual source drive integrated circuit S14.

In this case, the default value may be set as a no-signal value or a value for storing data for the final source drive integrated circuit S13.

In addition, as shown in FIG. 4, the virtual data output may be configured to receive the carry-out signal of the source drive integrated circuit S13 and to output the above default value in synchronization with it.

Detailed description thereof will be described with reference to FIGS. 4 and 5. In FIG. 4, the source drive integrated circuits S1 to S13 and the timing controllers S14 and S16 have the same reference numerals as in FIG. 1, and FIG. 1. In contrast, the configuration in which the carry out signal of the source drive integrated circuit S13 is fed back to the timing controller S16 is different.

According to the configuration of the second embodiment described above, the timing controllers 14 and 16 output the output horizontal synchronization signal, the output data 1 and the output data 2 as shown in FIG.

Then, the source drive integrated circuit S1 to which the shift signal STH1 is applied from the timing controller 14 latches the corresponding data among the output data 1 by the shift signal STH1 and outputs a carryout signal. The carry out signal of the source drive integrated circuit S1 is input to the carry in signal Cl11 of the source drive integrated circuit S2, and accordingly, the source drive integrated circuit S2 latches the corresponding data. By repeating this process, data latches up to the source drive integrated circuit S7 are performed.

On the other hand, the source drive integrated circuit S8 to which the shift signal STH2 is applied from the timing controller 16 latches the corresponding data among the output data 2 and outputs a carryout signal by the shift signal STH2. The carry out signal of the source drive integrated circuit S8 is input to the carry in signal Cl21 of the source drive integrated circuit S9, and accordingly, the source drive integrated circuit S9 latches the corresponding data. By repeating this process, data latches up to the source drive integrated circuit S13 are performed.

The carry out signal of the source drive integrated circuit S13 is fed back to the timing controller 16, and the timing controller 16 performs virtual data output to the above-described default value.

Accordingly, the timing controllers 14 and 16 may set a time for latching data for one horizontal line at the same timing.

Alternatively, as shown in FIG. 6, a third embodiment for synchronizing the timing controllers 14 and 16 may be configured.

To this end, as shown in FIG. 6, in the third embodiment, a synchronization unit 30 for outputting a synchronization signal using data D1 and D2 output from the timing controller 14 and the timing controller 16 is configured.

The synchronization unit 30 compares the output data of both timing controllers 14 and 16 and outputs a synchronization signal to the timing controller 16 at the timing of no signal section of the timing controller 16, and the timing controller 16 is connected thereto. According to the above-described default value, the virtual data output may be performed.

The first to third embodiments described above are implemented in consideration of a liquid crystal panel having a resolution of 1920 × 1200, and may be similarly implemented for higher resolutions.

That is, in order to have high resolution as shown in FIG. 7, when the number of source drive integrated circuits is 15, eight source drive integrated circuits correspond to the timing controller 40, and seven source drive integrated circuits correspond to the timing controller 42. And one virtual source drive integrated circuit correspond.

In order to divide the frequency of the data, the timing controllers 40 and 42 divide the screen into four source drive integrated circuits, respectively, and drive the screen separately, and the shift signals STH11, STH12, STH13, STH14 and data signals D11, D12, D13, D14 and control signals C11, C12, C13, C14 may be output.

Also in this case, the timing controller 42 can perform default value setting and virtual data output for the virtual source drive integrated circuits S16 of the first to third embodiments described above, so that timing adjustment between timing controllers can be performed. have.

In addition, unlike the case of FIG. 7, a fifth embodiment in which four timing controllers are configured as shown in FIG. 8 may be configured. The fifth embodiment is a one-to-one timing controller in the fourth embodiment, and virtual The source drive integrated circuit setting, the default value setting, and the virtual data output may be made as in the first to fourth embodiments described above.

As described above, embodiments according to the present invention can reduce the frequency of data by dividing and dividing screens, thereby reducing the burden on the frequency of the timing controller and the source drive integrated circuit.

In addition, by configuring the virtual source drive integrated circuit to set the timing controller as in the embodiments, it is possible to accurately adjust the data timing between the timing controllers.

Accordingly, the present invention can realize a screen having a high resolution by a split driving of a screen, and effectively adjust the timing of data corresponding to the divided screen by applying a virtual source drive integrated circuit to maximize the screen splitting effect. can do.

In addition, by adjusting the number of timing controllers corresponding to the divided screens, there is an effect of solving the pin shortage in design.

Claims (5)

Voltage generation means for generating a gate on / off voltage and gray scale voltages as a predetermined constant voltage; A liquid crystal panel forming a predetermined screen; A first timing controller configured to generate a gate control signal, a gate shift signal, a first shift signal, a first data signal, and a first control signal as data and control signals input from the outside; A second timing controller configured to generate a second shift signal, a second data signal, and a second control signal by the data and the control signal input from the outside; Gate drive integrated circuits providing gate signals to the liquid crystal panel using the gate control signal, the gate shift signal, and a gate on / off voltage; And source drive integrated circuits providing source signals to the liquid crystal panel using the first and second shift signals, the first and second data signals, the first and second control signals, and the gray voltages. Set a connection state of a virtual source drive integrated circuit to the second timing controller to maintain the same number as the number of source drive integrated circuits corresponding to the first timing controller, wherein the second timing controller is configured to control the first timing controller. And a virtual value output to the virtual source drive integrated circuit at a data output time of the last source drive integrated circuit corresponding to the virtual output. The method of claim 1, And the second timing controller determines the viewpoint by the self counting operation to perform the virtual output. The method of claim 1, And the second timing controller receives the carry out signal from the last data latch of the corresponding source drive integrated circuits to perform the virtual output. The method of claim 1, A synchronization unit for generating a synchronization signal by comparing the data output of the first timing controller and the second timing controller is further configured, And the second timing controller performs the virtual output when a synchronization signal is input from the synchronization unit. The method of claim 1, And each of the timing controllers is configured to output a shift signal, a data signal, and a control signal for at least two screen divisions.