KR100315027B1 - Repair circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair circuit of a semiconductor memory device, wherein when a repaired memory chip is used for battery operation, the repair of the fuse fuse is incomplete, and when a residual is present in the fuse, power is applied from the power supply voltage at low voltage. Repair efficiency can be improved by breaking the current source path and allowing the repair fuse circuit to operate only above voltage levels that can prevent device failure.

Description

Repair circuit of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair circuit of a semiconductor memory device, and more particularly, to a repair circuit of a semiconductor memory device which prevents a device from failing due to incomplete cutting of a fuse due to battery operation and improves a repair yield.

In general, a semiconductor memory device has a plurality of memory cells arranged in a matrix of rows and columns, and as memory capacity increases, a larger number of memory cells are arranged in a unit area. On the other hand, in a semiconductor memory device, even if a defect occurs in any one memory cell, the semiconductor memory device cannot be used. Accordingly, as a method of improving a yield so that even if a defective memory cell exists, a defective memory is provided by providing a spar cell array in a normal memory cell array. A method of replacing a cell with a spare cell has been proposed.

That is, when a cell in which a row, column, or bit is failed in a normal cell of a semiconductor device is generated, an address signal according to performing a repair operation in a repair circuit is designated. Then, the repair is performed by replacing the corresponding cell among the spare cells by row or column unit.

FIG. 1 is a diagram illustrating a general repair circuit. As shown in FIG. 1, a fuse F1 is connected to a power supply voltage VCC, and an NMOS transistor NM1 is connected to a fuse F1 at a node N1. Leads to. In addition, an inverter INV1 is connected to the node N1, and an output terminal of the inverter INV1 is connected to a gate of the NMOS transistor NM1.

That is, although not shown, when a defect occurs in the memory cell, the fuse F1 is cut by increasing the operating power supply VCC. Accordingly, discharge occurs through the NMOS transistor NM1, and the node N1 has a low phase, a high signal is output through the inverter INV1, and an address according to the repair operation is designated. As a result, the repair proceeds.

On the other hand, although not shown, when using the battery operation in the memory cell, in order to prevent the reverse current from the controller to the battery, the operating power supply (VCC) is slowly increased over a period of time. At this time, when the fuse F1 of the repair circuit is not cut, a leakage current flows to the node N1 due to the remaining fuse, so that the phase of the node N1 does not satisfy the low, and eventually the inverter INV1. The repair signal of the high signal cannot be outputted through, and the repair address is not properly specified. As a result, failure of the device is caused, a malfunction of the memory device occurs, and a repair yield is reduced.

Accordingly, the present invention has been made to solve the above-mentioned conventional problem, and an object of the present invention is that repair fuse cutting is incomplete when a repaired memory chip is used in battery operation, so that a residue exists in the fuse. When the low voltage is applied while the power is applied, the repair circuit of the semiconductor memory device which cuts off the current source path from the power supply voltage (Vcc) and allows the repair fuse circuit to operate only at a voltage level that can prevent the device from failing. To provide.

1 is a view showing a repair circuit of a conventional semiconductor memory device.

2 illustrates a repair circuit of a semiconductor memory device according to an embodiment of the present invention.

[Description of Code for Major Parts of Drawing]

VCC: Power supply voltage N1, N2: Node

PM1 to PM3: first to third PMOS transistors

NM1 to NM3: first to third NMOS transistors

INV1 to INV3: first to third inverters

R1: resistance GND: ground

100: reference voltage generator 10: CMOS inverter circuit

The repair circuit of the semiconductor memory device according to the present invention for achieving the above object,

A switching element for supplying a power supply voltage to the first node by a switching operation;

A fuse connected between one terminal of the switching element and the first node to select a repair operation;

A first inverter for inverting and transmitting the signal of the first node to an output terminal;

An NMOS transistor for discharging a potential of the first node to a ground potential by a signal of the output terminal;

And a reference voltage generator configured to sense the power supply voltage to generate a signal for controlling the operation of the switching element at low voltage and to generate a signal to drive the switching element at high voltage.

Here, the switching element is a PMOS transistor.

The reference voltage generator includes a first PMOS transistor connected in a diode structure between the power supply voltage and the second node, a resistor connected between the second node and a ground voltage, and a PMOS input signal. And a CMOS inverter composed of NMOS transistors, and second and third inverters connected in series between an output node of the CMOS inverter and a gate of the switching element.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

FIG. 2 is a view showing a repair circuit of a semiconductor device according to an embodiment of the present invention, and the same reference numerals are assigned to the same components as in FIG.

As shown in FIG. 2, in the present invention, the first PMOS transistor PM1 is interposed between the fuse F1 and the power supply voltage VCC, and the first PMOS transistor PM1 is disposed at the gate of the first PMOS transistor PM1. Reference voltage generator 100 for controlling the output of the) is connected. In addition, an NMOS transistor NM1 is connected to the fuse F1 in series at the node N1, a first inverter INV1 is connected to the node N1, and an output terminal and a first NMOS of the first inverter INV1 are connected. The gate of the transistor NM1 is connected. In addition, the reference voltage generator 100 is connected to the power supply voltage VCC and its gate is connected to the source and the drain, respectively, and the node P2 is connected to the second PMOS transistor PM2. A CMOS inverter circuit 10 for inverting the output of the CMOS inverter circuit 10 and a resistor connected to the ground and grounded (GND) and a signal of the node N2 as an input and outputting an inverted signal. It consists of 2 inverters INV2 and 3rd inverters INV3 which invert the output of the 2nd inverter INV2 and input into the 1st PMOS transistor PM1. In addition, the CMOS inverter circuit 10 includes a third PMOS transistor PM3 connected to the power supply voltage VCC and a second NMOS transistor NM2 connected in series with the third PMOS transistor PM3. That is, the reference voltage generator 100 outputs a low signal or a high signal of a CMOS level based on a predetermined voltage when the power supply voltage VCC swings.

Next, the operation of the repair circuit described above will be described.

When the power supply voltage VCC is applied by the battery operation, current flows to the second PMOS transistor PM2 of the reference voltage generator 100, and a current path to the ground GND is generated through the resistor R1. At this time, the voltage level of the node N2 is determined by the ratio of the current supplied through the second PMOS transistor PM2 from the power supply voltage VCC and the current flowing through the resistor R1 to the ground GND. This voltage level becomes the threshold voltage of the third PMOS transistor PM3 and the second NMOS transistor NM2 of the CMOS inverter circuit 10. According to this threshold voltage, the output level of the CMOS inverter circuit 10 is determined to be a high or low signal, a reference voltage signal is output, and the output of the first PMOS transistor PM1 is controlled by this reference voltage signal. For example, when the reference voltage signal is low, the first PMOS transistor PM1 is turned on to supply the power supply voltage VCC to the fuse F1. When the reference voltage signal is high, the first PMOS transistor PM1 is turned off. It is turned off and the supply of the power supply voltage VCC to the fuse F1 is cut off. At this time, the voltage level blocked by the power supply voltage generator 100 is preferably secured to a level having a certain margin.

According to the present invention described above, the output of the PMOS transistor provided between the power supply voltage and the fuse is controlled according to the voltage level of the power supply voltage generator, so that the power supply voltage is supplied to the fuse or completely cut off. Accordingly, in the case of using the battery operating system, accurate repair signal output is possible even when incomplete fuse cutting is performed, thereby preventing malfunction of the memory device and improving repair yield.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (3)

A switching element for supplying a power supply voltage to the first node by a switching operation; A fuse connected between one terminal of the switching element and the first node to select a repair operation; A first inverter for inverting and transmitting the signal of the first node to an output terminal; An NMOS transistor for discharging a potential of the first node to a ground potential by a signal of the output terminal; And a reference voltage generator configured to sense the power supply voltage to generate a signal for controlling the operation of the switching element at low voltage and to generate a signal for driving the switching element at high voltage. The method of claim 1, The switching element is a repair circuit of a semiconductor memory device, characterized in that the PMOS transistor. The method of claim 1, wherein the reference voltage generator, A first PMOS transistor connected in a diode structure between the power supply voltage and the second node, a resistor connected between the second node and a ground voltage, and a PMOS and NMOS transistor configured to receive a signal of the second node; And a second inverter and a third inverter connected in series between a CMOS inverter and an output node of the CMOS inverter and a gate of the switching element.