KR100313882B1 - Skip macro block processor - Google Patents

Abstract

PURPOSE: A skip macro block processor is provided to compensate a skip macro block and to realize the continuous motions of a VLC(Variable Length Coding) decoder. CONSTITUTION: In an HDTV(High Definition Television) decoder, a VLD(Variable Length Decoding) unit comprises a VLC decoder(8) transmitting a bit stream by decoding, an mba(macro block address) decoder(9) predicting an mba, a parameter decoder(10) decoding a parameter, a coefficient decoder(11) decoding the run-level pair of a coefficient from the VLC decoder, a motion vector decoder(12) decoding a motion vector, a first, second, third, and fourth FIFO(First-In First-Out) corresponding to the decoders of mba, parameter, coefficient, and motion vector, an mba generator(13) generating an mba and deciding a skip macro block, a parameter generator(14) generating a parameter, a coefficient generator(15) generating a coefficient by reading the run-level pairs from the FIFO, and a motion vector generator(16) generating a motion vector.

Description

Skip Macro Block Processing Unit

1 is a block diagram of an HDTV decoder

2 is a detailed configuration diagram of the VLD unit of the present invention

3 is a detailed configuration diagram of the mba generator of the present invention

4 is a detailed configuration diagram of the parameter generator of the present invention

5 is a detailed configuration diagram of the coefficient generator of the present invention

6 is a detailed configuration diagram of the motion vector generator of the present invention

7 is a first operation explanatory diagram of the present invention

8 is an explanatory view of a second operation of the present invention.

* Explanation of symbols for main parts of the drawings

1: Video buffer 2: VLD part

3: inverse quantization unit 4: IDCT unit

5: motion compensator 6: adder

7: VDP section 8: VLC decoder

9: mba decoder 10: rapeta decoder

11: coefficient decoder 12 motion vector decoder

13: mba generator 14: parameter generator

15: coefficient generator 16: motion vector generator

17: counter 18: edge detector

19: default parameter generator 20: prebios parameter register

21,24: Mux 22: run-level decoder

23: Prebios motion vector register

The present invention relates to an HDTV decoder, and more particularly, to an apparatus for processing a skip macroblock that is suitable for determining and processing a skip macroblock using mba decoded in a variable length cording (VLC) decoder.

In general, an HDTV signal is a signal obtained by digitally compressing image data and uses a macroblock composed of 16 × 16 pixels (Pixel) as a basic compression unit.

Compression methods include DCT, quantization, VLC coding, and motion compensation between frames. Compresses the difference from the block whose motion is estimated in the previous frame of every macroblock. Sent with a Motion Vector.

If there is no data to be sent to any macroblock, or if it is predictable, that is, if the difference is zero, the motion vector is zero, or matches the value of the previous macroblock, then it is treated as a skip macroblock and no data is sent for that macroblock. .

The decision of the skip macroblock in the decoder is to decode the macroblock address increment (mba) sent at the beginning of each macroblock and to skip the macroblock corresponding to the mba that does not appear when the mba is predicted. In this case, the VLC (Variable Length Code) decoder pauses the operation to process the skip macroblock.

Accordingly, an object of the present invention is to provide a skip macroblock processing apparatus capable of determining and supplementing the skip macroblock and enabling continuous operation of a VLC decoder.

In order to achieve the above object, a skip macroblock processing apparatus according to the present invention includes a video buffer for storing a bitstream, a VLD unit for interpreting the bitstream, an inverse quantizer for dequantizing an output signal of the VLD unit, and an inverse quantization. An IDCT unit for IDCT processing the received signal, a motion compensation unit for compensating for motion using the motion information output from the VLD, and an HDTV decoder for adding the output signals of the IDCT and the motion floating unit to output to the VDP; The VLD section includes a VLC decoder for decoding the bitstream, an mba decoder for predicting mba from the output of the VLC decoder, a parameter decoder for decoding parameters from the output of the VLC decoder, and a run-level from the output of the VLC decoder. A coefficient decoder for decoding the pair, a motion vector decoder for decoding the motion vector from the output of the VLC decoder, and the mba, First, second, third, fourth, and FIFOs corresponding to the parameter, the coefficient, and the motion vector decoder, an mba generator for generating mba and determining a skipped macroblock in response to the first FIFO, and the second A parameter generator for generating parameters in response to a FIFO, a coefficient generator for reading run-level pairs in response to the third FIFO and generating coefficients, and a motion vector generation for generating a motion vector in response to the fourth FIFO It is characterized by consisting of wealth.

Hereinafter, with reference to the accompanying drawings as follows.

1 is a block diagram of an HDTV decoder, in which 1 is a video buffer unit, 2 is a variable length decoding (VLD) unit, 3 is an inverse quantization unit (Q- ¹ ), and 4 is an inverse discreate. Cosine Transfom), 5 is a Motion Compensation unit, 6 is an adder, and 7 is a VDP (Video Display Processor) unit.

As shown, the video buffer unit 1 stores the input bitstream and the stored bitstream is interpreted by the VLD 2 and dequantized by the dequantizer 3.

In addition, the dequantized signal is IDCT in the IDCT unit 4, and the motion compensator 5 compensates for the motion by using the motion information of the VLD 2, and the adder 6 moves with the IDCT unit 4. The signal output from the compensator 5 is added and output to the VDP 7.

Subsequently, the determination and processing of the skip macroblock will be described with reference to the detailed configuration diagram of the VLD unit of FIG. 2.

The VLD unit 2 of the present invention is a VLC decoder 8 which decodes the bitstream read from the video buffer unit 1 and delivers the code to the next decoder, an mba decoder 9 which predicts mba, and a parameter. A parameter decoder 10 for decoding the N s), a coefficient decoder 11 for decoding a run-level pair of coefficients from the VLC decoder, and a motion vector decoder 12 for decoding the motion vector. And mba for generating and skipping each FIFO that sequentially inputs and outputs the mba, the parameters, the coefficients, and the motion vector decoders 13, 14, and 15, respectively, and determines the skipped macroblock. A generator 13, a parameter generator 14 for generating parameters, a coefficient generator 15 for generating coefficients by reading run-level pairs from the FIFO, and a motion for generating a motion vector. It consists of a vector generator 16.

As a description of the above configuration, the write enable signals we1, we2, and we3 of each FIFO are generated in each decoder, and mba and parameter values having one information for each macroblock are written at the end of each macroblock. We2 and we3 are generated so that run-level pairs and motion vectors of coefficients written by we1, which are written by we1 and whose number of decodes are not constant per macroblock, are written each time each value is decoded.

The mba and parameters written to the FIFO are read by re1, which is a read enable signal generated by the mba generator 13 and the parameter generator 14, and the run-level value and the motion vector value of the coefficient are respectively. Read by the coefficient generator 15 and re2 and re3 generated by the motion vector generator 16, the skip-flag generated in the mba generator 13 is the parameter generator 14 ), The coefficient generator 15, and the motion vector generator 16, respectively.

In addition, the mba generator 13 will be described with reference to the detailed configuration diagram of the mba generator of FIG. 3 as follows.

The mba generator 13 of the present invention includes a counter 17 for generating a macroblock address as a count output, an edge detector 18 for the macroblock, an Ex-OR gate, a Not gate, and an AND. It consists of a gate.

Accordingly, the counter 17 is reset to 0 by the reset signal generated at the slice start and then counted up by the macroblock clock to sequentially 0, 1, 2, 3,... Raises the

In addition, when the edge detector 18 generates a re1 at the rising edge, the read mba is Ex-ORed with the output of the counter 17 so that the skip-flag becomes zero if it is the same value. If the value is different, it becomes 1 to determine whether the skip macro block is present or not.

Re1 generates re1 only when the skip-flag is 0 at the first clock of the macroblock and prohibits the occurrence of re1 when it is 1.

In addition, the parameter generating unit 14 for generating the parameters of the macroblock will be described with reference to the detailed configuration diagram of the parameter generating unit of the present invention as shown in FIG.

The parameter generator according to the present invention has a default parameter generator 19 in which the current picture structure is set differently according to a frame or a field, and the parameters of the previous macroblock. It consists of a previous parameter register (20) and the MUX (21) storing the.

In the description according to the configuration, if the skip-flag provided by the mba generator 13 is 0, the parameter output from the FIFO is output as it is to D ₂ of the MUX 21, but the skip-flag becomes 1 and the skip macroblock When the picture coding type is P frame, P / B = 1 and D ₀ of the MUX 21 is selected to maintain the default parameter, and picture coding type. In this B frame, P / B = 0, indicating that D ₁ of the MUX 21 is selected to maintain the parameter value of the previous macro block.

Next, FIG. 5 is a detailed configuration diagram of the coefficient generator of the present invention. The coefficient generator 15 of the present invention includes a run-level decoder 22 that decodes run-level, a NOT gate, and an AND gate. According to the operation, the run-level decoder 22 decodes the run-level, converts it into a coefficient, and outputs the coefficient. A skip-flag value of 1 output from the mba generator 13 is forced by the NOT gate and the AND gate. 0 is outputted and re3 is prohibited and is not output from FIFO.

6 is a detailed configuration diagram of the motion vector generator of the present invention, which is composed of a previos motion vector register 23 and a MUX 24 that store motion vectors of a previous macro block. -If the flag is 0, the motion vector output from the FIFO is output as D ₂ of MUX (24). However, when the skip flag is 1 and it is skip macro block, it is processed differently according to the picture coding type. D ₀ of the MUX 24 is selected to maintain a motion vector of P / B = 1 and 0, and if it is a B frame, P / B = 0 to maintain a previous motion vector D ₁ of MUX 24. To indicate that it is selected.

The following is a description with reference to the seventh and eighth roads as the processing example of the circuit configuration diagram of the present invention described above.

7 is a diagram illustrating the first operation of the present invention, and FIG. 8 is a diagram illustrating the second operation of the present invention.

First, as shown in FIG. 7, data values stored in the mba FIFO for one slice are 0, 1, 3, 4, 7, 8, ..., n-1, 0, 1, 2, 2, 5, Macroblocks with an mba data value of 6 are not decoded to become skip macroblocks.

Therefore, mba data values of 0, 1, and 2 are stored instead of 2, 3, and 6.

8 is a diagram illustrating a second operation of the present invention. A method of processing a skip macroblock will now be described with reference to a timing diagram.

As shown, the counter 17 is reset to 0 by the slice clock, and the rising edge of the edge detector 18 generates re1 to read mba and parameters of the first macro block. Lose.

The zero block value of the counter 17 and the zero value of the mba data read from the FIFO are Ex-ORed to output a skip flag of zero.

At this time, the parameter generator 14 outputs the parameters read from the FIFO as it is, the coefficient generator 15 also reads run-level pairs and outputs them as coefficients, and the motion vector generator 16 also refers to the parameters and includes a macro with motion vectors. Read and output the motion vector for the block.

Next, in the second macroblock, the counter 17 becomes 1 and generates re1 at the rising edge of the edge detector 18 to read the second mba and the parameters, and the skip-flag is set to 1 and 1 of the counter 17. A skip-flag of 0 is output by E-ORing 1 value of mba data.

The parameters, coefficients, and motion vector generators 14, 15 and 16 are also output in the same process as the first.

However, in the third macroblock, the counter 17 becomes 2, generates er1 in the rising of the edge detector 18, reads 3, the value of the third mba, and outputs a skip-flag of 1.

Therefore, the parameter outputs the value of the default parameter generator 19 when P / B = 1, and outputs the value of the pre-bis parameter register 20 when P / B = 0.

And since the skip flag is 1, 0 is selected and output, and re3 is prohibited.

The motion vector also has an output of 0 when P / B = 1 and an output of the pre-vis motion vector register 23 when P / B = 0.

In the fourth macroblock, the counter 17 becomes 3, and in the third macroblock, the skip-flag is zero because the rising edge of the edge detector 18 generates re1 and maintains 3 of the mba value until the fourth macroblock. Become.

Accordingly, the parameters, coefficients, and motion vector generators 14, 15, and 16 are output in the same process as in the first, and the following cases (fifth, sixth, ...) proceed in the same manner as above.

The skip macroblock processing apparatus of the present invention described above has the effect of determining and supplementing the skip macroblock while allowing the continuous operation of the VLC decoder.

Claims (5)

A video buffer for storing the bitstream, a VLC unit for interpreting the bitstream, an inverse quantizer for inverse quantization of the output signal of the VLD unit, an IDCT unit for IDCT processing the inverse quantized signal, and an output from the VLD A motion compensator for compensating motion by using motion information, and an HDTV decoder for adding output signals of the IDCT unit and the motion floating unit to a VDP unit, wherein the VLD unit is a VLC decoder for decoding a bitstream and a VLC decoder. An mba decoder that predicts mba from its output, a parameter decoder that decodes parameters from the output of the VLC decoder, a coefficient decoder that decodes run-level pairs from the output of the VLC decoder, and motion from the output of the VLC decoder A motion vector decoder for decoding a vector, and first, second, third, and corresponding mba, parameters, coefficients, and the motion vector decoder, respectively. A FIFO, an mba generator for generating mba in response to the first FIFO and determining a skip macroblock, a parameter generator for generating a parameter in response to the second FIFO, and a run in response to the third FIFO And a coefficient generator which reads a level pair and generates coefficients, and a motion vector generator that generates a motion vector in response to the fourth FIFO. The skip macro of claim 1, wherein the mba generating unit compares a counter value of a counter that starts counting after being set to zero by a reset signal generated at a slice start and an mba value read from the first FIFO by a read enable signal. A skip macro block processing apparatus for generating a skip-flag determined as a block and outputting a skip-flag to the parameter, coefficient, and motion vector generator. The method of claim 1, wherein the parameter generator outputs a default parameter when the picture coding type is P frame when the skip flag is determined to be a skip macro block, and outputs a parameter of the previous macro block when the picture coding type is B frame. The skip macro flag processing unit is characterized in that the output of the parameter output of the FIFO as it is. The method of claim 1, wherein the coefficient generator decodes a run-level pair into a coefficient and does not output a coefficient because the run flag of the FIFO is not input when a skip flag determined by a skip macroblock is applied. A skip macroblock processing apparatus characterized in that. According to claim 1, wherein the motion vector generator outputs a motion vector of 0 when the picture coding type is P frame when the skip-flag determined by the mba generator as a skip macroblock is applied, and when the frame is B frame, (Previous) The skip macroblock processing apparatus outputs the motion vector of the macroblock and outputs the motion vector output of the FIFO as it is if the skip flag is not applied.