KR100313602B1 - An Electro Static Chuck - Google Patents
An Electro Static Chuck Download PDFInfo
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- KR100313602B1 KR100313602B1 KR1019990009019A KR19990009019A KR100313602B1 KR 100313602 B1 KR100313602 B1 KR 100313602B1 KR 1019990009019 A KR1019990009019 A KR 1019990009019A KR 19990009019 A KR19990009019 A KR 19990009019A KR 100313602 B1 KR100313602 B1 KR 100313602B1
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- wafer
- switches
- switch
- voltage
- electrostatic chuck
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- 230000003068 static effect Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000007599 discharging Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 41
- 239000010408 film Substances 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
본 발명은 반도체 제조용 정전척에 관한 것으로써, 종래에는 플라즈마 상태의 공정쳄버내에서 웨이퍼상에 소정의 공정이 진행될 때 웨이퍼에 일정량의 전압이 충전되어 리프트 핀과 서로 접촉되면서 전위차에 의한 불꽃 방전이 발생되는 문제점이 있었던 바, 플라즈마 상태의 공정쳄버 내에 위치되며, 리프트 핀의 구동에 의해 웨이퍼가 안착되거나 탈착되는 반도체 제조용 정전척에 있어서, 상기 리프트 핀에 전위차 감쇠수단을 더 구비하여, 상기 웨이퍼와 리프트 핀이 서로 접촉될 때, 상기 웨이퍼에 충전되어 있는 잔류전압이 상기 전위차 감쇠수단에 의해 순차적으로 제거되도록 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic chuck for semiconductor manufacturing. In the related art, when a predetermined process is performed on a wafer in a plasma process chamber, a predetermined amount of voltage is charged to the wafer to contact the lift pins, thereby preventing spark discharges caused by a potential difference. In the electrostatic chuck for semiconductor manufacturing, which is located in a process chamber in a plasma state, in which a wafer is seated or detached by driving a lift pin, the lift pin further includes a potential difference attenuation means. When the lift pins are in contact with each other, the residual voltage charged in the wafer is sequentially removed by the potential difference attenuation means.
따라서, 웨이퍼의 잔류전압 방전이 순차적으로 진행됨으로써, 리프트 핀과 웨이퍼의 접촉시 불꽃 방전발생을 방지하여 반도체 소자의 손상이 방지되며, 방전을 위한 별도의 공정단계가 필요하지 않게 되어 반도체 소자 생산효율이 증대되는 효과가 있다.Therefore, since the residual voltage discharge of the wafer proceeds sequentially, damage of the semiconductor device is prevented by preventing spark discharge when the lift pin and the wafer contact each other, and a separate process step for discharging is not required. This has the effect of increasing.
Description
본 발명은 반도체 제조용 정전척(Electro Static Chuck: ESC)에 관한 것으로써, 특히, 플라즈마 상태의 공정쳄버 내에서 공정이 진행되면서 웨이퍼에 충전된 잔류전압을 순차적으로 감쇠시키는 반도체 제조용 정전척에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic chuck (ESC) for semiconductor manufacturing, and more particularly to an electrostatic chuck for semiconductor manufacturing which sequentially attenuates the residual voltage charged to a wafer while the process is performed in a plasma process chamber. .
종래의 반도체 제조용 정전척은 제 1 도에 도시된 바와 같이, 플라즈마 상태의 공정쳄버(18)내에 고주파 전원에 연결된 상부전극(11) 및 하부전극(12) 사이에 위치되고, 정전기력에 의해 웨이퍼(13)를 고정시킨다.The conventional electrostatic chuck for semiconductor manufacturing is located between the upper electrode 11 and the lower electrode 12 connected to the high frequency power source in the process chamber 18 of the plasma state, as shown in FIG. 13).
상부전극 및 하부전극 사이에 위치된 정전척(10)은 절연막(15)에 의해 웨이퍼(13)와는 서로 절연된 상태를 유지하며, 웨이퍼를 안착시키거나, 반송시킬 때 업/다운(up/down)구동되어 웨이퍼를 안착 또는 탈착시키는 리프트 핀(lift-pin)(16)이 있다. 그리고, 리프트 핀(16)은 접지단자에 접지 되어 있다.The electrostatic chuck 10 positioned between the upper electrode and the lower electrode is kept insulated from the wafer 13 by the insulating film 15, and is up / down when the wafer is seated or conveyed. There is a lift-pin 16 which is driven to seat or detach the wafer. The lift pin 16 is grounded to the ground terminal.
이러한 반도체 제조용 정전척(10)은 웨이퍼(13)가 미도시된 이송수단에 의해 공정쳄버(18)내로 이송되면, 리프트 핀(16)이 상,하방향으로 구동하여 웨이퍼를 안착시켜 정전기력에 의해 고정시킨다.In the electrostatic chuck 10 for manufacturing a semiconductor, when the wafer 13 is transferred into the process chamber 18 by a transfer means (not shown), the lift pins 16 are driven up and down to seat the wafer, and the electrostatic force is applied by the electrostatic force. Fix it.
웨이퍼(13)가 고정되면 상,하부 전극(11,12)으로 고주파 전원이 인가되고, 공정가스가 공급되어 플라즈마를 생성시켜 소정의 공정이 웨이퍼 상에 진행된다.When the wafer 13 is fixed, high frequency power is applied to the upper and lower electrodes 11 and 12, a process gas is supplied to generate a plasma, and a predetermined process is performed on the wafer.
웨이퍼(13)상에 소정의 공정이 완료되면, 리프트 핀(16)이 웨이퍼(13)를 정전척(10)에서 탈착시켜 웨이퍼가 반송되게 한다.When the predetermined process is completed on the wafer 13, the lift pin 16 detaches the wafer 13 from the electrostatic chuck 10 so that the wafer is conveyed.
그러나, 플라즈마 상태에서 소정의 공정 진행시 정전척의 정전기력이 해제되면, 웨이퍼에는 축적된 전하가 남게 되어 접지단자 대비 수 내지 수십 볼트의 전위차를갖는 잔류전압을 가지게 된다.However, when the electrostatic force of the electrostatic chuck is released during a predetermined process in the plasma state, the accumulated charge remains on the wafer and thus has a residual voltage having a potential difference of several to several tens of volts with respect to the ground terminal.
따라서, 접지단자 대비 수 내지 수십 볼트 전위차를 갖는 잔류전압이 형성된 웨이퍼를 탈착시키고자 접지단자에 접지된 리프트 핀이 서로 접촉하게 되면, 접촉점에서 전위차에 의해 순간적인 불꽃 방전(arc)이 발생되어 반도체 소자의 손상을 입히게 되는 문제점이 있다.Therefore, when lift pins grounded on the ground terminal come into contact with each other to remove the wafer having a residual voltage having a potential difference of several to several tens of volts from the ground terminal, an instantaneous spark discharge (arc) is generated by the potential difference at the contact point. There is a problem that damages the device.
그리고, 이러한 전압차를 감소시키기 위해 별도로 He 등의 가스를 공정쳄버 내로 공급하여 자연 방전시키는 방법이 있으나, 이는 공정진행 과정이 복잡하고, 자연방전에 소요되는 공정시간이 많이 걸리게 되어 단위시간당 반도체 소자 생산효율이 저하되는 문제점이 있다.In addition, in order to reduce the voltage difference, there is a method of separately supplying a gas such as He into the process chamber and naturally discharging it. However, the process progress is complicated and the process time required for the natural discharge takes a lot, and thus the semiconductor device per unit time. There is a problem that the production efficiency is lowered.
이에 본 발명은 웨이퍼와 리프트 핀과의 접촉시 웨이퍼에 충전된 잔류전압을 순차적으로 방전시켜 불꽃 방전(arc) 발생을 제거하며, 반도체 소자의 생산효율이 증대되는 반도체 제조용 정전척을 제공하고자 한다.Accordingly, an embodiment of the present invention is to provide an electrostatic chuck for manufacturing a semiconductor in which a residual voltage charged in a wafer is sequentially discharged upon contact between a wafer and a lift pin to remove spark discharges, and the production efficiency of the semiconductor device is increased.
따라서, 상기 목적을 달성하고자, 플라즈마 상태의 공정쳄버내에 위치되며, 리프트 핀의 구동에 의해 웨이퍼가 안착되거나 탈착되는 반도체 제조용 정전척에 있어서, 상기 리프트 핀에 전위차 감쇠수단을 더 구비하여, 상기 웨이퍼와 리프트 핀이 서로 접촉될 때, 상기 웨이퍼에 충전되어 있는 잔류전압이 상기 전위차 감쇠수단에 의해 제거되도록 한다.Therefore, in order to achieve the above object, in the electrostatic chuck for semiconductor manufacturing, which is located in a process chamber in a plasma state, in which a wafer is seated or detached by driving a lift pin, the lift pin further includes a potential difference attenuation means. When and the lift pins are in contact with each other, the residual voltage charged in the wafer is removed by the potential difference attenuation means.
여기서, 감쇠수단은 리프트 핀에 연결되는 제 1 스위치와, 제 1 스위치에 직렬로 연결되며, 제어수단에 의해 제 1 스위치와 동시에 온/오프 동작되는 다수개의 제 2스위치와, 상기 다수개의 제 2 스위치와 각각 직렬로 연결되며, 상기 제어수단에 의해 온/오프 동작하되, 상기 제 1 및 제 2 스위치의 온/오프와 반대로 상기 제어수단에 의해 온/오프 되는 다수개의 제 3 스위치와, 다수개의 제 3 스위치와 접지단자 사이에 각각 연결되며, 제 3 스위치가 온 상태일 때 외부로부터 소정의 전압을 공급받는 다수개의 커패시터와, 다수개의 제 2 스위치와 접지단자 사이에 연결되며, 커패시터에 대해 병렬로 연결된 저항으로 이루어진다.Here, the attenuation means is a first switch connected to the lift pin, a plurality of second switches connected in series to the first switch, the on and off operation simultaneously with the first switch by the control means, and the plurality of second A plurality of third switches connected in series with the switches, each of which is turned on / off by the control means and is turned on / off by the control means as opposed to the on / off of the first and second switches; Respectively connected between the third switch and the ground terminal, and connected between the plurality of capacitors receiving a predetermined voltage from the outside when the third switch is turned on, and the plurality of second switches and the ground terminal, It consists of a resistor connected to
또한, 다수개의 커패시터로 공급되는 전압은 순차적으로 일정한 전압차이를 갖도록 공급되며, 최대값은 웨이퍼의 잔류전압과 동일한 값을 갖도록 한다.In addition, the voltage supplied to the plurality of capacitors is sequentially supplied to have a constant voltage difference, and the maximum value is to have the same value as the residual voltage of the wafer.
제 1 도는 종래의 반도체 제조용 정전척을 설명하기 위한 도면이고,1 is a view for explaining a conventional electrostatic chuck for semiconductor manufacturing,
제 2 도는 전위차 감쇠수단이 장착되어 웨이퍼의 잔류전압이 순차적으로 감쇠되는 본 발명인 반도체 제조용 정전척을 설명하기 위한 도면이고,2 is a view for explaining an electrostatic chuck for manufacturing a semiconductor according to the present invention in which the potential difference attenuation means is mounted so that the residual voltage of the wafer is sequentially attenuated.
제 3 도는 본 발명인 반도체 제조용 정전척의 전위차 감쇠수단을 설명하기 위한 도면이다.3 is a view for explaining the potential difference attenuation means of the electrostatic chuck for semiconductor manufacture according to the present invention.
< 도면의 주요부분에 대한 간략한 부호설명 ><Brief description of the main parts of the drawings>
10,100 : 정전척 11,12 : 전극10,100: electrostatic chuck 11,12: electrode
13 : 웨이퍼 14 : 고주파 전원13: wafer 14: high frequency power supply
15 : 절연막 16,101 : 리프트 핀15: insulating film 16,101: lift pin
17 : 공정쳄버17: process chamber
102 : 전위차 감쇠부102: potential difference attenuation unit
C 1 내지 C 4: 커패시터 S1,S2,S3 : 스위치C 1 to C 4: Capacitors S1, S2, S3: Switch
R : 저항R: resistance
이하, 첨부된 도면을 참조하여 본 발명인 반도체 제조용 정전척에 대한 바람직한 일실시 예를 설명하면 다음과 같다.Hereinafter, a preferred embodiment of an electrostatic chuck for semiconductor manufacturing according to the present invention will be described with reference to the accompanying drawings.
제 2 도는 웨이퍼에 충전된 잔류전압이 제거되는 본 발명인 반도체 제조용 정전척을 설명하기 위한 도면으로, 본 발명인 반도체 제조용 정전척(100)은 플라즈마 상태의 공정쳄버(17)내 상부 및 하부 전극(11,12)사이에 설치되고, 웨이퍼(13)를 정전기력에 의해 고정시켜 박막의 증착 또는 식각 등의 공정이 진행되게 한다.2 is a view for explaining an electrostatic chuck for semiconductor manufacturing according to the present invention, in which residual voltage charged on a wafer is removed, and the electrostatic chuck 100 for semiconductor manufacturing according to the present invention includes upper and lower electrodes 11 in a process chamber 17 in a plasma state. , 12), and the wafer 13 is fixed by electrostatic force to allow a process such as deposition or etching of a thin film to proceed.
상부 전극 및 하부 전극(11,12) 사이에 위치된 정전척(100)은 절연막(15)에 의해 웨이퍼(13)와는 서로 절연된 상태를 유지하며, 웨이퍼(13)의 안착 또는 반송시 웨이퍼를 정전척에서 들어올리는 리프트 핀(101)이 있다.The electrostatic chuck 100 positioned between the upper electrode and the lower electrode 11, 12 is insulated from the wafer 13 by the insulating film 15, and the wafer is held when the wafer 13 is seated or conveyed. There is a lift pin 101 that lifts from the electrostatic chuck.
리프트 핀(101)은 웨이퍼의 전위차를 순차적으로 감쇠시키기 위한 전위차 감쇠수단(102)이 구비된다.The lift pin 101 is provided with potential difference attenuation means 102 for sequentially attenuating the potential difference of the wafer.
리프트 핀에 구비되는 전위차 감쇠수단(102)은 다수개의 스위치(S1,S2,S3)와, 커패시터(C1 내지 C4) 및 저항(R)을 사용하여 웨이퍼(13)의 잔류전압을 순차적으로 감쇠시키도록 구성한 것이다.The potential difference attenuation means 102 provided in the lift pin sequentially attenuates the residual voltage of the wafer 13 using a plurality of switches S1, S2, S3, capacitors C1 to C4, and a resistor R. It is configured to be.
제 3 도는 전위차 감쇠수단(102)을 설명하기 위한 회로도로써, 전위차 감쇠수단(102)은 리프트 핀(101)에 연결되는 제 1 스위치(S1)와, 제 1 스위치에 직렬로 연결되며, 제 1 스위치(S1)와 동시에 온/오프 동작되는 다수개의 제 2 스위치(S2)와, 다수개의 제 2 스위치와 각각 직렬로 연결되며, 제 1 및 제 2 스위치(S1,S2)와 반대로 온/오프 되는 다수개의 제 3 스위치(S3)와, 다수개의 제 3 스위치와 접지단자 사이에 각각 연결되며, 제 3 스위치(S3)가 온 상태일 때 외부로부터 소정의 전압을 공급받는 다수개의 커패시터(C1 내지 C4)와, 다수개의 제 2 스위치(S2)와 접지단자 사이에 연결되며, 커패시터(C1 내지 C4)에 대해 병렬로 연결된 저항(R)으로 이루어지도록 하면 된다.3 is a circuit diagram for explaining the potential difference attenuation means 102. The potential difference attenuation means 102 is connected to the first switch S1 connected to the lift pin 101, and is connected in series to the first switch. A plurality of second switches S2 that are simultaneously turned on and off simultaneously with the switch S1, and are connected in series with the plurality of second switches, respectively, and are turned on and off opposite to the first and second switches S1 and S2. A plurality of capacitors C1 to C4 that are connected between the plurality of third switches S3 and the plurality of third switches and the ground terminals, respectively, and receive a predetermined voltage from the outside when the third switch S3 is turned on. ) And a plurality of second switches S2 and a ground terminal, and a resistor R connected in parallel to the capacitors C1 to C4.
여기서, 제 1 스위치(S1), 제 2 스위치(S2), 제 3 스위치(S3)는 외부의 제어수단에 의해 온/오프가 제어되도록 한다.Here, the first switch (S1), the second switch (S2), the third switch (S3) to be controlled on / off by an external control means.
그리고, 제 3 스위치(S3)가 온 상태일 때 외부로부터 다수개의 커패시터(C1 내지 C4)로 공급되는 전압은 동일한 전압으로 공급시키지 않고, 일정한 전압차이를 두고 순차적으로 공급시키도록 한다.When the third switch S3 is in the on state, the voltages supplied to the plurality of capacitors C1 to C4 from the outside are not supplied at the same voltage, but are sequentially supplied with a constant voltage difference.
여기서, 커패시터(C1 내지 C4)에 공급되는 전압의 최대 전압값은 웨이퍼의 잔류전압과 동일한 값으로 하고, 0.5 볼트 또는 1 볼트 단위로 전압차이를 갖게 공급하는 것이 바람직하다.Here, the maximum voltage value of the voltages supplied to the capacitors C1 to C4 is set to the same value as the residual voltage of the wafer, and is preferably supplied with a voltage difference in units of 0.5 volts or 1 volt.
즉, 커패시터(C1)에는 웨이퍼의 잔류전압과 동일한 값을 갖는 최대 전압이 충전되고, 커패시터(C2,C3)에는 최대 전압값에서 0.5 볼트 또는 1 볼트의 전압차이를 갖는 전압이 순차적으로 충전된다. 따라서, 커패시터(C4)에는 가장 낮은 최소 전압값을 갖게 된다.That is, the capacitor C1 is charged with a maximum voltage having the same value as the residual voltage of the wafer, and the capacitors C2 and C3 are sequentially charged with a voltage having a voltage difference of 0.5 volt or 1 volt at the maximum voltage value. Therefore, the capacitor C4 has the lowest minimum voltage value.
이러한 구성으로 이루어진 본 발명인 반도체 제조용 정전척(100)은 소정의 공정이 완료된 웨이퍼(13)를 탈착시키고자, 리프트 핀(101)이 웨이퍼(13)를 들어올릴 때, 접지단자 대비 수 내지 수십 볼트 전위차의 잔류전압을 갖는 웨이퍼(13)가 커패시터(C1 내지 C4)에 의해 순차적으로 잔류전압을 방전하게 된다.The electrostatic chuck 100 for semiconductor manufacturing according to the present invention having such a configuration may have several to several tens of volts compared to the ground terminal when the lift pin 101 lifts the wafer 13 to detach and remove the wafer 13 having a predetermined process. The wafer 13 having the residual voltage of the potential difference discharges the residual voltage sequentially by the capacitors C1 to C4.
즉, 웨이퍼(13)가 정전기력에 의해 정전척(100)에 고정된 상태에서 소정의 공정이 진행될 때, 다수개의 제 3 스위치(S3)는 별도의 제어부에 의해 온 상태가 되어 외부로부터 소정의 전압이 다수개의 커패시터(C1 내지 C4)에 각각 최대 전압부터 최소전압까지 일정한 전압차이를 갖도록 충전된다.That is, when a predetermined process is performed while the wafer 13 is fixed to the electrostatic chuck 100 by the electrostatic force, the plurality of third switches S3 are turned on by a separate control unit so that a predetermined voltage is received from the outside. Each of these capacitors C1 to C4 is charged to have a constant voltage difference from the maximum voltage to the minimum voltage.
이와 같이 커패시터(C1 내지 C4)에 일정한 전압차를 갖게 각각 충전된 상태에서 웨이퍼(13)에 공정이 완료되어 웨이퍼(13)를 탈착시키고자, 리프트 핀(101)이 상승하여 웨이퍼와 서로 접촉하게 된다.As described above, the process is completed on the wafer 13 in the state where the capacitors C1 to C4 have a constant voltage difference, and the lift pins 101 are raised to contact the wafers. do.
이때, 별도의 제어부는 제 1 및 제 2 스위치(S1,S2)를 온 상태가 되게 하고, 제 3 스위치(S3)는 오프 상태로 되도록 하여 웨이퍼(13)의 잔류전압이 리프트 핀(101)을 거쳐 방전되게 한다.At this time, the separate control unit turns on the first and second switches S1 and S2 and turns off the third switch S3 so that the residual voltage of the wafer 13 causes the lift pins 101 to rise. Allow discharge through.
제 1 및 제 2 스위치(S1, S2)가 온 상태로 되면, 접지단자 대비 수 내지 수십 볼트의 전위차의 잔류전압은 갖는 웨이퍼(13)는 방전이 순차적으로 진행되는데, 다수개로 이루어지며, 0.5 볼트 또는 1 볼트의 전압차이로 미리 각각 충전된 커패시터(C1 내지 C4)의 전압차이에 의해 순차적인 방전이 진행되고, 저항(R)을 거치면서 최종적으로는 방전이 진행되면서 접지단자에 단락되어 방전이 완료된다.When the first and second switches S1 and S2 are turned on, the discharge of the wafer 13 having a residual voltage having a potential difference of several to several tens of volts compared to the ground terminal proceeds sequentially, and is made of a plurality of 0.5 volts. Alternatively, the sequential discharge proceeds according to the voltage difference of the capacitors C1 to C4 precharged with the voltage difference of 1 volt, and the discharge is short-circuited to the ground terminal as the discharge progresses through the resistor R. Is done.
상기에서 상술한 바와 같이, 본 발명인 반도체 제조용 정전척은 순차적으로 웨이퍼의 방전이 진행됨으로써 급격한 웨이퍼 방전에 의한 불꽃 방전이 발생되지 않게 되어 반도체 소자의 손상을 방지할 뿐만 아니라, 웨이퍼 방전을 위해 실시되는 He 가스공급에 의해 자연적인 방전 공정 단계가 필요없게 되어 단위시간당 공정시간이 단축되어 웨이퍼 생산효율이 증대되는데 이점이 있다.As described above, the electrostatic chuck for semiconductor manufacturing according to the present invention sequentially discharges the wafer so that spark discharge due to abrupt wafer discharge does not occur, thereby preventing damage to the semiconductor element and performing wafer discharge. The supply of He gas eliminates the need for a natural discharge process step, which shortens the process time per unit time, thereby increasing wafer production efficiency.
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| KR1019990009019A KR100313602B1 (en) | 1999-03-17 | 1999-03-17 | An Electro Static Chuck |
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| KR980003069A (en) * | 1996-06-15 | 1998-03-30 | 박병재 | Position and key lock switch of gear shift lever for automatic transmission |
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