KR100309475B1 - Semiconductor memory - Google Patents
Semiconductor memory Download PDFInfo
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- KR100309475B1 KR100309475B1 KR1019990058246A KR19990058246A KR100309475B1 KR 100309475 B1 KR100309475 B1 KR 100309475B1 KR 1019990058246 A KR1019990058246 A KR 1019990058246A KR 19990058246 A KR19990058246 A KR 19990058246A KR 100309475 B1 KR100309475 B1 KR 100309475B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000002093 peripheral effect Effects 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000015654 memory Effects 0.000 claims abstract description 17
- 238000009825 accumulation Methods 0.000 claims abstract description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract 1
- 230000000593 degrading effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
Abstract
본 발명은 반도체 메모리에 관한 것으로, 종래 반도체 메모리는 셀영역과 주변회로영역에 위치하는 피웰에 서로다른 값의 전압을 인가하기 위해 두 피웰영역의 사이에 딥엔웰을 형성하여 반도체 메모리의 집적도가 저하됨과 아울러 셀영역 피웰에 -1V의 저전압을 인가하여 커패시터와의 전압차가 커져, 전계가 강해짐으로써, 커패시터 노드에서의 누설전류가 발생하는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판의 각영역에 복수의 피웰 및 엔웰을 위치시키고, 그 복수의 피웰중 선택된 피웰 상에 위치하며 셀트랜지스터와 커패시터를 포함하는 메모리셀과; 상기 메모리셀이 위치하지 않은 나머지 피웰상에 위치하는 주변회로중 엔모스 트랜지스터와; 상기 엔웰 상에 위치하는 주변회로중 피모스 트랜지스터를 포함하는 반도체 메모리에 있어서, 상기 복수의 피웰 전체에는 접지전압을 인가함과 아울러 상기 셀트랜지스터의 오프시 게이트전압을 -1V로 하여, 그 셀트랜지스터의 오프시 채널영역이 축적모드에 있도록 하여, 채널영역의 상부표면에서 발생하는 누설전류의 발생을 방지하고, 커패시터의 하부전극과 기판전압의 전압차를 줄여 그 커패시터의 노드에서 발생하는 누설전류의 양을 감소시켜 메모리셀의 리프레시 특성을 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory. In the conventional semiconductor memory, a deep enwell is formed between two pewell regions in order to apply different voltages to the pewells located in the cell region and the peripheral circuit region, thereby decreasing the integration degree of the semiconductor memory. In addition, a low voltage of −1 V is applied to the cell region pewell to increase the voltage difference with the capacitor, thereby increasing the electric field, thereby causing a leakage current at the capacitor node. In view of the above problems, the present invention provides a memory device comprising: a memory cell including a plurality of pewells and enwells in each region of a substrate, the plurality of pewells being positioned on a selected pewell among the plurality of pewells, and including a cell transistor and a capacitor; An NMOS transistor among peripheral circuits positioned on the remaining pewells in which the memory cell is not located; A semiconductor memory including a PMOS transistor among peripheral circuits located on the enwell, wherein a ground voltage is applied to all of the plurality of pwells, and a gate voltage of -1V when the cell transistor is turned off is set. When the channel is off, the channel region is in the accumulation mode to prevent leakage current occurring at the upper surface of the channel region, and the voltage difference between the lower electrode of the capacitor and the substrate voltage is reduced to reduce the leakage current generated at the node of the capacitor. There is an effect of reducing the amount to improve the refresh characteristics of the memory cell.
Description
본 발명은 반도체 메모리에 관한 것으로, 특히 메모리셀의 셀트랜지스터가 오프상태일때 게이트와 기판전압의 조건이 채널영역이 축적모드에서 동작되도록 하여 누설전류를 억제하는데 적당하도록 한 반도체 메모리에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which the gate and substrate voltage conditions are suitable for suppressing the leakage current by operating the channel region in the accumulation mode when the cell transistor of the memory cell is turned off.
도1은 종래 반도체 메모리가 제조된 기판의 개략적인 단면도로서, 이에 도시한 바와 같이 기판(1)의 일부에 메모리셀의 형성을 위해 P형의 불순물 이온으로 도핑된 셀영역 피웰(2)과; 상기 셀영역 피웰(2)의 측면 및 하부에 위치하는 깊은 딥엔웰(DEEP N-WELL,3)과; 상기 딥엔웰(3)에 의해 상기 셀영역 피웰(2)과 분리되며, 반도체 메모리를 구동하는 주변회로가 위치하는 주변회로영역의 엔형의 모스 트랜지스터가 그 상부에 형성되는 주변회로영역 피웰(4)과; 상기 주변회로영역에 피모스 트랜지스터를 형성하기 위해 위치하는 주변회로영역 엔웰(5)을 포함하여 구성된다.1 is a schematic cross-sectional view of a substrate on which a conventional semiconductor memory is fabricated, and as shown therein, a cell region pewell 2 doped with a P-type impurity ion to form a memory cell in a portion of the substrate 1; A deep deep well (DEEP N-WELL) 3 positioned on the side and bottom of the cell region pewell 2; Peripheral circuit region pewells (4), which are separated from the cell region pewells (2) by the deep and well (3), and have N-type MOS transistors in the peripheral circuit region where peripheral circuits for driving semiconductor memories are located. and; And a peripheral circuit region enwell 5 positioned to form a PMOS transistor in the peripheral circuit region.
상기와 같이 메모리셀의 셀트랜지스터는 엔모스 트랜지스터로, 그 엔모스 트랜지스터의 제조를 위해 기판은 셀영역 피웰(2)로 형성하고, 그 셀영역 피웰(2)에는 기판전압으로 -1V의 저전압(VBB)이 인가된다. 이와 같이 저전압을 인가하는 이유는 메모리셀 영역은 셀트랜지스터의 문턱누설전류를 억제하기 위해 문턱전압을 크게할 필요가 있어, 그 문턱전압을 크게하기 위함이다.As described above, a cell transistor of a memory cell is an NMOS transistor, and a substrate is formed of a cell region pewell 2 for manufacturing the NMOS transistor, and the cell region pewell 2 has a low voltage of −1 V as a substrate voltage. VBB) is authorized. The reason why the low voltage is applied in this way is to increase the threshold voltage in the memory cell region in order to suppress the threshold leakage current of the cell transistor.
또한, 반도체 메모리셀을 구동하는 주변회로가 형성될 주변회로영역에서는 피모스 트랜지스터 및 엔모스 트랜지스터가 함께 형성되며, 이에 따라 주변회로영역피웰(4)과 주변회로영역 엔웰(5)이 형성된다. 이때 주변회로영역 피웰(4)에는 전압값이 0V인 접지전압(VSS)이 인가되며, 주변회로영역 엔웰(5)에는 전원전압(VCC)이 인가되어 그 상부에 형성되는 피모스 트랜지스터 또는 엔모스 트랜지스터의 동작이 고속동작에 적당하도록 문턱전압의 값을 낮추는 방향으로 기판전압을 인가하게 된다.In addition, the PMOS transistor and the NMOS transistor are formed together in the peripheral circuit region in which the peripheral circuit for driving the semiconductor memory cell is to be formed, thereby forming the peripheral circuit region pewell 4 and the peripheral circuit region enwell 5. At this time, a ground voltage VSS having a voltage value of 0 V is applied to the peripheral circuit region pewell 4, and a power supply voltage VCC is applied to the peripheral circuit region enwell 5 to form a PMOS transistor or an NMOS formed thereon. The substrate voltage is applied in the direction of lowering the threshold voltage so that the operation of the transistor is suitable for high speed operation.
도2는 일반적인 반도체 메모리셀의 단면도로서, 이에 도시한 바와 같이 상기 설명한 셀영역 피웰(2)의 상부 중앙에 위치하며, 그 상부 및 측면에 절연막이 형성된 워드라인인 셀트랜지스터의 게이트(6)와; 상기 게이트(6)의 양측면 기판하부에 형성된 소스(7) 및 드레인(8)과; 상기 소스(7)에 접속된 비트라인(8)과; 상기 드레인에 접속되는 커패시터(9)로 구성된다.FIG. 2 is a cross-sectional view of a general semiconductor memory cell. As shown in FIG. 2, a gate line 6 of a cell transistor, which is a word line formed at an upper center of the cell region pewell 2 described above and having insulating films formed thereon, is shown in FIG. ; A source (7) and a drain (8) formed under the substrate on both sides of the gate (6); A bit line (8) connected to the source (7); It consists of a capacitor 9 connected to the drain.
이와 같은 구성에서 메모리셀의 셀트랜지스터가 오프되는 경우, 워드라인인 게이트(6)에는 0V의 전압이 인가되며, 커패시터(9)의 하부전극에는 데이터 H를 기준으로 2V의 전압이 인가되며, 기판전압은 상기 설명한 -1V의 VBB가 인가되며, 상기 커패시터(9)의 상부전극에는 1V의 전압이 인가되어, 하부전극의 접합 누설전류(storage node junction leakage), 커패시터의 누설전류(capacitor leakage), 표면발생전류(surface generation current), 트랜지스터 문턱 누설전류(transistor subthreshold leakage), 분리 누설전류(isolation leakage)가 발생한다.In this configuration, when the cell transistor of the memory cell is turned off, a voltage of 0 V is applied to the word line gate 6, and a voltage of 2 V is applied to the lower electrode of the capacitor 9 based on data H. The voltage is applied to the above-described VBB of -1V, the voltage of 1V is applied to the upper electrode of the capacitor 9, the storage node junction leakage of the lower electrode, the capacitor leakage (capacitor leakage) of the capacitor, Surface generation current, transistor subthreshold leakage, and isolation leakage occur.
이는 셀트랜지스터가 오프상태일때 즉, 게이트에 0V, 셀영역 피웰(2)에 -1V가 인가되는 상태에서 채널영역이 공핍모드로 동작하여 그 채널영역에서 상기 표면발생전류에 의해 커패시터(9)의 리프레시 특성이 열화되는 것이다.This is because the channel region operates in the depletion mode when the cell transistor is turned off, that is, 0 V is applied to the gate and -1 V is applied to the cell region pewell 2 so that the surface of the capacitor generates the capacitor 9 in the channel region. The refresh characteristic is deteriorated.
또한, 주변회로영역과 셀영역의 기판전압이 달라지므로, 딥엔웰(3)에 의해 종류가 동일한 두 웰을 서로 격리해야 함으로써, 칩면적이 증가하게 된다. 이와 같은 딥엔웰(3)을 사용하지 않으려면, 상기 주변회로영역의 피웰(4)과 셀영역의 피웰(2)에 동일한 기판전압을 인가하여 두 영역을 하나의 영역으로 형성하면 되나, 상기 설명한 셀트랜지스터의 동작특성과 주변회로영역의 트랜지스터의 특성차이에 의해 현재의 방식으로는 딥엔웰(3)의 형성이 불가피하다.In addition, since the substrate voltages of the peripheral circuit region and the cell region are different, the two wells of the same type are separated from each other by the deep N well 3, thereby increasing the chip area. In order not to use the deep N well 3, the same substrate voltage may be applied to the Pwell 4 of the peripheral circuit region and the Pwell 2 of the cell region to form two regions as one region. Due to the difference between the operation characteristics of the cell transistor and the transistors in the peripheral circuit region, the formation of the deep n well 3 is inevitable in the present method.
상기 설명한 바와 같이 셀영역 피웰(2)에는 문턱전압을 높이기 위해 -1V의 VBB를 인가하여 커패시터 하부전극과의 전압차가 커져 그 노드에서 누설전류가 발생하여 반도체 메모리의 특성이 열화된다.As described above, in order to increase the threshold voltage, the cell region pwell 2 is applied with a VBB of −1 V to increase the voltage difference with the lower electrode of the capacitor, resulting in leakage current at the node, thereby degrading the characteristics of the semiconductor memory.
상기한 바와 같이 종래 반도체 메모리는 셀영역과 주변회로영역에 위치하는 피웰에 서로다른 값의 전압을 인가하기 위해 두 피웰영역의 사이에 딥엔웰을 형성하여 반도체 메모리의 집적도가 저하됨과 아울러 셀영역 피웰에 -1V의 저전압을 인가하여 커패시터와의 전압차가 커져, 전계가 강해짐으로써, 커패시터 노드에서의 누설전류가 발생하는 문제점이 있었으며, 셀트랜지스터가 오프되는 전압조건이 게이트에 0V, 기판에 -1V가 인가되어, 채널영역이 공핍상태가 되어 그 채널영역에서의 표면발생 누설전류가 발생되어 반도체 메모리의 리프레시 특성이 열화되는 문제점이 있었다.As described above, in the conventional semiconductor memory, a deep enwell is formed between two pewell regions in order to apply different voltages to the pewells located in the cell region and the peripheral circuit region, thereby decreasing the degree of integration of the semiconductor memory and also in the cell region pewell. A low voltage of -1V was applied to the capacitor to increase the voltage difference and the electric field became stronger, resulting in a leakage current at the capacitor node.The voltage condition at which the cell transistor was turned off was 0V at the gate and -1V at the substrate. There is a problem in that the channel region is depleted and surface leakage current is generated in the channel region, thereby degrading the refresh characteristics of the semiconductor memory.
이와 같은 문제점을 감안한 본 발명은 셀트랜지스터의 오프 전압조건을 변경하여 그 셀트랜지스터가 오프되었을 때, 채널영역이 공핍상태가 아닌 축적상태에 있도록 함과 아울러 셀영역 피웰에 인가되는 전압을 접지전압으로 하여 누설전류 및 집적도를 향상시킬 수 있는 반도체 메모리를 제공함에 그 목적이 있다.In view of the above problems, the present invention changes the off voltage condition of a cell transistor so that when the cell transistor is turned off, the channel region is in an accumulation state rather than a depletion state, and the voltage applied to the cell region pewell is grounded. The purpose is to provide a semiconductor memory that can improve the leakage current and the degree of integration.
도1은 종래 반도체 메모리가 형성되는 기판의 개략적인 단면도.1 is a schematic cross-sectional view of a substrate on which a conventional semiconductor memory is formed.
도2는 일반적인 메모리셀의 단면도.2 is a cross-sectional view of a typical memory cell.
도3은 본 발명 반도체 메모리가 형성되는 기판의 개략적인 단면도.3 is a schematic cross-sectional view of a substrate on which a semiconductor memory of the present invention is formed.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:피웰1: Substrate 2: Pewell
3:엔웰3: enwell
상기와 같은 목적은 기판의 각영역에 복수의 피웰 및 엔웰을 위치시키고, 그 복수의 피웰중 선택된 피웰 상에 위치하며 셀트랜지스터와 커패시터를 포함하는 메모리셀과; 상기 메모리셀이 위치하지 않은 나머지 피웰상에 위치하는 주변회로중 엔모스 트랜지스터와; 상기 엔웰 상에 위치하는 주변회로중 피모스 트랜지스터를 포함하는 반도체 메모리에 있어서, 상기 복수의 피웰 전체에는 접지전압을 인가함과 아울러 상기 셀트랜지스터의 오프시 게이트전압을 -1V로 하여, 그 셀트랜지스터의 오프시 채널영역이 축적모드에 있도록 함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a memory cell for positioning a plurality of pewells and enwells in each region of the substrate, and a selected position of the plurality of pewells and including a cell transistor and a capacitor; An NMOS transistor among peripheral circuits positioned on the remaining pewells in which the memory cell is not located; A semiconductor memory including a PMOS transistor among peripheral circuits located on the enwell, wherein a ground voltage is applied to all of the plurality of pwells, and a gate voltage of -1V when the cell transistor is turned off is set. This is achieved by allowing the channel region to be in the accumulation mode at the time of off, and will be described in detail with reference to the accompanying drawings.
도3은 본 발명 반도체 메모리가 위치하는 기판의 개략적인 단면도로서, 이에 도시한 바와 같이 기판(1)의 표면으로 부터 소정깊이에 이르도록 매몰되어 형성되며, 그 상부에 메모리셀과 주변회로 중 엔모스 트랜지스터가 형성될 피웰(2)과; 상기 피웰(2)의 측면에 위치하며 상기 주변회로 중 피모스 트랜지스터가 형성될 엔웰(3)로 구성된다.FIG. 3 is a schematic cross-sectional view of a substrate on which a semiconductor memory of the present invention is located, and is buried to reach a predetermined depth from the surface of the substrate 1 as shown in FIG. A pewell 2 in which a MOS transistor is to be formed; Located on the side of the pewell (2) and consists of the enwell (3) in which the PMOS transistor of the peripheral circuit is to be formed.
또한, 상기 피웰(2)에는 기판전압으로 0V인 접지전압(VSS)이 인가되며, 상기 엔웰(3)에는 종래와 동일하게 전원전압(VCC)이 인가된다.In addition, a ground voltage VSS of 0 V is applied to the pewell 2, and a power supply voltage VCC is applied to the enwell 3 as in the prior art.
이와 같이 메모리셀영역과 주변회로영역의 소자, 즉 셀트랜지스터와 엔모스트랜지스터가 형성될 피웰(2)에 접지전압(VSS)을 인가하면, 종래와 같이 셀영역 피웰과 주변회로영역 피웰을 분리하기 위한 딥엔웰을 사용하지 않아도되어 그 집적도가 향상되나, 상기 설명한 바와 같이 셀트랜지스터의 문턱전압값이 저하되므로, 이를 보완하기 위해 셀트랜지스터의 오프조건을 기존의 0V에서 -1V에서 오프되도록 한다.As described above, when the ground voltage VSS is applied to the elements of the memory cell region and the peripheral circuit region, that is, the cell transistors and the MOS transistors, the cell region pewell and the peripheral circuit region pewells are separated. Although the integration is improved by not using a deep n well, the threshold voltage value of the cell transistor is reduced as described above. To compensate for this, the off condition of the cell transistor is turned off from -1V to -1V.
다시말해서, 셀트랜지스터를 오프시키는 전압을 보면 워드라인인 게이트에 인가되는 전압을 -1V로 하고, 셀영역 피웰의 기판전압을 0V로 한다.In other words, when the voltage for turning off the cell transistor is set, the voltage applied to the gate, which is the word line, is -1V, and the substrate voltage of the cell region pewell is 0V.
이와 같은 전압의 분포에서 셀트랜지스터가 오프되었을 경우 그 채널영역은 공핍모드가 아닌 축적모드로 있으며, 이와 같은 동작으로 채널영역의 상부표면에서의 누설전류는 발생하지 않게 된다.When the cell transistor is turned off in this voltage distribution, the channel region is in the accumulation mode instead of the depletion mode. As a result, the leakage current at the upper surface of the channel region is not generated.
또한, 셀영역 피웰에 VSS가 인가됨으로써, 커패시터 하부전극과의 전압차가 커패시터에 고전위의 전압축적된 경우 2V로 종래 3V에 비해 그 전계가 줄어 누설전류의 발생이 억제된다.In addition, when VSS is applied to the cell region pewell, when the voltage difference with the capacitor lower electrode is accumulated at high potential in the capacitor, the electric field is reduced to 2V, compared to the conventional 3V, thereby suppressing generation of leakage current.
상기한 바와 같이 본 발명 반도체 메모리는 그 셀트랜지스터의 오프조건을 기판전압 0V에 게이트전압 -1V로, 셀트랜지스터의 오프시 채널영역이 축적모드로 있게 하여, 채널영역의 상부표면에서 발생하는 누설전류의 발생을 방지하고, 커패시터의 하부전극과 기판전압의 전압차를 줄여 그 커패시터의 노드에서 발생하는 누설전류의 양을 감소시켜 메모리셀의 리프레시 특성을 향상시키는 효과와 아울러 상기 셀영역의 피웰과 주변회로영역의 피웰에 인가되는 전압을 동일하게 하여, 두 피웰을 분리하는 딥엔웰을 형성하지 않아도 됨으로써, 집적도를 향상시키는 효과가 있다.As described above, in the semiconductor memory of the present invention, the cell transistor is turned off with a gate voltage of -1V at a substrate voltage of 0V, and the channel region is in the accumulation mode when the cell transistor is turned off, so that the leakage current generated at the upper surface of the channel region. To reduce the voltage difference between the lower electrode of the capacitor and the substrate voltage, thereby reducing the amount of leakage current generated at the node of the capacitor, thereby improving the refresh characteristics of the memory cell, as well as improving the pewell and the surrounding area of the cell region. By having the same voltage applied to the pwell in the circuit area, it is not necessary to form a deep enwell separating the two pwell, thereby improving the degree of integration.
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