KR100308301B1 - The reference value generation circuit for three phase drive of a power factor correction apparatus - Google Patents

Abstract

The present invention relates to a three-phase driving reference value generation circuit of a power factor correction apparatus, and has conventionally had a problem in that a peripheral circuit is complicated by using an analog chip for power factor correction. Accordingly, the present invention provides an initial pointer setting unit for setting an initial pointer based on a zero point or an arbitrary pointer value through a digital circuit, and a second pointer for calculating and outputting a pointer value and a pulse driving period deceleration signal set in the initial pointer setting unit. A first pointer generation unit and a second pulse point obtained by adding or subtracting the current pulse driving period to the current pointer according to the pulse driving period deceleration signal provided by the first pointer generation unit, and obtaining a point (next_address) to provide to the first pointer generation unit. The pointer generator, the sine wave table for reading and outputting the sine wave data stored in the pointer provided by the first pointer generator, and the sine wave data output from the table are determined according to the voltage level supplied to the inverter. A multiplier for multiplying and outputting a predetermined pulse width determination factor, and provided by the first pointer generator Is a phase generator that generates and outputs a reference value of each phase determined by adding or subtracting an arbitrarily set amplitude value to a value output from the multiplier according to polarity, and thus the circuit is simple, economical and efficient. I did it.

Description

Reference value generator for three-phase driving of power factor corrector {THE REFERENCE VALUE GENERATION CIRCUIT FOR THREE PHASE DRIVE OF A POWER FACTOR CORRECTION APPARATUS}

The present invention generates a three-phase reference value for power factor correction apparatus for generating an economical and efficient three-phase reference value based on the data of a sine wave table of 90 ° or less. In particular, the present invention relates to a three-phase driving reference value generating circuit of a power factor correcting apparatus that generates a three-phase driving reference value based on an offset register value for setting a reference value amplitude.

Inverters are rapidly being promoted due to energy saving and ease of output control of home appliances.

Washing machines, refrigerators, air conditioners and the like are on the market as home appliances to which a motor driven by the inverter (INVERTER) is applied.

1 is a block diagram of a conventional inverter system. As shown in FIG. 1, the rectifier 11 rectifies the commercial AC power input to a DC voltage through a bridge diode, and the choke coil 12 outputs the smoothed output therefrom. And the smoothing capacitor 13, the choke coil 12 and the smoothing capacitor 13 converts the DC voltage smoothed through the pulse width modulation (PWM) into a three-phase AC power source motor (M). It is composed of an inverter 14 to be provided to drive.

The operation of the inverter system configured as described above will be described based on FIG. 2. First, an AC power source having a commercial AC power voltage waveform as shown in FIG. 2A and a commercial AC power current waveform as shown in FIG. 2B is rectified. ), The rectifier 11 rectifies a DC voltage using a bridge diode and outputs the same to the choke coil 12.

Then, the choke coil 12 and the smoothing capacitor 13 are smoothed to remove the AC component included in the DC voltage of the rectifier 11, and the DC voltage from which the AC component is removed is output to the inverter 14. do.

At this time, the DC voltage input to the inverter 14 becomes a voltage larger than the peak value of the input AC power supply.

Accordingly, the inverter 14 converts the three-phase AC power by the on / off operation of the switching element to the DC voltage input from the smoothing capacitor 13 to provide the motor M to drive the motor.

In FIG. 2 (b), time t is a time determined by the time constants of the choke coil 12 and the smoothing capacitor 13, and is usually 1/5 or less of a commercial AC power supply.

Assuming that the power factor is 1, the current waveform flowing through the inverter is in phase with the commercial AC power input and has a peak current much smaller than the maximum current, as shown in FIG.

Thus, if the ideal current waveform as shown in Fig. 2 (c) is made, the advanced countries such as noise reduction and reactive power reduction are legalized to produce the waveform as shown in Fig. 2 (c).

A power factor correction circuit is used to make a waveform as in FIG. 2 (c), the configuration of which is as shown in FIG.

Figure 3 is a detailed view of the power factor correction circuit of the conventional inverter system, as shown here, the rectifier 31 for rectifying the commercial AC power input to the DC voltage through the bridge diode, and outputs the smoothed output from the above The DC voltage smoothed through the choke coil 32 and the smoothing capacitor 33, and the choke coil 32 and the smoothing capacitor 33 are converted back into three-phase AC power through pulse width modulation (PWM). And a comparator, a multiplexer, a NAND gate, a noah gate, and the like, for the inverter 36 for supplying and driving the motor M, and the output voltage of the rectifier 31 and the voltage across the smoothing capacitor 33. By using the analog power factor improving unit 34 for varying the pulse width duty so that the overall input current and voltage are equal to each other and the pulse width duty varied in the analog power factor improving unit 34. It is composed of a switching element Q1 for controlling the charging and discharging operation of the utilization capacitor 33 and is composed of a power factor correcting unit 35 for correcting the power factor.

The operation of the power factor correction configured as described above will be described with reference to FIGS. 3 and 4.

When a commercial AC power is applied, the rectifier 31 rectifies the DC voltage and outputs the rectified DC voltage.

The DC voltage outputted in this way is input to the terminal ③ VM1 of the analog power factor improving unit 34 by the voltage divided by the resistors R1 and R2 of the power factor correcting unit 35 and the choke coil 32. The induced voltage is input to terminal ⑤ of the analog power factor improving unit 34 through the resistor R5, and the induced voltage of the choke coil 32 is connected to the resistor R4, the diode D1, and the like. The voltage adjusted by the capacitor C3 and the voltage adjusted by the resistor R3 are added, and the added voltage is input to the ⑧ terminal VCC of the analog power factor improving unit 34.

The reason why the input voltage is continuously received through the terminal VCC of the above is to be the same as the waveform of the input voltage during power factor control.

A voltage obtained by dividing the DC voltage of the rectifier 31 through the choke coil 32 and the diode D2 to the inverter 36 by the resistors R11-R13 is the analog power factor improving unit 34. Input voltage is input to the terminal (INV) of ①, and the voltage divided by the time constants of the capacitor (C2) and the resistors (R7, R8) is divided into the terminal (②) of the analog power factor improvement unit 34. A voltage corresponding to the current supplied to the (COMP) and supplied to the inverter 36, that is, the voltage determined by the capacitor C3 is input to the terminal ④.

The input voltage is inputted through the comparators 341, 347, and 349, the multiplexer 347, the NAND gates 343 and 344, the self-stacker 342, and the noah gate 345 shown in FIG. 4 and the output of the inverter 36. The pulses are output by comparing the voltages so that the two voltages are the same. As a result, as shown in (a) and (b) of FIG. Output pulse through ⑦.

The pulse output through terminal ⑦ Vout of the analog power factor improving unit 34 is input to the gate of the switching element Q1, and the switching element Q1 is turned on or off in accordance with the pulse to input the input current and the input. Correct the power factor by making the voltage waveforms the same.

However, in the prior art as described above, there is a problem that the peripheral circuit is complicated by using an analog chip for power factor correction.

Accordingly, the present invention for solving the conventional problems as described above is to provide a three-phase drive reference value generation circuit of the power factor correction apparatus to implement a power factor correction apparatus in a digital circuit to be configured simply.

Another object of the present invention, when the zero point of the input power supply voltage is input, generates a reference value of the U, V, W phase by using the 0 ° ~ 90 ° data stored in the sine wave table, and performs the power factor correction according to each phase It is to provide a three-phase drive reference value generation circuit of the power factor correction device.

1 is a block diagram of a general inverter system.

FIG. 2 is an input / output waveform diagram of each part shown in FIG. 1. FIG.

3 is a detailed view of a power factor improvement circuit of the conventional inverter system.

4 is a detailed view of an analog power factor improving unit in FIG. 3.

5 is an input / output waveform diagram of each part in FIG. 4;

6 is a circuit diagram illustrating a power factor correcting apparatus of the present invention.

7 is a block diagram of a three-phase driving reference value generation circuit of the power factor correction apparatus of the present invention.

FIG. 8 is a, b, direction and pole generation tables for pointers of respective phases stored in a memory in the first pointer generator in FIG.

9 is a V, W phase waveform diagram having a phase difference from the U phase.

FIG. 10 is a flowchart illustrating an operation of a first pointer generator in FIG. 7.

FIG. 11 is an explanatory diagram showing an occurrence value of out_dir in FIG. 7; FIG.

FIG. 12 is a flowchart illustrating an operation of a second pointer generator in FIG. 7. FIG.

FIG. 13 is a flowchart showing an operation of a phase generator in FIG. 7; FIG.

14 is a three-phase reference value and PWM signal waveform diagram in FIG.

***** Explanation of symbols for the main parts of the drawing *****

61 Inverter 62 Choke Coil

63: smoothing capacitor 64: inverter

65 zero voltage detector 66 voltage level detector

67: three-phase reference value generator 68: drive unit

1: pointer register 72: multiplexer

73: Oagate 74: the first pointer generator

75: second pointer generator 76: sign table

77: multiplier 78: phase generator

79: offset register 80: initial pointer setting section

In order to achieve the above object, the present invention calculates and outputs an initial pointer setting unit for setting an initial pointer based on a zero point or an arbitrary pointer value, and a pointer value and a pulse driving period deceleration signal set by the initial pointer setting unit. According to the first pointer generating unit and the pulse driving period deceleration signal provided by the first pointer generation unit to obtain the current pulse driving period by adding or subtracting the current pulse driving period to obtain the next point (next_address) to provide to the first pointer generator. The second point generator, a sine wave table that reads and outputs sine wave data stored in a pointer provided by the first pointer generator, and a voltage level supplied to the inverter to sine wave data output from the table. A multiplier for multiplying and outputting a pulse width decision factor determined according to the first point generator, and And a phase generator for generating and outputting a reference value of each phase determined by adding or subtracting an arbitrarily set amplitude value to a value output from the multiplier according to the polarity.

Hereinafter, with reference to the accompanying drawings in detail as follows.

7 is a configuration diagram of a three-phase driving reference value generation circuit of the power factor correction apparatus of the present invention. As shown in FIG. 7, an initial pointer is set based on a zero point or an arbitrary pointer value provided by a zero voltage detector. An initial pointer setting unit 71, a first pointer generating unit 74 for calculating and outputting a pointer value and a pulse driving period ramp signal set by the initial pointer setting unit 71, and the first pointer generating unit 74; And a second pointer generator 75 which obtains a point (next_address) by adding or subtracting the current pulse driving cycle to the current pointer according to the pulse driving period acceleration / deceleration signal provided by the second pointer generator 74 and provides the point pointer to the first pointer generator 74. And a sine wave table 76 for reading and outputting sine wave data stored in a pointer provided by the first pointer generator 74, and the sine wave data output from the table 76. A multiplier 77 for multiplying and outputting a pulse width determination factor determined according to a voltage level supplied to the data emitter, and a value output from the multiplier according to the polarity provided by the first pointer generator 74. And a phase generator 78 for generating and outputting a reference value of each phase determined by adding or subtracting an arbitrarily set amplitude value to the offset value, and an offset register 79 for setting an amplitude value supplied to the phase generator 78. .

Referring to the operation and effect of the present invention configured as described in detail as follows.

When the rectifier 61 outputs a DC voltage generated by rectifying the input AC power, and removes the AC component included in the DC voltage from the choke coil 62 and the smoothing capacitor 63 and supplies it to the inverter 64. The inverter 64 converts the DC voltage into an AC power source and supplies the same to the motor M to drive the same.

At this time, the zero voltage detector 65 detects the zero voltage of the input AC power source and provides it to the three-phase reference value generator 67, and also detects the level of the voltage supplied from the voltage level detector 66 to the inverter 64. To the three-phase reference value generator 67.

Then, the three-phase reference value generator 67 determines a pulse width determination coefficient determined by the three-phase sine wave detected by the zero voltage of the zero voltage detector 65 and the level detected by the voltage level detector 66. The three phase reference value is generated by the factor) and output to the driver 68.

Accordingly, the driver 68 corrects the power factor by controlling the operation of the switching element Q1 based on the reference value output from the three-phase reference box generator 67.

The operation of the three-phase reference value generator 67 will now be described in detail with reference to FIG. 7.

The pointer written in the pointer register 71 is provided to one input terminal of the multiplexer 72, and the zero voltage detection signal detected by the zero voltage detector 65 is output.

In this case, the zero voltage detector 65 provides a zero point control bit of '0' to the multiplexer 72 when a zero voltage is detected, and provides a zero point control bit of '1' if a zero voltage is not detected.

Then, the multiplexer 72 selects and outputs a zero voltage signal when a zero point control bit of '0' is input, and selects a pointer output from the pointer register 71 when a zero point control bit of '1' is input. The oragate 73 is output.

Accordingly, the oA gate 73 transmits the input signal to the first pointer generator 74.

Then, the first pointer generator 74 is a, b, direction, polarity according to each phase (U, V, W) stored in a table in a memory not shown according to an arbitrary pointer. Then, the pointer initial value and in_dir (pulse driving period acceleration / deceleration signal) are sequentially calculated for U, V, and W phases.

Where a is the point where the pointer ends, b is the point where the pointer begins, and the direction is set to 0 to 0-90 °, otherwise to 1, and the polarity is 0 to the 0-180 ° interval. , Set to 1 for 180-360 °.

Then, looking at the contents of the table with respect to the U phase, the pointer [15: 0] value (X) is shown in FIG.

Ⓐ If 0≤X≤90 °, the current pointer value is X, so select a ← pointer, b ← 0, direction ← 0,

Ⓑ 90 ° ≤ X ≤ 180 °, since it is symmetric with ⓐ, select a ← 2X, b ← pointer, direction ← 1,

If ⓒ180 ° ≤X≤270 °, select a ← pointer, b ← 2X, direction ← 1,

If ⓓ270 ° ≤X≤360 °, a ← 4X, b ← pointer. Select direction ← 1, calculate intermediate value = ab if direction is '1', calculate intermediate value = a + b if direction is '0', and find meaningful bits in the range of 90 °. Output to the pointer to set the initial value.

In other words, as illustrated in FIG. 10, when the zero point control bit of '0' is input from the zero voltage detector 65, the first pointer generator 74 determines that the zero voltage signal is applied to the pointer ( After setting the pointer and the polarity to '0', the initial value of the pointer is calculated using a ± b according to each phase, and the pulse driving period deceleration signal (in_dir) is set to '0'. )

When the zero point control bit of '1' is input from the zero voltage detector 65, it is determined that the zero voltage signal is not detected, the pointer output from the pointer register 71 is accepted, and the pointer register 71 is output. It is checked whether the first cycle is performed (S103).

As a result of the check, if the first cycle is output from the pointer register 71, the output pointer is received (S104), and the initial value for each phase (U, V, W) is calculated using a ± b. , Pulse driving period ramp signal in_dir is set to '0' (S102).

If a predetermined time has elapsed rather than initialization (S105), the next address NEXT_ADDRESS generated by the second pointer generation unit 75 is sequentially applied to the pointer for each phase and set as the next pointer (pointer ← next_address). ) and the value of out_dir (drive cycle change signal) is applied to in_dir (pulse drive cycle ramp signal) to output the in_dir value.

Here, the sine wave is stored in the memory that stores the sine wave from 0 to 90 °, so it is obtained by adding or subtracting the data from 0 to 90 ° from 90 ° to 360 °. Decide whether or not the signal for the sine wave continues to add or increase or decrease.

And out_dir (drive cycle change signal) changes the signal value every 90 degrees as shown in FIG.

As described above, the first pointer generator 74 receives the pointer and the pulse driving period deceleration signal in_dir, and the second pointer generator 75 generates the pulse driving period according to the pulse driving period deceleration signal In_dir. the next pointer (next_address) value is calculated and added to the first pointer generator 74, and the second pointer generator 75 is connected to the pointer provided from the first pointer generator 74. The pulse driving period is added to or subtracted from the pulse driving period in_dir to generate the next point (next_address), and is provided to the first pointer generator 74 via the oragate 73.

That is, when the pulse driving period ramp signal in_dir is '0' (that is, when the pointer exists in the range of 0 to 90 ° and 180 to 270 °), the second point generator 75 is the second point generator. The next pointer (next_address) is output to the oragate 74 by adding a pulse driving period to the current pointer value.

At this time, when the calculated next pointer (next_address) is less than or equal to 'X' as shown in FIG. 11, the driving period change signal out_dir becomes out_dir = 0, and pulse driving is performed on the current pointer value when the pointer is calculated. If the next pointer (next_address) is greater than 'X', it is out after 90 °, so out_dir = 1, and the pulse pointer frequency is subtracted from the current pointer value.

The second pointer generator 75 generates a second point when the pulse driving period ramp signal in_dir is '1' (that is, when the pointer is present in the 90 ° to 180 ° and 270 ° to 360 ° sections). The unit 75 outputs the next pointer next_address to the oragate 74 by subtracting the pulse driving frequency from the current pointer value.

At this time, if no carry occurs at the next pointer (next_address), the drive period change signal (out_dir) is out_dir = 1 because the pointer section is continuously between 90 ° and 180 ° or 270 ° to 360 °. When the pointer is calculated, the pulse driving period is subtracted from the current pointer value, and if a carry occurs during operation and the pointer section exceeds the 90 ° to 180 ° or 270 ° to 360 ° range, the drive cycle change signal (out_dir) When out_dir = 0, the pulse driving frequency is added to the current pointer value during the next pointer calculation.

Thus, the operation flow of the second pointer generator 75 is as shown in FIG.

By obtaining the next pointer (next_address) in this manner and providing the next point (next_address) to the first point generator 74 through the oragate 73, the first point generator 74 can input an input point value and a drive cycle change signal ( out_dir) and outputs the pointer computed through the above-described process to the sine wave table 76.

The sine wave table 76 reads the sine wave data stored in the pointer provided by the first pointer generator 74 and outputs the sine wave data to the multiplier 76.

Then, the multiplier 76 obtains a value obtained by multiplying a pulse width determination factor set according to the level detected by the voltage level detector 66 of FIG. 6 with the sine wave data output from the sine wave table 76 ( mul_out) is output to the phase generator 78.

At this time, the polarity of the pointer currently generated by the first pointer generator 74 is provided to the phase generator 78, and the offset register 79 provides an offset, which is a reference value for determining the amplitude to be used.

Accordingly, as shown in FIG. 13, when the polarity is '0', the phase generator 78 adds a value mul_out provided by the multiplier 77 to an offset value provided by the offset register 79. When the polarity is '1', the reference value is generated and the reference value is generated by subtracting the value mul_out provided by the multiplier 77 from the offset value provided by the offset register 79.

For this operation, reference values for the respective phases U, V, and W are obtained and provided to the driving unit 68 of FIG.

Accordingly, the driver 68 generates a PWM signal according to the reference value of each phase U, V, and W as shown in FIG. 14 to drive the switching element Q1 to correct the power factor.

As described in detail above, the present invention generates a three-phase reference value based on data of a sine wave table of 90 ° or less from zero voltage or an arbitrary instant. There is an effect to generate economically and efficiently in the calibration.

Claims (3)

A rectifier for rectifying the input AC power into a DC voltage, an inverter for converting the DC voltage back to an AC power and supplying the motor, and a zero voltage of the AC power to detect a zero voltage signal and a zero point control bit accordingly. A zero voltage detector for outputting, a voltage level detector for detecting a level of the voltage supplied to the inverter and outputting a pulse width determination coefficient according thereto, and a zero voltage signal or arbitrary value according to the zero point control bit An initial pointer setting unit which sets an initial pointer based on a pointer value, and calculates and outputs a pointer value and a pulse driving period deceleration signal set by the initial pointer setting unit, and obtains and outputs the polarity of the pointer value. A current pointer according to a first pointer generator and a pulse driving period deceleration signal provided by the first pointer generator; A second pointer generator which obtains a point (next_address) by adding or subtracting a current pulse driving period to the first pointer generator, and supplies the sine wave data stored in the pointer provided by the first pointer generator. A sine wave table to be read and output, a multiplier that multiplies the pulse width determination factor of the voltage level detector by the sine wave data output from the table, and a polarity provided by the first pointer generator; And a phase generator for generating and outputting a reference value of each phase determined by adding or subtracting an amplitude value arbitrarily set to a value output from the multiplier according to the reference value generating circuit for driving the power factor correction apparatus. The method of claim 1, wherein the initial pointer setting unit selects one of a pointer register for outputting a randomly set pointer value, a pointer value output from the pointer register, or a zero voltage signal provided by a zero voltage detector according to a zero point control bit. And an oar gate configured to add and output a multiplexer and a signal selected by the multiplexer and a next pointer value generated by the second pointer generator. The method of claim 1, wherein the phase generator generates a reference value by adding a multiplier value to an offset value for determining amplitude when the polarity generated by the first pointer generator is '0', and when the polarity is '1'. A reference value generation circuit for driving a three-phase drive of a power factor correction apparatus, characterized in that the reference value is generated by subtracting the multiplier value mul_out from the offset value.