KR100307400B1 - Data transmitter between processor in the communication ssystem - Google Patents

Abstract

The present invention relates to a mobile communication system employing a CDMA scheme such as DCS, PCS, etc., in which a broadcasting system can implement a broadcasting function by simultaneously transmitting data from one upper processor to a plurality of lower processors using a buffer control function. The inter-processor data transmission apparatus of the present invention, when the upper processor is to transmit data to all the lower processor at the same time through the decoder outputs the broadcasting control signal and the selection control signal for each sub-processor to the buffer control unit, and then the buffer control unit According to the control signal, the enable signal is output to the data buffer unit and the memory in the lower processor so that the data of the upper processor stored in the data buffer unit can be read from the memory unit in the lower processor and transmitted. Only When the data is to be transmitted, the block configurations operate according to the selection control signal for each lower processor, so that the data of the upper processor stored in the data buffer unit can be read and transmitted from the memory unit in the corresponding lower processor. As such, by using a buffer control function, one upper processor may implement broadcasting by transmitting data to multiple lower processors at once, thereby improving data transmission efficiency and thus improving system performance. It is effective.

Description

Data transmitter between processor in the communication ssystem

The present invention applies a code division multiple access (CDMA) scheme such as a digital cellular communication system (hereinafter referred to as 'DCS') and a personal communication system (hereinafter referred to as 'PCS'). In a mobile communication system, the present invention relates to an interprocessor data transmission apparatus in a communication system capable of simultaneously transmitting data from one upper processor to a plurality of lower processors by using a buffer control function.

In general, mobile communication systems employing CDMA schemes such as DCS, PCS, and the like, transmit and receive data by communicating with each other through a back board.

That is, as shown in FIG. 1, in a system in which one upper processor 1 manages a plurality of lower processors 2-1 to 3, one upper processor 1 and a plurality of lower processors 2-1 to 3 are managed. 3) uses the same back plane to interface with each other to transmit and receive data.

However, in the related art, when an upper processor transmits data to a plurality of lower processors, only one lower processor may be transmitted at a time, and data may not be simultaneously transmitted to all the lower processors.

The present invention has been made to solve the above problems, the object of the present invention is a mobile communication system using a CDMA method such as DCS, PCS, etc., using a buffer control function from one upper processor to a plurality of lower processors at the same time An object of the present invention is to provide an interprocessor data transmission apparatus in a communication system capable of implementing a broadcasting function by transmitting data.

1 is a diagram illustrating data transmission between a conventional upper processor and a lower processor;

2 is a block diagram of an apparatus for transmitting data between processors in a communication system according to the present invention;

3 is a detailed block diagram of the configuration of FIG.

<Description of the symbols for the main parts of the drawings>

10: upper processor 20: decoder

30: buffer control unit 40: data buffer unit

50: lower processor 60: memory

70: CPU

The inter-processor data transmission apparatus in the communication system of the present invention for achieving the above object, when the upper processor is to transmit data to all the lower processor at the same time buffers the broadcasting control signal and the selection control signal for each lower processor through the decoder The controller outputs the enable signal to the data buffer unit and the memory in the lower processor according to the control signal, and receives the data of the upper processor stored in the data buffer unit from the memory unit in the lower processor. If the upper processor wants to transmit data only to the lower processor, the block configurations are operated according to the selection control signal for each lower processor, so that the data of the upper processor stored in the data buffer unit is stored in the corresponding lower processor memory unit. DE to features that allow you to transfer.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the inter-processor data transmission apparatus in the communication system according to the present invention.

2 is a block diagram of an interprocessor data transmission apparatus in a communication system according to the present invention, in which an address signal and a control signal output from an upper processor 10 are input to select a broadcasting control signal and a lower processor. A decoder 20 that outputs a selection control signal for each subprocessor to enable, a broadcasting control signal and a selection control signal for each subprocessor that are output from the decoder 20 to be enabled or disabled. A buffer controller 30 for outputting a (Disable) signal and a data stored in the upper processor 10 are stored and operated according to an enable or disable signal output from the buffer controller 30. Data buffer unit 40 to be output to the memory unit 60 in the (50), and enable or disable scene output from the buffer control unit 30 A memory unit 60 for storing data of the upper processor 10 outputted from the data buffer unit 40 and a CPU 70 for controlling data storage of the memory unit 60 according to a call; It is composed of a lower processor (50).

3 is a detailed block diagram of the buffer control unit 30, the data buffer unit 40, and the memory unit 60. The buffer control unit 30 may include a broadcasting control signal output from the decoder 20. The first to third AND gates 31 to 33 are inputted to logically multiply by selecting the first to third control signals for each lower processor. The data buffer unit 40 includes the upper processor 10. Memory stored in the lower processor 50 by storing the data outputted from the control unit and operating according to the enable or disable signal output from the first to third and gates 31 to 33 in the buffer controller 30. And first to third buffers 41 to 43 for each sub-process outputted to (60), and the memory unit 60 includes first to third and gates 31 to 33 in the buffer controller 30. The data buffer operates according to the enable or disable signal output from the 40 is made up of my first to third buffers 41 to 43 first to third Diffie RAM (DPRAM) (61~63), each sub-processor to store the data of the higher-processor 10 to be output from.

In the first to third buffers 41 to 43, a 74F245 chip is used, and the first to third deprams 61 to 63 in the memory unit 60 according to the number of data bits output from the upper processor 10. ) Can be used for 8-bit, 16-bit, and 32-bit.

Here, the configuration has been described using three subprocessors as an example. However, the number of subprocessors includes the AND gate in the buffer controller 30 and the buffers in the buffer and memory unit 60 in the data buffer unit 40. The number is determined.

In the present invention, when the data is written to a predetermined address in the memory unit 60 of the lower processor, an interrupt is generated using a memory device having a characteristic of generating an interrupt to a counterpart. However, FIFO (First In First) is implemented. It can also be implemented using

Referring to the operation of the inter-processor data transmission apparatus in the communication system according to the present invention configured as described above are as follows.

First, when the upper processor 10 has data to transmit to all lower processors at the same time and wants to transmit the data, the upper processor 10 outputs an address signal and a control signal to the decoder 20.

Then, the decoder 20 generates a broadcasting control signal for selecting all lower processors and a selection control signal for each lower processor according to the address signal and the control signal output from the upper processor 10 to the buffer controller 30. Output

In the AND gate of the buffer controller 30, the broadcasting control signal output from the decoder 20 and the selection control signal for each subprocessor are logically multiplied, respectively, and the buffer in the data buffer unit 40 and the buffer in the memory unit 60 are divided. The enable signal for operating the RAM is output to the data buffer unit 40 and the memory unit 60 in the lower processor.

At this time, the data output from the upper processor 10 is stored in the data buffer unit 40.

Subsequently, when the data buffer unit 40 operating according to the enable signal of the buffer controller 30 outputs the data of the upper processor 10 stored therein, the memory unit 60 in all the lower processor CPUs 70 transmits the data. According to the control of the data of the upper processor 10 output from the data buffer unit 40 is read and transmitted.

Meanwhile, when the upper processor 10 intends to transmit data only to a corresponding lower processor, the data buffer unit outputs only the selection control signal for each lower processor to the AND gate in the buffer controller 30 through the decoder 20. Data of the upper processor 10 stored in the 40 is read by the corresponding lower processor memory unit 60 to be transmitted.

On the contrary, when the lower processor wants to transmit data to the upper processor 10, the lower processor 10 writes the data to the memory of the memory unit 60 in the lower processor so that an interrupt is generated toward the upper processor 10. ) Reads the data from the processor's disk.

As described above, a single upper processor may implement a broadcasting function by transmitting data to a plurality of lower processors at a time by using a buffer control function, thereby improving data transmission efficiency, and thus performance of the system. There is an effect that can be improved.

Claims (5)

A decoder for outputting a control signal for selecting a broadcasting control signal and a lower processor by inputting an address signal and a control signal output from an upper processor, and a decoder for outputting a control signal for selecting the broadcasting processor, and a broadcasting control signal and a selection for each lower processor output from the decoder. A buffer controller for inputting a control signal and outputting an enable or disable signal; and storing data output from the upper processor, and operating according to the enable or disable signal output from the buffer controller to operate the memory in the lower processor. A memory unit configured to store data of the upper processor output from the data buffer unit by operating in response to a data buffer unit output to the unit, an enable or disable signal output from the buffer control unit, and data storage of the memory unit doing An inter-processor data transmission apparatus in a communication system, characterized in that the lower processor consisting of a CPU. The processor of claim 1, wherein the buffer controller comprises a plurality of AND gates for each of the sub-processors, each of which is logically multiplied by inputting the broadcasting control signal and the selection control signal for each sub-processor outputted from the decoder. Inter data transfer device. The lower processor of claim 1, wherein the data buffer unit stores data output from the upper processor and operates according to an enable or disable signal output from the AND gate in the buffer controller to output the data to the memory unit of the lower processor. An inter-processor data transfer device in a communication system, comprising a plurality of buffers for each process. 2. The plurality of disks of claim 1, wherein the memory unit operates according to an enable or disable signal output from the AND gate in the buffer controller to store data of the upper processor output from the buffer in the data buffer unit. An interprocessor data transmission apparatus in a communication system, characterized in that consisting of RAM. 2. The plurality of FIFOs according to claim 1, wherein the memory unit stores data of the upper processor output from the buffer in the data buffer unit by operating according to an enable or disable signal output from the AND gate in the buffer controller. Interprocessor data transmission apparatus in a communication system, characterized in that consisting of.