KR100307318B1 - Mpeg audio bit stream packing aparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an MPEG audio bit stream packing apparatus.

2. The problem to be solved by the invention

In the present invention, in packing the final output bit stream in the unit of byte according to the MPEG audio standard in the MPEG audio encoding process, by using a conventional processor core to perform a bit stream packing by combining several instructions for the bit stream packing To provide a bit stream packing device that can significantly improve the packing speed.

3. Summary of Solution to Invention

The present invention relates to a bit stream packing apparatus for MPEG audio, which receives a number of bits for determining the number of bits to be packed from the outside, and outputs a bit number control signal for controlling the number of bits of packetized data. Bit number control means; Shifting means for shifting data input from the outside according to the bit number control signal; Multiplexing means for multiplexing the lower bits and the upper bits according to the bit number control signal; First storage means for temporarily storing a signal output from the multiplexing means; And logically combining the output signal of the shifting means and the output signal of the first storage means, transferring the logically lower bits and upper bits to the multiplexing means, and outputting the packetized data by packetizing the upper bits. And data packetization means.

4. Important uses of the invention

The present invention is used for MPEG audio and the like.

Description

MPEG audio bit stream packing device {Mpeg audio bit stream packing aparatus}

The present invention relates to MPEG (Mobile Picture Export Group) audio bit stream packing technology, and in particular, by driving a special module that performs bit packing optimized for the architecture and pipeline techniques of the processor. The present invention relates to a bit stream packing apparatus capable of significantly improving a packing speed.

Bit-stream that is finally output during MPEG audio encoding process should be packed in byte unit according to MPEG audio standard. In the device which encodes MPEG audio using existing processor core, bit packing Bit packing is performed by combining several instructions for bit packing, and for this reason, it is impossible to perform bit packing in a short time because many clock cycles are required.

In other words, when MPEG audio is encoded using a conventional processor core, bit packing is performed by combining a plurality of instructions for bit packing, so that many clock cycles are required, resulting in fast bit packing time. There is a problem that is difficult to perform within.

The present invention has been proposed in order to solve the above problems, and in packing the final output bit stream in the unit of byte according to the MPEG audio standard in the MPEG audio encoding process, packing the bit stream using a conventional processor core The purpose of the present invention is to provide a bit stream packing apparatus capable of significantly improving the packing speed by performing bit stream packing by combining several instructions.

1 is a block diagram of an instruction pipeline to which the present invention is applied.

2 is a structural diagram of a whole unit for three-stage pipeline processing to which the present invention is applied;

3 is a block diagram of an embodiment of an MPEG audio bit stream packing apparatus according to the present invention;

Explanation of symbols on the main parts of the drawings

310: number of bits control unit 320: shifter

330: multiplexer 340: register

350: data packetizer 360: packet state output unit

In the present invention for achieving the above object, in the bit stream packing apparatus of MPEG audio, receiving the number of bits to determine the number of bits to be packed from the outside, to control the number of bits of the packetized data Bit number control means for outputting a bit number control signal for the device; Shifting means for shifting data input from the outside according to the bit number control signal; Multiplexing means for multiplexing the lower bits and the upper bits according to the bit number control signal; First storage means for temporarily storing a signal output from the multiplexing means; And logically combining the output signal of the shifting means and the output signal of the first storage means, transferring the logically lower bits and upper bits to the multiplexing means, and outputting the packetized data by packetizing the upper bits. Characterized in that it comprises a data packetization means to. The present invention is characterized in that it further comprises a packet state output means for receiving the bit number control signal output from the bit number control means, and outputs the number of bits to be packetized to the outside.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The processor core used in the present invention processes instructions using a pipelined method and uses a Harvard structure. In addition, registers as well as memory values can be used as a source operand, and a destination operand is a memory-register machine that can use only registers. That is, the address of the data memory is designated in the source operand, the value of the designated address is read, calculated, and stored in the register. To write a value to the memory, you can only use the 'Write' command. The instruction processing is divided into three stages: prefetch, decoding / read, and execution. In other words, the designed processor's pipeline technique is a three-stage pipeline, where the actual processing of the data is at the execution end.

1 is a schematic diagram of an instruction pipeline to which the present invention is applied.

Referring to FIG. 1, first, an instruction fetch step reads instructions from a program memory.

Next, in the decoding and reading step, all the control signals necessary for the execution step are generated by decoding the fetched instruction, and the data memory value is read from the memory if necessary.

Finally, the execute step performs a specified operation, assigns a value to memory, or stores a value in memory in the case of a 'write' instruction. At this time, each pipeline stage is performed in one cycle.

2 is a structural diagram of an entire unit for a three-stage pipeline processing to which the present invention is applied.

As shown in FIG. 2, first, there is a program sequencer for executing a prefetch step, and a control and data address generation for performing a decoding and reading step (DAG: Data Address). There is a generator unit, and finally there is an arithmetic unit (ALU) to process the execution stage. Here, the bit stream packing device is coupled to the execution unit.

In the processor core of this structure, a bit packing is packed for an arbitrary number of bits in one cycle, and if it is packed in half of 16 bits, the following conditions are assumed to be stored in a desired memory.

A) Operated by 'PACK' command.

B) data = Data to be packed and input in units of 1 word (1 word = 16 bits), and all other bits must be filled with 0 (the maximum unit to pack is 16 bits). ).

C) The unit of the packed result is 16, which is a data processing unit of the processor.

D) Designed processors manipulate or write data to memory at the execution end. The 'PACK' instruction should pack and store in the desired memory once the 16 bits are packed. Therefore, when not storing, it can be performed for one cycle of the execution stage. However, if 16 bits are packed and need to be stored, all of them cannot be performed for one cycle. Therefore, in this case, the execution stage should be extended to 2 cycles. In this design, many modifications must be made to the program sequencer and the controller, and the clock per instruction (CPI) is dropped. As the overall performance is reduced, the following method is introduced.

It makes an independent module for 'PACK' instruction and performs packing. When 16 bits are packed, it is saved and saved when the next 'PACK' instruction is executed. Of course, bit packing is also performed at this time. This can be done without increasing the execution stage in two cycles and can be handled with a simple modification of the controller.

3, which will be described later, is a packing device operated by a 'PACK' command, and is packed by the following procedure.

end. reset

(One). Index = 10h (= 16, 5 bits)

(2) Num_Bit = number of bits to be packed (5 bits, having a value from 0 to 16 under the above conditions)

(3) Destination = 0000h

(4) Packed_Result = 0000h

I. packing

(1) Index_Result = Index-Num_Bit (The result is treated as two's complement and recognized as -16 to 15.)

(2) After adding 0000h to the right of the data to expand it to 32 bits, shift the data by 'Index_Result' (shift to the right if 'Index_Result' is positive and to the left if it is negative, but shift to 'Logical'). ).

(3) The result of (2) and '0000h' to the right of 'Destination' and 'OR'.

(4) 'Index Result' is treated as two's complement, so if MSB is 1, it is recognized as negative. At this time, if the MSB of the index result (0) is '0', since 16 bits have not been packed yet, only the upper 16 bits are stored in 'Destination' and the lower 16 bits are discarded. If the MSB of the index result (Index Result) is 1, this indicates that the number of bits currently packed exceeds 16. In this case, since the upper 16 bits of the result of (3) are packed, the upper 16 bits are stored in 'Packed_Result' and '1' is stored in 'Bit_Pack_Write_Status'.

(5) Wait for the next 'Pack' command.

(6) When it meets 'Pack' command, it checks 'Write_Status' and if it is '1', it provides the desired address to data memory address (DMA) and 'Packed_Result' on DMD to perform memory storage (1). To start with.

This is the process of the 'Pack' command operation, the internal structure is shown in FIG.

In this module, 32-bit barrel shifts are required. Using the new barrel shifter for this purpose is inefficient because the barrel shifter takes up a considerable area. Therefore, a shifter in an arithmetic operation unit (ALU) was used. For this purpose, the number of bits to be shifted from the controller decoding the instruction and the "Index_Result" provided by the packing module are connected to the multiplexer (Mux) and the "Num_Bit" of the shifter.

This packed data is special at the system level. The result of this processor core is data in a FIFO for transmitting data to the outside. For the exchange of data between the processor core and the FIFO, we decided to use a constant memory area, which is fixed, so the address range is fixed. Therefore, one address generator for modulo operation is needed. This address generator is named "AR4" as described in the previous address generator, and modulo operation is incremented by 1 between "2800h" and "33FFh".

3 is a block diagram of an embodiment of an MPEG audio bit stream packing apparatus according to the present invention.

As shown in FIG. 3, the MPEG audio bit stream packing apparatus according to the present invention receives a number of bits for determining the number of bits to be packed from the outside, and controls the number of bits for controlling the number of bits of the packetized data. From the bit number control unit 310 for outputting a signal, the shifter 320 for shifting data input from the outside, and the bit number control unit 310 according to the bit number control signal transmitted from the bit number control unit 310. According to the transmitted bit number control signal, the multiplexer 330 for multiplexing the inputted lower bits and the upper bits, the register 340 for temporarily storing the signal output from the multiplexer 330, and the shifter ( Data obtained by logically combining the output signal of 320 and the output signal of register 340, transferring the logically lower bits and the upper bits to the multiplexer 330, and packetizing the upper bits by packetizing the upper bits. It includes a data packetizer 350 for outputting.

The present invention further includes a packet state output unit 360 which receives a bit number control signal output from the bit number controller 310 and outputs the number of bits to be packetized to the outside.

The bit number control unit 310 temporarily subtracts the output signal of the subtractor 311 and the subtractor 311 outputting the bit number control signal by subtracting the number of bits transmitted from the index register 312 from the number of bits input from the outside. The index register 312 stores and outputs the result to the subtractor 311.

The data packetizer 350 packetizes the logical sum gate 351 for ORing the output signal of the shifter 320 and the output signal of the register 340, and the higher bits that are OR'ed by the logical sum gate 351. And a packet data output unit 352 for outputting the normalized data.

The operation of the MPEG audio bit stream packing apparatus of the present invention having the structure as described above will be described in detail as follows.

In the initial state, the subtractor 311 outputs the number of bits inputted from the outside without being subtracted and transmits the same to the shifter 320 and the multiplexer 330. Accordingly, the data packetizer 350 subtracts the subtractor 311. Packetize the upper bits as many as the number of bits passed through.

When the initial state passes, the number of bits output through the subtractor 311 is temporarily stored in the index register 312 and then transferred to the subtractor 311, which is then subtracted from the external index register at the current number of bits. Subtract the signal from 312.

In this case, the signal output from the subtractor 311 is a bit number control signal for controlling the number of bits of the packetized data, and is transmitted to the shifter 320, the multiplexer 330, and the packet state output unit 360.

Subsequently, the shifter 320 shifts data input from the outside according to the transmitted bit number control signal to the logic sum gate 351.

The multiplexer 330 multiplexes the upper bits and the lower bits transmitted from the logic sum gate 351 according to the transmitted number control signal to the register 340.

On the other hand, the packet state output unit 360 receives the bit number control signal and transfers the number of bits to be packetized to an external device, such as a CPU, so that the user can know the number of bits of the current packetized data.

In addition, the OR gate 351 performs OR on the multiplexed signal transferred through the shifter 320 and the data shifted through the register 340 and outputs the OR bits and the OR bits that are OR.

In this way, the output upper bits and lower bits are transmitted to the multiplexer 330, and the upper bits are transmitted to the packet data output unit 352 to be packetized.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, according to the present invention, by packing a plurality of instructions for bit stream packing using an existing processor core, bit stream packing is performed on a byte stream, which is finally output in the MPEG audio encoding process, by byte unit, thereby remarkable packing speed. There is an effect that can be improved.

Claims (4)

In the bit stream packing apparatus of MPEG audio, Bit number control means for receiving a bit number for determining the number of bits to be packed from the outside and outputting a bit number control signal for controlling the number of bits of the packetized data; Shifting means for shifting data input from the outside according to the bit number control signal; Multiplexing means for multiplexing the lower bits and the upper bits according to the bit number control signal; First storage means for temporarily storing a signal output from the multiplexing means; And Logically combining the output signal of the shifting means and the output signal of the first storage means, transferring the logically lower bits and upper bits to the multiplexing means, and outputting the packetized data by packetizing the upper bits Data packetization means Bit stream packing apparatus of the MPEG audio comprising a. The method of claim 1, Packet state output means for receiving the bit number control signal output from the bit number control means and outputting the number of bits to be packetized to the outside Bit stream packing apparatus of the MPEG audio further comprising. The method according to claim 1 or 2, The bit number control means, Subtraction means for subtracting the number of bits transmitted from the second storage means from the number of bits input from the outside and outputting the bit number control signal; And The second storage means for temporarily storing the output signal of the subtraction means and outputting the output signal to the subtraction means; Bit stream packing apparatus of the MPEG audio comprising a. The method of claim 3, wherein The data packetization means, Logical sum calculating means for ORing the output signal of the shifting means and the output signal of the first storage means; And Packet data output means for outputting the packetized data by packetizing the upper bits that are logically joined by the logical sum means. Bit stream packing apparatus of the MPEG audio comprising a.