KR100305871B1 - Base sector device for multi-sector - Google Patents

Abstract

According to the present invention, a multi-sector base station apparatus having a simple DU configuration can be guaranteed by using an SE for switching three sectors to multiple sectors in a base station apparatus of a wireless communication system. The present invention relates to a multi-sector base station apparatus using an SE that can reassign the CE in a flexible manner according to the amount of calls in the sector. Handoff between multiple sectors by switching forward data of the supported CE to any three sectors among the multi-sectors, and switching backward data from the multi-sectors to the CE supporting three sectors of α, β, and γ. Are all handled as soft handoffs, and the SE can switch the forward data of the CE to any sector of the multi-sector and output it. It allows the allocation of more CEs to sectors and less CEs to sectors with less traffic.In this way, the use of SEs enables efficient handoffs between soft sectors across all sectors. Since the base station device can be configured, it can be applied to the base station device of the microcell system for the future wireless multimedia information service, and the technical competitiveness can be improved. As a conventional method, multiple sectors can be supported by one DU without requiring a plurality of DUs. Therefore, there is a cost reduction effect when implementing a multisector base station system.

Description

Multisector Base Station Device Using Switch

The present invention is a base station apparatus of a wireless communication system, using a switch element (switch element; hereinafter referred to as "SE") for switching three sectors to multiple sectors (Digital Unit; By implementing a multi-sector base station apparatus having a simple configuration of DU ', it is possible to ensure softer handoff between sectors, and according to the call volume in each sector (Channel element; A multisector base station apparatus using an SE that can be reassigned in a flexible manner.

Future wireless communication systems are expected to support a variety of high-speed multimedia information services, including high-speed data and video, as well as voice services.

However, since the frequency resources of the wireless communication system are limited, in order to accommodate the high-speed multimedia information service, a large capacity of the wireless channel is required above all, and accordingly, a micro cell that can efficiently reuse the limited frequency resources ( The introduction of the concept of cell radius (hundreds of meters) and Pico Cell (cell radius: several tens of meters) is emerging as an unavoidable issue.

Currently, microcells have been developed and used to solve coverage problems of base stations or to solve shaded areas such as underground spaces or indoors.

Since the cell size of the microcell system is significantly smaller than the cell size of a conventional macro cell system, frequent handoffs occur between base stations, thereby degrading the call quality. A hand occurring between base stations of the digital cellular system Off is referred to as soft handoff, which means that both base stations are handed off with CE assignment, resulting in waste of channel resources and a new base station and channel to be set up.

On the other hand, softer handoff is a handoff that occurs between sectors of a three-sector base station and does not require a separate CE allocation, and handoff processing time is also less than that of soft handoff.

Therefore, in order to realize a microcell system that requires a large number of small cells for future high-speed multimedia information service, it is possible to design the system so that handoff between each cell proceeds to softer handoff and centrally manage multiple cells. System development technology is required.

Meanwhile, the base station apparatus of the conventional digital cellular system can design only up to three sectors of alpha (α), beta (β), and gamma (γ), thereby supporting a multisector, that is, a base station apparatus of a microcell concept. In order to design, as shown in FIG. 1, two 1FA (Frequency Assignment) three sector DUs are combined to have the same FA so that a six sector base station apparatus is implemented.

That is, a configuration in which two base station apparatuses having the same FA exist in one base station apparatus can be used as it is without changing the hardware and software of the conventional system. The disadvantage of using the unit is that the system implementation is expensive.

In addition, since DU # 0 (10) is responsible for sectors # 0 to sector # 2 and DU # 1 (20) is responsible for sectors # 3 to sector # 5, the mobile station is located within the sectors of sectors # 0 to sector # 2. When moving, or when moving within the region of sectors # 3 to sector # 5, a soft handoff occurs, but from one of sectors # 0 to sector # 2 to any of sectors # 3 to sector # 5 If you move, a soft handoff occurs.

In the conventional multi-sector base station apparatus in which two three-sector base station apparatuses are integrated so as to have the same FA, the soft handoff between sectors managed by different DUs is as described above. Compared to the off, the processing time is long and the utilization efficiency of channel resources is lowered.

The present invention has been made to solve the above problems, and its object is to implement a wireless communication system of a microcell concept supporting multiple sectors, the forward data of the CE supporting three sectors of α, β, γ The multi-sector base station apparatus having a single DU using a SE for switching the output to multiple sectors and the reverse data from the multi-sectors to switch the CE to three sectors is implemented. It is to provide a multi-sector base station apparatus using an SE that can guarantee data handoff and to efficiently use channel resources by reallocating CE according to the call volume in each sector.

1 is a block diagram of a six-sector base station apparatus implemented using a conventional three-sector base station apparatus.

2 is a block diagram of a multi-sector base station apparatus using a switch according to the present invention;

3 is a view showing a connection state between a channel element and a switch for a pilot / synchronous / access channel and a paging channel;

4 is a detailed block diagram of a switch in a multi-sector base station apparatus according to the present invention;

5 is a block diagram of a forward switch in the switch and the switch control unit according to the present invention;

6 is a view showing a control command value of a control register in a switch control unit for controlling the forward switch unit;

7 is a view showing an output timing diagram of forward data in a channel element according to the present invention;

8 is a block diagram of the reverse switch unit and the switch control unit in the switch according to the present invention;

9 is a block diagram of a digital combiner unit in a switch according to the present invention;

10 is a block diagram of a serial adder in a digital combiner according to the present invention;

11 is a block diagram of a parity error detection unit in a digital combiner unit according to the present invention;

12 is a block diagram of a parity interrupt generation unit in a digital combiner unit according to the present invention;

Fig. 13 is a block diagram showing a timing generator in a digital combiner unit according to the present invention.

<Description of the symbols for the main parts of the drawings>

200: DU 202-0 to 202-9: CDCA # 0 to CDCA # 9

210: control unit 220-0 to 220-11: CE # 0 to CE # 11

230-0 to 230-11: SE # 0 to SE # 11 240: Forward switch

241: Input latch section 242 to 244: 4-bit three-phase buffer section

250: switch control unit 251: SE control unit

252: control register 253 to 255: decoder

260: reverse switch 261: input latch

262 to 267: 8-bit three-phase buffer section 268: Output latch section

270: digital combiner portion 280: serial adder portion

290: parity error detector 300: parity interrupt generator

310: parity generator 320: timing generator

The multi-sector base station apparatus using the SE of the present invention for achieving this purpose, switching the forward data of the CE supporting three sectors of α, β, γ through the SE corresponding to each CE provided in one DU Outputs to any three sectors among the multi-sectors, and switches backward data from the multi-sectors to the CE supporting three sectors of α, β, and γ, so that all handoffs between the multi-sectors are treated as softer handoffs. By using SE, the forward data of CE can be switched and output to any sector among multiple sectors, so that more CE can be allocated to high-traffic sectors and less CE can be allocated to low-traffic sectors. It is characterized by.

Hereinafter, the configuration and operation of a multi-sector base station apparatus using SE according to the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, a multisector base station apparatus having six sectors will be described as an example.

FIG. 2 is a block diagram of a multi-sector base station apparatus using SE according to the present invention, in which an RF signal transmitted from a mobile station (not shown) located in each sector area is converted into an IF signal or an IF signal input from a DU. After converting an RF signal into a baseband signal and converting an RF signal into a baseband signal, which is converted into an RF signal and transmitted to a mobile station (hereinafter referred to as 'RF'), the RF unit 100 DU (200) and the base station apparatus for converting the signal and the data signal or the base station processing the voice signal and the data signal input from the control station 600, and then converts the IF signal to the RF unit 100 to output to the RF unit 100; A base station matching network (BTS Control Processor) for controlling the operation of the configuration block (hereinafter referred to as "BCP") 300, and the base station matching network (BTS Interconnection Network) for performing wireless matching with the control station 600; , 'BIN' 400, and a Global Position System (hereinafter, referred to as GPS) 500 for supplying a reference clock to each component block of the base station apparatus.

The DU 200 converts an IF signal transmitted from the RF unit 100 into a baseband signal or a baseband and IF signal conversion card assembly (baseband & IF) for converting a baseband processed signal from the CDCA to be described later into an IF signal. Conversion card assembly (hereinafter referred to as 'BICA') # 0 to BICA # 5 (201-0 to 201-5) and the basis converted from the BICA # 0 to BICA # 5 (201-0 to 201-5) Converts a band signal into respective voice signals and data signals or baseband processes the voice signals and data signals inputted through SRCA to be described later and outputs them to the BICA # 0 to BICA # 5 (201-0 to 201-5). CDCA Digital Channel card Assembly (hereinafter referred to as 'CDCA') # 0 to CDCA # 9 (202-0 to 202-9), and the BICA # 0 to BICA # 5 (201-0 to 201-5) Shelf control & routing card assembly (hereinafter referred to as SRCA) for controlling and managing the CDCA # 0 to CDCA # 9 (202-0 to 202-9). (20 3) consists of.

In addition, the CDCA # 0 (202-0) is a control unit 210 for controlling the operation of each component block of the CDCA # 0 (202-0) and CE # 0 to CE # for transmitting and receiving forward and reverse data 11 (220-0 to 220-11) and the forward data of three sectors α, β, and γ outputted through the respective CE # 0 to CE # 11 (220-0 to 220-11) are switched to BICA #. Reverse direction input to any three sectors of multiple sectors through 0 to BICA # 5 (201-0 to 201-5) or input from multiple sectors through BICA # 0 to BICA # 5 (201-0 to 201-5) SE # 0 to SE # 11 (230-0 to 230-11) for switching data and outputting to CE # 0 to CE # 11 (220-0 to 220-11) supporting three sectors of α, β, and γ. It is composed.

Here, the CE # 0 to CE # 11 (220-0 to 220-11) have at least one pilot and sync for each multi-sector for signaling for call setup, handoff, location registration, and the like. ), Access and paging channels must be allocated.

In this case, the pilot / synchronous / access channel may be allocated to one CE, while the paging channel may be allocated to a separate CE.

Since at least one of these channels must be fixed for each multisector, a fixed switch value is set at SE during system initialization. The fixed value does not need to be changed during system operation.

As shown in FIG. 2, when there are 6 sectors and there are 6 sectors, an SE which allocates one CE for pilot / synchronous / access and one CE for each sector, and switches the data of each CE, The fixed switch value is set to be connected as shown in FIG. 3.

FIG. 4 is a block diagram of SE, that is, SE # 11 (230-11) according to the present invention, and shows four bits of forward data for three sectors α, β, and γ from CE # 11 220-11. A forward switch unit 240 for receiving the input and selectively switching according to a control command of the switch controller to output forward data for outputting to any three sectors of the multi-sector, and the controller 210 in the CDCA # 0 202-0. Switch control unit 250 for controlling the switching operation of the forward switch unit 240 and the reverse switch unit according to the control command of the BICA # 0 to BICA # 5 (201-0 to 201-5) for each of the multi-sector The reverse switch unit 260 which receives 8-bit reverse data of the control unit and selectively switches according to a control command of the switch controller 250 and outputs the same to CE # 11 220-11 that supports three sectors of α, β, and γ. And, forward data output from the forward switch unit 240 and the forward direction output from the SE # 10 (230-10) of the previous stage And a digital combiner unit 270 which adds data and outputs the result of the addition to the BICA # 0 to BICA # 5 (201-0 to 201-5).

Here, the SE of the configuration used in the present invention should be able to perform the following functions essentially.

end. The forward output of the CE configured for three sectors α, β, and γ should be able to be connected to any three sectors of the six sectors according to the control command of the controller 210.

I. It should be possible to connect the reverse inputs from six sectors to a CE consisting of three sectors (α, β, γ).

All. In order to replace the combiner function for the forward three sectors (α, β, and γ) performed in the conventional CE, a six-sector combiner should be incorporated.

la. The six-sector combiner must be able to check parity for error detection of the combined data.

hemp. The parity error should be reported to the controller 210.

bar. Do not transmit the combined data with the parity error.

four. In order to receive the forward data from the CE, the forward input timing standard corresponding to the transmission timing standard provided by the CE must be provided.

Ah. In order to deliver the switched forward data to the BICA, the forward output timing of the same standard as the timing that the conventional CE delivers to the BICA must be satisfied.

character. In order to receive reverse data from BICA, it is necessary to have a reverse input timing standard that matches the forwarding timing standard provided by BICA.

car. In order to deliver the switched reverse data to the CE, it is necessary to satisfy the reverse output timing of the same specification as the timing that the conventional BICA delivers to the CE.

5 is a block diagram of the forward switch unit 240 and the switch control unit 250 in the SE according to the present invention, the forward switch unit 240 is 4 each of the three sectors α, β, γ output from the CE Input latch unit 241 for inputting and latching forward data of bits (Even and Odd bits) for each of the I and Q channels, and a control command of the switch controller 250. Accordingly, the four-bit forward data of three sectors α, β, and γ output from the input latch unit 241 is selectively switched to output forward data for outputting to any three sectors of six sectors. Four-bit three-phase buffers 242 to 244 output to the digital combiner unit 270. Each of the four-bit three-phase buffer units 242 to 244 is output from the input latch unit 241. Control name of the switch controller 250 by inputting 4-bit forward data for each of three sectors α, β, and γ The selection is made in accordance with the switching to the six four-bit three-phase buffer (242-0~5,243-0~5,244-0~5) for outputting a forward data.

The switch controller 250 outputs a control command for controlling a switching operation of the SE according to a control signal output from the controller 210 through an address bus, and the SE controller (251). A control register 252 for temporarily storing the control instructions of 251, and six four-bit three-phase buffers in the four-bit three-phase buffer units 242 to 244 by decoding the control instructions stored in the control register 252. And decoders 253 to 255 which output control signals for operating (242-0 to 5, 243-0 to 5,244-0 to 5).

In this case, the control register 252 requires three bits of control data for each sector in order to distribute the forward data into six sectors for each of three sectors of α, β, and γ. The number consists of 9 bits in total.

FIG. 6 is a view showing control command values of the control register 252 for controlling the switching operation of the 4-bit three-phase buffers 242-0 to 5, 243-0 to 5,244-0 to 5 in the forward switch unit 240. FIG. As the 3-bit control data, the connection information of the forward switch unit 240 can be known. In the present invention, the number of sectors connected to α, the number of sectors connected to β, and the number of sectors connected to γ If is equal, do not connect even if the connection information is a valid value.

Meanwhile, a CE called a Cell Site Modem has a 12-bit forward direction for each rising edge of the system clock of 19.6608 MHz synchronized with the even clock as shown in the timing diagram shown in FIG. Since the data is output, the input latch unit 241 in the forward switch unit 240 should also be able to receive 12-bit forward data output from the CE in synchronization with the system clock.

In this case, the input latch unit 241 in the forward switch unit 240 is such that the input setup-time and hold-time are smaller than the data output setup-time and hold-time of CE. Choose.

That is, considering that the setup-time of the output data of the CE is at least 15ns and the hold-time is at least 8ns, the setup time of the input data is less than 15ns and the hold-time is less than 8ns.

8 is a block diagram of the reverse switch unit 260 and the switch control unit 250 in the SE according to the present invention. Since the switch control unit 250 has been described above, the reverse switch unit 260 is omitted through the BICA. An input latch unit 261 that receives and latches 8-bit reverse data of each of the outputted multi-sectors, and each of the 8-bit outputted from the input latch unit 261 according to a control command of the switch controller 250. 8-bit three-phase buffer sections 262 to 267 for selectively switching reverse data and outputting three sector reverse data for?,?, And?, And?,? Output from the 8-bit three-phase buffer sections 262 to 267. and an output latch unit 268 which latches three sector reverse data for each gamma and outputs the CE to support three sectors of alpha, beta, and gamma, respectively. Each of the 8 sectors of reverse data for each multi-sector output from the input latch unit 261 Three 8-bit three-phase buffers 262-0 to 2,263 which are inputted and selectively switched according to a control command of the switch controller 250 to output reverse data for each of three sectors of α, β, and γ to the output latch unit 268. -0-2,264-0-2,265-0-2,266-0-2,267-0-2).

In this case, the input latch unit 261 receives 8 bits of data from each BICA in synchronization with the rising edge of the system clock, and the output latch unit 268 is also switched in synchronization with the system clock. Reverse sector data for three sectors of gamma is output to CE.

9 is a block diagram of the digital combiner unit 270 in the SE according to the present invention. The multi-sector forward data output from the forward switch unit 240 and the serial data added from the previous stage SE are added. An adder 280, a parity error detector 290 for detecting whether there is a parity error in the forward data output from the previous stage SE, and a controller 210 if an error is detected in the parity error detector 290; A parity interrupt generator 300 for reporting to the parity, a parity generator 310 for adding a parity bit to the 16th bit of the forward data output from the serial adder 280, and a digital combiner 270. Each component block includes a timing generator 320 that provides timing for operation.

FIG. 10 is a block diagram of the serial adder 280 of the digital combiner unit 270 according to the present invention. FIG. 10 is a diagram illustrating the forward data of the multi-sector I channel or Q channel output from the forward switch unit 240. A first AND gate 281 which ANDs the signal Even and the enable signal according to the block signal output from the parity error detector 290, and the odd signal Odd of the forward data. And a second AND gate 282 for ANDing the enable signal, a third AND gate 283 for ANDing the enable signal among the forward data output from the previous stage SE, and the timing generator. A first inverter 286 for inverting the timing control signal 1 output from the 320 and a second inverter 287 for inverting the timing control signal 2 output from the timing generator 320; Forward forward output from SE of previous stage A fourth AND gate 284 for performing an AND operation on the odd signal, the enable signal, and a timing control signal 1 inverted by the first inverter 286, and a timing control signal 2 inverted by the second inverter 287. Full adder that adds the fifth and gate 285 for ANDing the feedback carry signal and the output signals of the first to fourth AND gates 281 to 284 divided by even and odd. 288 and a D flip-flop 289 which latches the sum output of the full adder 288 and outputs it to the BICA according to the system clock.

Since one serial adder 280 exists for each of the I and Q channels for every six sectors, a total of 12 are required.

In the serial adder 280 configured as described above, the forward data of the forward switch unit 240 and the forward data of the previous SE are added. Both of these data are in 2's complement form. It has a length of 16 bits, and two bits of even and odd are output in one system clock tick for each sector, so that one data packet is transmitted every eight system clock ticks.

In this way, since data is serially transmitted in units of 2 bits, the serial adder 280 may be configured by using a 2-bit full adder for each of 6 sectors.

11 is a block diagram of the parity error detection unit 290 of the digital combiner unit 270 according to the present invention, and is a configuration for determining whether there is an error in the forward data output from the digital combiner unit in the previous SE. We use odd parity detection and use exclusive-OR logic.

That is, the parity error detection unit 290 is an even signal of an enable signal for operating an exclusive-OR gate to which the output signal of the first D flip-flop is fed back and the forward data output from the previous SE. An exclusive OR gate 291 exclusively ORing the signal Even and the odd signal Odd, an inverter 292 for invertering the enable signal, an enable signal inverted by the inverter 292, and The OR gate 293 for ORing the enable signal for operating the parity error detector 290 and the output signal of the exclusive OR gate 291 are latched, and the exclusive OR gate ( Enabled by the first D flip-flop 294 for feedback output to the enable signal of 291 and the timing control signal 1 output from the timing generator 320 to output the OR gate 293. A second D flip-flop 295 that latches an output signal and outputs a parity error detection signal according to the system clock, and a block according to the system clock when the parity error detection signal is received from the second D flip-flop 295. The block signal generator 296 generates a block signal as an enable signal of the serial adder 280.

The parity error detection unit 290 also requires a total of 12 because there is one for each of the I channel and the Q channel for every six sectors.

12 is a block diagram of the parity interrupt generator 300 of the digital combiner unit 270 according to the present invention. The inverter 301 inverts the parity error detection signal output from the parity error detector 290. Initialize the first AND gate 302 and the parity interrupt generator 300 to logically multiply the parity error detection signal inverted by the inverter 301 and the timing control signal 0 output from the timing generator 320. A 7-bit counter 303 for counting a system clock by operating according to a clear signal and a timing control signal 1 output from the timing generator 320, and an output signal of the 7-bit counter 303; A second AND gate 304 for ANDing the enable signal for operating the parity error detector 290, an output signal of the first AND gate 302, and an inverted output signal of the second AND gate 304. On And the D flip-flop 305 to latch and output the parity error detection signal according to a system clock, and to enable the output signal of the D flip-flop 305 and the parity interrupt generator 300 to operate. The OR gate 306 outputs an interrupt signal to the controller 210 by ORing the signals.

Since the parity interrupt generator 300 also has one for each of the I channel and the Q channel for every six sectors, a total of 12 are required.

On the other hand, the parity generator 310 is a block for adding the odd parity to the 16th bit of the forward data added by the serial adder 280, which is used for error checking of the forward data in the SE of the next stage. .

FIG. 13 is a block diagram of the timing generator 320 of the digital combiner unit 270 according to the present invention. The system clock is counted in synchronization with the even clock, and the control signal is controlled for every system clock based on eight system clocks. The digital combiner unit generates timing control signals 1 to 7 according to a modulo-8 down counter 321 for outputting the control signal and a control signal output from the modulo-8 down counter 321. And a comparator 322 provided to each component block 270.

That is, all of the configuration blocks in the digital combiner unit 270 operate based on the even clock as the input / output data packets are aligned with the even clock, and at this time, the even clock is asserted based on the assertion. Since one data packet is transmitted every 8 system clocks, a timing reference provided by the timing generator 320 is needed to determine which bit of the data packet is presently transmitted.

Referring to the operation of the multi-sector base station apparatus according to the present invention configured as described above are as follows.

First, a case in which forward data is transmitted from a base station supporting multi-sector to a mobile station will be described. The DU 200 of the base station may control the voice signal and the data signal input from the control station 600 under the control of the BCP 300. The associated traffic channel is outputted through CDCA # 0 to CDCA # 9 (202-0 to 202-11) 9 through the routing function of the SRCA 203.

Subsequently, in CE # 0 to CE # 11 (220-0 to 220-11) of CDCA # 0 to CDCA # 9 (202-0 to 202-11) 9, forward data of the traffic channel, that is, α, β, Each 4-bit and 12-bit forward data for three sectors of gamma is subjected to baseband processing and output to BICA # 0 to BICA # 5 (201-0 to 201-5).

Then, in BICA # 0 to BICA # 5 (201-0 to 201-5), the baseband processed forward data is converted into an IF signal, and then the RF unit 100 converts the IF signal into an RF signal and multisectors. Transmit to the mobile station located at.

At this time, in the CDCA # 0 (202-0), switching of SE # 0 to SE # 11 (230-0 to 230-11) connected to each of CE # 0 to CE # 11 (220-0 to 220-11). Through operation, forward data of each of the three sectors α, β, and γ output from CE # 0 to CE # 11 (220-0 to 220-11) can be transmitted to a mobile station located in any three sectors among six multi-sectors. Make sure

That is, according to the control command of the control unit 210 in the CDCA # 0 (202-0), the switch control unit 250 in the SE # 11 (230-11) receives the SE through the control register 252 and the decoders 253 to 255. A control command is outputted to the forward switch unit 240 in # 11 (230-11), and a total of 18 buffers of the 4-bit three-phase buffer units 242 to 244 in the forward switch unit 240 are output according to the control command. (242-0 to 5,243-0 to 5,244-0 to 5) are operated in switching, and a total of three sectors are outputted from the CE # 11 220-11 latched to the input latch portion 241 in the forward switch portion 240. By switching and selecting 12 bits of forward data, a total of 24 bits of forward data is output to the digital combiner unit 270.

Therefore, the digital combiner unit 270 adds the forward data output from the forward switch unit 240 and the forward data output from the previous stage SE # 10 230-10 through the serial adder 280. The addition result is output to BICA # 0 to BICA # 5 (201-0 to 201-5).

In the digital combiner 270, the parity error detector 290, the parity interrupt generator 300, the parity generator 310, and the timing generator 320 are input to the serial adder 280. It detects whether there is an error in the forward data, and notifies the control unit 210 if there is an error, and does not add the forward data and transmit it.

That is, in the operation of the serial adder 280, since the 16th bit is a parity bit, the timing control signal 1 output from the timing generator 320 at the time of addition is set low to add the input value to 0. When the first bit value is added, the timing control signal 0 output from the timing generator 320 is set high to reset the carry input value of the fifth and gate 285 to 0. After that, it is added.

When an error is detected by the parity error detector 290, the enable signal is set to 0 so as to satisfy a blocking condition, and the input of the serial adder 280 is set to 0 to generate a serial adder 280. Output 0.

When the parity error detection unit 290 detects a parity error, the parity error detection unit 290 outputs a block signal so that the block signal generation unit 296 can ignore as many as 64 packets from the time when the parity occurs, and is input to the block signal generation unit 296. If a parity error occurs in any one of the I and Q channels when the selection signal is high, block both the I and Q channels. If the selection signal is low, the parity error in the I and Q channels is blocked. Block only channels where

The parity interrupt generator 300 does not generate a parity error interrupt even when a parity error occurs when the enable signal, which is an input signal of the OR gate 306, is high, and is an input signal of the second AND gate 304. If the enable signal is low, do not generate a parity error interrupt.

Next, a case in which reverse data is transmitted from a mobile station located in multiple sectors to a base station supporting multiple sectors, the DU 200 of the base station inputs an RF signal transmitted from the mobile station under the control of the BCP 300. The IF unit is converted into an IF signal through the RF unit 100, and then the IF signal is converted into a baseband signal through BICA # 0 to BICA # 5 (201-0 to 201-5), and CDCA # 0 to CDCA # 9 ( 202-0 to 202-9).

Subsequently, in each of CE # 0 to CE # 11 (220-0 to 220-11), each of 8 bits for six multi-sectors output from the BICA # 0 to BICA # 5 (201-0 to 201-5) is output. In addition, the reverse data of the baseband signal of 48 bits in total is converted into a voice signal and a data signal, and outputted to the control station 600 through the SRCA 203.

At this time, in the CDCA # 0 (202-0), switching of SE # 0 to SE # 11 (230-0 to 230-11) connected to each of CE # 0 to CE # 11 (220-0 to 220-11). Α, which supports reverse data of each of six sectors outputted from BICA # 0 to BICA # 5 (201-0 to 201-5) through CE # 0 to CE # 11 (220-0 to 220-11). Connect them to 3 sectors of β and γ.

That is, according to the control command of the control unit 210 in the CDCA # 0 (202-0), the switch control unit 250 in the SE # 11 (230-11) receives the SE through the control register 252 and the decoders 253 to 255. A control command is outputted to the reverse switch unit 260 in # 11 (230-11), and a total of 18 buffers of the 8-bit three-phase buffer units 262 to 267 in the reverse switch unit 260 are output according to the control command. BICA # 0 (262-0 to 2,263-0 to 2,264-0 to 2,265-0 to 2,266-0 to 2,267-0 to 2) is switched and latched to the input latch portion 261 in the reverse switch portion 260. By switching the 6 sectors of 48 bits of reverse data to be output from BICA # 5 (201-0 to 201-5), the output latch section (24 bits of reverse data for 3 sectors of α, β, and γ) is selected. 268) to CE # 11 (220-11).

As described above, the present invention can switch the forward data of the CE supporting three sectors of α, β, and γ to more than one multisector, and the reverse data from the multi-sector to three sectors through the SE. .

Meanwhile, in order to satisfy the IS-95 standard, the base station apparatus must deliver a forward data stream aligned with a universal time (UT). The following delay exists in the forward channel.

T _{pp2s ― dly} : Delay with even clock input to PP2S pin of UT and CE modem chip.

T _{mod ― dly} : Processing delay of CE modem chip.

T _{dist ― dly} : The delay caused by the actual chipcasting of the modem chip output at the antenna.

As above, the total delay in the forward channel is T _{pp2s ― dly} + T _{mod ― dly} + T _{dist ― dly} To compensate for this delay, the CE forwards the forward data stream by advancing the total delay in time.

As described above, to compensate for the delay, the CE advances the timing of the encoder section in units of a power control group (1.25ms), which allows TX_PCG_ADV (6 bits) to advance the time by up to 80ms-8PN chips. Registers, TX_8CHIP_ADV (8-bit) registers to advance the timing of encoder sections in 8PN chips (6.51μs), up to 1PCG-8PN chips, and 3 transmit sections of α, β and γ in CE Transmit Section) Sn_CHIPX2_ADV (10-bit) register that can advance the timing in 1 / 2PN chip (4.07s) unit, and the timing of the transmitter adder in 1 / 8PN chip (0.10μs) unit up to 3 / 8PN It has a number of registers, such as the TX_PHASE (2-bit) register, which can advance the chip time.

In the present invention, since three sectors of α, β, and γ can be connected to each other through six sectors through SE, the total delay value for 3 × 6 = 18 paths ( T _{pp2s ― dly} + T _{mod ― dly} + T _{dist ― dly} ) And store the value to be set in the register as a database to compensate for this.

Then, at initial setup or when the connection of the switch is changed, the timing adjustment caused by the addition of the SE is solved by reading the corresponding timing adjustment value from the database and downloading it to the timing adjustment register of the CE according to the switch connection to be changed.

As described above, the present invention can construct an efficient multi-sector base station apparatus capable of softening handoff between all sectors by using an SE capable of switching three sectors to multiple sectors. Applied to the base station apparatus of the microcell system for information service, the technical competitiveness can be improved, and the cost can be reduced when the multi-sector base station system is implemented because a single DU can support multiple sectors without requiring multiple DUs as in the prior art. Has the effect of.

Claims (11)

In the base station apparatus of the wireless communication system comprising the RF unit 100, DU 200, BCP 300, BIN 400, GPS 500, etc. CDCA in the DU 200 composed of BICA # 0 to BICA # 5 (201-0 to 201-5), CDCA # 0 to CDCA # 9 (202-0 to 202-9), and SRCA 203 # 0 to CDCA # 9 (202-0 to 202-11) control the operation of each component block in CDCA # 0 to CDCA # 9 (202-0 to 202-9), and the forward direction. And? (CE) output through CE # 0 to CE # 11 (220-0 to 220-11) for transmitting and receiving reverse data, and each of CE # 0 to CE # 11 (220-0 to 220-11). Forward and forward data of three sectors of β, γ are output to any three sectors of multiple sectors through BICA # 0 to BICA # 5 (201-0 to 201-5), or BICA # 0 to BICA # 5 (201-0) SE # 0 to SE # 0 to CE # 11 (220-0 to 220-11) supporting 3, sectors of α, β, and γ by switching reverse data inputted from multiple sectors through 201-5). A multisector base station apparatus using a switch, comprising: SE # 11 (230-0 to 230-11). The method of claim 1, wherein the SE # 0 to SE # 11 (230-0 to 230-11) are divided into three sectors α, β, and γ from the CE # 0 to CE # 11 (220-0 to 220-11). Forward switch unit 240 for receiving the four-bit forward data for each and outputs the forward data for output to any three sectors of the multi-sector by selectively switching according to the control command of the switch controller, and the CDCA # A switch control unit 250 for controlling the switching operation of the forward switch unit 240 and the reverse switch unit according to a control command of the control unit 210 in 0 to CDCA # 9 (202-0 to 202-9), and the BICA #; Receives 8-bit reverse data of multiple sectors from 0 to BICA # 5 (201-0 to 201-5) and selectively switches according to a control command of the switch control unit 250 to switch 3, α, β, and γ sectors. Reverse switch unit 260 for outputting to CE # 0 to CE # 11 (220-0 to 220-11) that support the data, and forward data output from the forward switch unit 240 and the And a digital combiner unit 270 for adding forward data output from the SE of the stage and outputting the addition result value to the BICA # 0 to BICA # 5 (201-0 to 201-5). Multisector base station apparatus using a switch. The method of claim 2, wherein the forward switch unit 240, the input latch unit 241 for inputting and latching each of four bits of forward data for the three sectors α, β, γ output from the CE, and Α, β, γ 3 composed of 4-bit three-phase buffers 242-0 to 5, 243-0 to 5,244-0 to 5 and outputted from the input latch unit 241 according to a control command of the switch controller 250. A plurality of 4-bit three-phase buffers for outputting, to the digital combiner unit 270, forward data for selectively switching each 4-bit forward data for a sector and outputting the output to any three sectors of six sectors. A multisector base station apparatus using a switch, characterized by comprising units (242 to 244). The SE control unit 251 of claim 2, wherein the switch control unit 250 outputs a control command for controlling a switching operation of the SE according to a control signal output from the control unit 210 through an address bus; A control register 252 for temporarily storing a control command of the SE control unit 251 and a 4-bit 3-phase in each of the 4-bit three-phase buffer units 242 to 244 by decoding the control command stored in the control register 252. And a decoder (253 to 255) for outputting a control signal for operating the buffers (242-0 to 5, 243-0 to 5,244-0 to 5). The method of claim 2, wherein the reverse switch unit 260, an input latch unit 261 for receiving and latching 8-bit reverse data of each of the multi-sectors outputted through the BICA, and each 8-bit three-phase buffer ( 262-0 to 2,263-0 to 2,264-0 to 2,265-0 to 2,266-0 to 2,267-0 to 2, and are output from the input latch unit 261 according to a control command of the switch controller 250. A plurality of 8-bit three-phase buffer units 262 to 267 for selectively switching each 8-bit reverse data to output three sector reverse data for α, β, and γ, and the eight-bit three-phase buffer units 262 to 267. Multi-sector using a switch, characterized in that consisting of an output latch unit 268 for latching the 3-sector reverse data for each of the α, β, γ output to the CE supporting the three sectors of α, β, γ Base station device for. The serial adder 280 of claim 2, wherein the digital combiner unit 270 adds multi-sector forward data output from the forward switch unit 240 and forward data output from a previous SE. And a parity error detector 290 for detecting whether there is a parity error in the forward data output from the previous SE, and a parity interrupt for reporting the error to the controller 210 when an error is detected by the parity error detector 290. It operates as a generator 300, a parity generator 310 for adding a parity bit to the 16th bit of forward data output from the serial adder 280, and each component block in the digital combiner 270. Multisector base station apparatus using a switch, characterized in that consisting of a timing generator for providing a timing for. The apparatus of claim 6, wherein the serial adder 280 outputs an even signal among forward data of the multi-sector I channel or the Q channel output from the forward switch unit 240 and the parity error detector 290. A first AND gate 281 that ANDs the enable signal according to the block signal, a second AND gate 282 that ORs the odd signal and the enable signal among the forward data, and an output signal from the previous stage SE. A third AND gate 283 for ANDing the even signal and the enable signal of the forward data, a first inverter 286 for inverting the timing control signal 1 output from the timing generator 320, and the timing In the second inverter 287 for inverting the timing control signal 2 output from the generator 320, the odd signal, the enable signal, and the first inverter 286 of the forward data output from the previous stage SE. half A fourth AND gate 284 for ANDing the transmitted timing control signal 1, a fifth AND gate 285 for ANDing the carry signal fed back with the timing control signal 2 inverted by the second inverter 287, and the fourth The sum total of the total adder 288 and the total adder 288, which divides the output signals of the first through fourth AND gates 281 through 284 into even and odd, respectively, is latched and output to the BICA according to the system clock. Multi-sector base station apparatus using a switch, characterized in that consisting of D flip-flop (289). 8. The signal of claim 6, wherein the parity error detection unit 290 is configured to enable an exclusive or gate for operating the exclusive OR gate to which the output signal of the first D flip-flop is fed back and the even signal of the forward data output from the previous stage SE. An exclusive OR gate 291 for exclusive OR of the odd signal, an inverter 292 for inverting the enable signal, and an enable signal and a parity error detector 290 inverted by the inverter 292. The OR gate 293 for ORing the enable signal for operation and the output signal of the exclusive OR gate 291 are latched and used as the enable signal of the exclusive OR gate 291 according to a system clock. It is enabled by the first D flip-flop 294 for feedback output and the timing control signal 1 output from the timing generator 320 to output the output signal of the OR gate 293. The second D flip-flop 295 that latches and outputs a parity error detection signal according to the system clock, and the block signal according to the system clock when the parity error detection signal is received from the second D flip-flop 295. A multisector base station apparatus using a switch comprising a block signal generator (296) generated as an enable signal of a serial adder (280). 7. The inverter of claim 6, wherein the parity interrupt generator 300 inverts the parity error detection signal output from the parity error detector 290, and the parity error inverted by the inverter 301. The first AND gate 302 for ANDing the detection signal and the timing control signal 0 output from the timing generator 320, the clear signal for initializing the parity interrupt generator 300, and the timing generator 320. A 7-bit counter 303 for counting a system clock by operating in accordance with the timing control signal 1 output from the signal, an output signal of the 7-bit counter 303, and an enable signal for operating the parity error detector 290. The second AND gate 304 is multiplied by AND, the output signal of the first AND gate 302 and the inverted output signal of the second AND gate 304 are operated to latch the parity error detection signal. And an output signal according to the system clock, and the output signal of the D flip-flop 305 and the enable signal for operating the parity interrupt generator 300 to logically control the interrupt signal. Multi-sector base station apparatus using a switch, characterized in that consisting of an OR gate (306) to output. The modulo-8 down counter 321 of claim 6, wherein the timing generator 320 counts the system clock in synchronization with the even clock and outputs a control signal for every system clock based on eight system clocks. And a comparator 322 which provides timing control signals 1 to 7 to the respective component blocks in the digital combiner 270 according to the control signal output from the modulo-8 down counter 321. Multisector base station apparatus using a switch. The method of claim 1, wherein the total delay value for the switching path is compensated for to compensate for the delay present in the forward channel of the base station apparatus. T _{pp2s ― dly} + T _{mod ― dly} + T _{dist ― dly} ), Save the value to be set in the register for delay compensation to the database, and read the corresponding timing adjustment value from the database according to the switch connection that will be changed at the initial setting or whenever the switch connection is changed. A base station apparatus for multi-sector using a switch, characterized in that to solve the timing delay due to the addition of the SE by downloading to the adjustment register.