KR100301045B1 - Method for forming multilevel interconnect in a semiconduct or device - Google Patents
Method for forming multilevel interconnect in a semiconduct or device Download PDFInfo
- Publication number
- KR100301045B1 KR100301045B1 KR1019980035720A KR19980035720A KR100301045B1 KR 100301045 B1 KR100301045 B1 KR 100301045B1 KR 1019980035720 A KR1019980035720 A KR 1019980035720A KR 19980035720 A KR19980035720 A KR 19980035720A KR 100301045 B1 KR100301045 B1 KR 100301045B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- conductive layer
- lower conductive
- layer
- contact plug
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 콘택플러그와 콘택플러그의 상부 또는/ 및 하부에 형성되는 도전층 사이의 접촉저항을 최소화시키는 반도체 소자의 다층배선 형성방법을 개시한다. 본 발명은 반도체 기판상에 제1 하부도전층을 형성하는 단계와, 제1 하부도전층상에 제2 하부도전층을 형성하는 단계와, 제2 하부도전층상에 층간절연막을 증착하는 단계와, 층간절연막에 콘택홀을 형성하는 단계와, 콘택홀에 제2 하부도전층을 이루는 도전물질과 동일한 물질을 매립하여 콘택플러그를 형성하는 단계를 구비한다. 본 발명에 의해, 콘택플러그와 상부 또는/및 하부도전층의 접촉면적을 증대시킴으로써, 콘택플러그와 상부 또는/및 하부도전층의 계면에 형성되는 접촉저항을 최소화할 수 있으며, 또한 콘택플러그를 형성한 후에 진행되는 후속공정에 의해 발생하는 콘택플러그의 분리현상 및 이탈현상을 방지할 수 있다.The present invention discloses a method for forming a multilayer wiring of a semiconductor device which minimizes contact resistance between a contact plug and a conductive layer formed on or / or under the contact plug. The present invention provides a method of forming a first lower conductive layer on a semiconductor substrate, forming a second lower conductive layer on the first lower conductive layer, depositing an interlayer insulating film on the second lower conductive layer, and Forming a contact hole in the insulating layer and forming a contact plug by filling the same material as the conductive material forming the second lower conductive layer in the contact hole. According to the present invention, by increasing the contact area of the contact plug and the upper or / and lower conductive layer, it is possible to minimize the contact resistance formed at the interface of the contact plug and the upper or / and lower conductive layer, and also to form a contact plug After that, it is possible to prevent separation and separation of the contact plug caused by the subsequent process.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 상세하게는 접촉저항을 최소화시키는 다층배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a multilayer wiring to minimize contact resistance.
반도체 소자가 고집적화됨에 따라 복잡도와 집적밀도가 증가하게 되고, 그 결과 불가피하게 다층배선화가 필요하게 되었다. 반도체 소자에 있어서 다층배선화를 실현하기 위하여, 하부배선층 및 상부배선층을 연결하는 비아콘택홀(via contact hole)을 형성한 후 비아콘택홀을 도전물질로 채우는 기술이 사용되고 있다.As semiconductor devices are highly integrated, complexity and integration densities increase, and as a result, multilayer wiring is inevitably required. In order to realize multilayer wiring in a semiconductor device, a technique of forming a via contact hole connecting a lower wiring layer and an upper wiring layer and then filling the via contact hole with a conductive material is used.
도 1은 종래의 다층배선 형성방법에 따라 형성된 반도체 소자를 도시한 단면도이다. 도 1을 참조하면, 반도체 기판(100) 상에 하부도전층(110) 및 캡핑층(130)을 순차적으로 증착한다. 다음, 하부도전층(110) 및 캡핑층(130)을 패터닝하여 하부배선을 형성한다. 다음, 하부배선이 형성된 결과물상에 층간절연막(140)을 증착한다. 다음, 콘택홀을 형성하고자 하는 영역의 층간절연막(140) 및 캡핑층(130)을 식각하여 콘택홀을 형성한다. 다음, 콘택홀이 형성된 반도체 기판(100)의 전면에 도전물질을 증착한 후, 층간절연막(140)의 상부면을 식각저지층으로 하여 증착된 도전물질을 식각하여 콘택플러그(150)를 완성하고, 층간절연막(140)의 표면을 평탄화한다. 다음, 결과물 상에 상부도전층(180)을 증착한 후 패터닝하여 상부배선을 형성한다.1 is a cross-sectional view illustrating a semiconductor device formed by a conventional method for forming a multilayer wiring. Referring to FIG. 1, the lower conductive layer 110 and the capping layer 130 are sequentially deposited on the semiconductor substrate 100. Next, the lower conductive layer 110 and the capping layer 130 are patterned to form a lower wiring. Next, an interlayer insulating layer 140 is deposited on the resultant formed lower wiring. Next, the interlayer insulating layer 140 and the capping layer 130 in the region where the contact hole is to be formed are etched to form a contact hole. Next, after the conductive material is deposited on the entire surface of the semiconductor substrate 100 on which the contact hole is formed, the contact plug 150 is completed by etching the deposited conductive material by using the upper surface of the interlayer insulating layer 140 as an etch stop layer. The surface of the interlayer insulating film 140 is planarized. Next, the upper conductive layer 180 is deposited on the resultant and then patterned to form an upper wiring.
그런데, 최근 반도체 소자의 제조공정의 디자인 룰(design rule)이 작아짐에 따라 콘택플러그와 상,하부 도전층의 접촉면적이 점점 작아지게 되어 접촉저항이증가하는 문제점이 있다. 또한, 콘택플러그와 상하부 도전층에 사용되는 도전물질들이 일반적으로 서로 다르기 때문에 이들 계면의 접촉저항이 증가할 뿐만이 아니라, 콘택플러그를 형성한 후 층간절연막 및 콘택플러그의 표면을 평탄화하기 위한 화학기계적 연마공정이나 에치백공정을 진행하는 경우, 콘택플러그가 콘택홀로부터 분리되는 현상이나 콘택플러그가 하부도전층과의 계면으로부터 들뜨는 현상이 발생하는 문제점이 있다.However, as the design rules of the manufacturing process of semiconductor devices become smaller, the contact area between the contact plug and the upper and lower conductive layers becomes smaller, resulting in an increase in contact resistance. In addition, since the conductive materials used for the contact plug and the upper and lower conductive layers are generally different from each other, the contact resistance of these interfaces not only increases, but also the chemical mechanical polishing to planarize the surfaces of the interlayer insulating film and the contact plug after forming the contact plug. When the process or the etch back process is performed, there is a problem in that the contact plug is separated from the contact hole or the contact plug is lifted from the interface with the lower conductive layer.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 콘택플러그와 상,하부 도전층 사이에 형성되는 계면의 접촉저항을 최소화하고 콘택플러그 형성후에 진행되는 후속공정에 의해 콘택플러그가 콘택홀로부터 분리되는 현상 및 들뜨는 현상을 방지할 수 있는 반도체 소자의 다층배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and minimizes the contact resistance of the interface formed between the contact plug and the upper and lower conductive layers, and the contact plug is removed from the contact hole by a subsequent process performed after the contact plug is formed. It is an object of the present invention to provide a method for forming a multilayer wiring of a semiconductor device capable of preventing the phenomenon of separation and the phenomenon of lifting.
도 1은 종래의 다층배선 형성방법에 따라 제조된 반도체소자를 도시한 단면도이다.1 is a cross-sectional view illustrating a semiconductor device manufactured according to a conventional method for forming a multilayer wiring.
도 2a 내지 도 2c는 본 발명의 제1실시예에 따른 반도체 소자의 다층배선 형성방법을 순차적으로 도시한 단면도들이다.2A through 2C are cross-sectional views sequentially illustrating a method of forming a multilayer wiring of a semiconductor device according to a first embodiment of the present invention.
도 3은 본 발명의 제2실시예의 다층배선 형성방법에 따라 제조된 반도체 소자를 도시한 단면도이다.3 is a cross-sectional view illustrating a semiconductor device manufactured according to the method for forming a multilayer wiring according to the second embodiment of the present invention.
도 4는 본 발명의 제3실시예의 다층배선 형성방법에 따라 제조된 반도체 소자를 도시한 단면도이다.4 is a cross-sectional view illustrating a semiconductor device manufactured according to the method for forming a multilayer wiring according to a third embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
200:반도체 기판210:제1 하부도전층200: semiconductor substrate 210: first lower conductive layer
220:제2 하부도전층240:층간절연막220: second lower conductive layer 240: interlayer insulating film
250':콘택플러그320:제1 상부도전층250 ': contact plug 320: first upper conductive layer
340:제2 상부도전층340: the second upper conductive layer
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 다층배선 형성방법은 단위소자가 형성된 반도체 기판 상에 제1 하부도전층을 형성하는 단계와, 제1 하부도전층 상에 제2 하부도전층을 형성하는 단계와, 제2 하부도전층상에 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 제2 하부도전층의 일부를 노출시키는 콘택홀을 형성하는 단계와, 콘택홀을 제2 하부도전층을 이루는 도전물질과 동일한 물질로 매립하여 콘택플러그를 형성하는 단계를 구비한다. 이때, 콘택홀을 형성하는 단계이후, 콘택홀의 표면에 티타늄막 및 티타늄질화막의 적층구조로 된 장벽층을형성하는 단계를 더 구비하는 것이 바람직하다. 또한, 콘택플러그를 형성하는 단계는, 콘택홀이 형성된 반도체 기판상에 제2 하부도전층을 이루는 도전물질과 동일한 물질을 증착하는 단계와, 층간절연막의 상부면을 식각저지층으로 하여 반도체 기판의 표면을 평탄화하는 단계를 구비하는 것이 바람직하다.In order to achieve the above object, a method of forming a multilayer wiring of a semiconductor device of the present invention includes forming a first lower conductive layer on a semiconductor substrate on which a unit device is formed, and forming a second lower conductive layer on the first lower conductive layer. Forming an interlayer insulating film on the second lower conductive layer, etching the interlayer insulating film to form a contact hole exposing a portion of the second lower conductive layer, and forming a contact hole in the second lower conductive layer. And filling the contact plug with the same material as the conductive material. At this time, after the forming of the contact hole, it is preferable to further comprise the step of forming a barrier layer having a laminated structure of titanium film and titanium nitride film on the surface of the contact hole. The forming of the contact plug may include depositing the same material as the conductive material forming the second lower conductive layer on the semiconductor substrate on which the contact hole is formed, and using the upper surface of the interlayer insulating layer as an etch stop layer. It is preferred to have a step of planarizing the surface.
상기 목적을 달성하기 위하여 본 발명의 다른 반도체 소자의 다층배선 형성방법은 단위소자가 형성된 반도체 기판 상에 제1 하부도전층을 형성하는 단계와, 제1 하부도전층 상에 제2 하부도전층을 형성하는 단계와, 제2 하부도전층상에 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 제2 하부도전층의 일부를 노출시키는 콘택홀을 형성하는 단계와, 콘택홀에 제2 하부도전층을 이루는 도전물질과 동일한 물질을 매립하여 콘택플러그를 형성하는 단계와, 콘택플러그가 형성된 결과물 상에 콘택플러그를 이루는 도전물질과 동일한 물질을 증착하여 제1 상부도전층을 형성하는 단계와, 제1 상부도전층상에 제2 상부도전층을 형성하는 단계를 구비한다.In order to achieve the above object, a method of forming a multilayer wiring of another semiconductor device of the present invention includes forming a first lower conductive layer on a semiconductor substrate on which a unit device is formed, and forming a second lower conductive layer on the first lower conductive layer. Forming an interlayer insulating layer on the second lower conductive layer, etching the interlayer insulating layer to form a contact hole exposing a portion of the second lower conductive layer, and forming a second lower conductive layer in the contact hole. Filling the same material as the conductive material forming the contact plug, depositing the same material as the conductive material constituting the contact plug on the resultant on which the contact plug is formed, and forming a first upper conductive layer; And forming a second upper conductive layer on the upper conductive layer.
본 발명에 의해 콘택플러그와 상부 및/또는 하부도전층의 사이에 콘택플러그와 동일한 물질로 이루어진 도전층을 더 구비함으로써, 콘택플러그와 상부 및/또는 하부도전층의 계면에 형성되는 접촉저항을 최소화할 수 있으며, 또한 콘택플러그를 형성한 후에 진행되는 후속공정에 의해 발생하는 콘택플러그의 분리현상 및 이탈현상을 방지할 수 있다.The present invention further includes a conductive layer made of the same material as the contact plug between the contact plug and the upper and / or lower conductive layer, thereby minimizing contact resistance formed at the interface between the contact plug and the upper and / or lower conductive layer. In addition, it is possible to prevent the separation and separation of the contact plug caused by the subsequent process that proceeds after the contact plug is formed.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세히 설명한다. 그러나 본 발명이 하기 실시예에 한정되는 것은 아니며, 단지 본 실시예들은 본 발명의 개시가 완전해지도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위하여 제공되는 것으로서, 본 발명의 기술사상 및 범위내에서 당 분야의 통상의 지식을 가진 자에 의하여 각종 변형 및 개량이 가능함은 명백하다. 또한, 도면에서 층이나 영역들의 두께는 설명을 명확하게 하기 위하여 과장된 것이다. 도면에서 동일한 참조부호는 동일한 구성요소를 나타낸다. 또한 어떤 층이 다른 층 또는 기판의 "상부"에 있다고 기재된 경우, 상기 어떤 층이 상기 다른 층 또는 기판의 상부에 직접 접촉하면서 존재할 수도 있고, 그 사이에 다른 제3의 층이 개재될 수도 있다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following examples, only the examples are provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art. Various modifications and improvements are apparent to those skilled in the art within the spirit and scope of the invention. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. In addition, where a layer is described as being on the "top" of another layer or substrate, the layer may be present in direct contact with the top of the other layer or substrate, with another third layer interposed therebetween.
제1실시예First embodiment
도 2a를 참조하면, 단위소자가 형성된 반도체 기판(200) 상에 제1 하부도전층(210) 및 제2 하부도전층(220)을 순차적으로 형성한다. 이때, 제1 하부도전층(210)은 알루미늄, 알루미늄 합금 또는 구리등을 사용하는 것이 바람직하다. 또한, 제2 하부도전층(220)은 콘택플러그를 형성하는 도전물질과 동일한 물질을 사용하여야 한다. 이때, 제1 하부도전층(210)과 제2 하부도전층(220)의 사이에 캡핑층(미도시)을 더 구비하는 것이 바람직하다. 캡핑층은 제1 하부도전층(210)과 제2 하부도전층(220)의 계면에서 서로 반응하여 합금상태가 되는 것을 방지하기 위하여 형성하는 것으로서, 화학적으로 열적으로 안정할 뿐만 아니라 전기적 비저항이 매우 작은 티타늄질화막을 사용하여 형성하는 것이 바람직하다. 또한, 제2 하부도전층(220)과 후속공정에서 제2 하부도전층(220)상에 형성되는 층간절연막(240) 사이에 캡핑층을 형성할 수 있다. 다음, 제2 하부도전층(220) 상에층간절연막(240), 예컨대 실리콘산화막을 증착한다.Referring to FIG. 2A, the first lower conductive layer 210 and the second lower conductive layer 220 are sequentially formed on the semiconductor substrate 200 on which the unit devices are formed. At this time, it is preferable that the first lower conductive layer 210 is made of aluminum, an aluminum alloy, or copper. In addition, the second lower conductive layer 220 should use the same material as the conductive material forming the contact plug. In this case, a capping layer (not shown) may be further provided between the first lower conductive layer 210 and the second lower conductive layer 220. The capping layer is formed to prevent an alloy from reacting with each other at an interface between the first lower conductive layer 210 and the second lower conductive layer 220. The capping layer is not only chemically thermally stable but also has very high electrical resistivity. It is preferable to form using a small titanium nitride film. In addition, a capping layer may be formed between the second lower conductive layer 220 and the interlayer insulating layer 240 formed on the second lower conductive layer 220 in a subsequent process. Next, an interlayer insulating film 240, for example, a silicon oxide film, is deposited on the second lower conductive layer 220.
도 2b를 참조하면, 콘택홀을 형성하고자 하는 영역의 층간절연막(240)을 식각하여 콘택홀을 형성한다. 이때, 제2 하부도전층(220)의 상부면의 일부도 함께 식각될 수 있다. 다음, 콘택홀의 표면에 장벽층(미도시)을 형성하는 것이 바람직하다. 이러한 장벽층은 티타늄막 및 티타늄질화막을 순차적으로 얇게 증착함으로써 형성된다. 이때, 티타늄질화막은 층간절연막(240')의 측벽과 후속공정에서 형성되는 콘택플러그(250')가 그 계면에서 서로 반응을 일으키는 것을 방지하기 위한 것이며, 티타늄막은 티타늄질화막 및 층간절연막의 접촉이 잘 되도록 하기 위한 것이다. 다음, 장벽층상에 콘택플러그용 도전물질(250)을 증착하며, 콘택플러그용 도전물질은 텅스텐인 것이 바람직하다.Referring to FIG. 2B, a contact hole is formed by etching the interlayer insulating layer 240 in the region where the contact hole is to be formed. In this case, a portion of the upper surface of the second lower conductive layer 220 may also be etched together. Next, it is preferable to form a barrier layer (not shown) on the surface of the contact hole. This barrier layer is formed by sequentially depositing a titanium film and a titanium nitride film. At this time, the titanium nitride film is to prevent the contact plug 250 'formed at the sidewall of the interlayer insulating film 240' and the subsequent process from reacting with each other at the interface, and the titanium film has a good contact between the titanium nitride film and the interlayer insulating film. It is to make it possible. Next, the contact plug conductive material 250 is deposited on the barrier layer, and the contact plug conductive material is preferably tungsten.
도 2c를 참조하면, 층간절연막(240')의 상부면을 식각저지층으로 하여 층간절연막(240')의 표면 및 콘택플러그용 도전물질(250)의 표면을 평탄화하여 콘택플러그(250')를 완성한다. 이때, 식각 공정은 화학기계적연마방법을 이용하거나 에치백방법을 이용할 수 있다. 특히 화학기계적연마방법을 이용하면 콘택플러그(250')의 표면의 특성을 향상시킬 수 있다.Referring to FIG. 2C, the surface of the interlayer insulating layer 240 'and the surface of the contact plug conductive material 250 are planarized by using the upper surface of the interlayer insulating layer 240' as an etch stop layer to form the contact plug 250 '. Complete In this case, the etching process may use a chemical mechanical polishing method or an etch back method. In particular, by using a chemical mechanical polishing method, the surface of the contact plug 250 'may be improved.
본 발명은 하부도전층을 제1 하부도전층(210) 및 제2 하부도전층(220)으로 이루어지는 적층구조로 형성하고, 콘택플러그(250')와 제1 하부도전층(210)사이에 콘택플러그용 도전물질과 동일한 물질로 이루어지는 제2 하부도전층(220)을 형성한다. 그 결과, 콘택플러그(250')와 제2 하부도전층(220)의 계면이 동종의 물질들로 형성되어 계면의 접촉특성을 향상시킴으로써 후속공정에 의해 발생하는콘택플러그(250')의 이탈현상 및 들뜸 현상을 방지할 수 있다. 또한, 제1 하부도전층(210)과 제2 하부도전층(220)의 계면은 이종의 물질들로 형성되더라도 접촉면적이 넓기 때문에 접촉저항을 최소화시킬 수 있다. 이는, 종래의 콘택플러그와 하부도전층의 사이에 형성되는 계면이 이종의 물질들로 이루어짐에 따라 계면의 접촉특성이 열화되고 콘택플러그의 크기가 작아짐에 따라 접촉면적이 감소하고 접촉저항이 증가되는 것과 비교된다.According to the present invention, the lower conductive layer is formed in a laminated structure including the first lower conductive layer 210 and the second lower conductive layer 220, and a contact is formed between the contact plug 250 ′ and the first lower conductive layer 210. A second lower conductive layer 220 made of the same material as the plug conductive material is formed. As a result, an interface between the contact plug 250 'and the second lower conductive layer 220 is formed of the same kind of material, thereby improving contact characteristics of the interface, so that the contact plug 250' is displaced by a subsequent process. And lifting phenomenon can be prevented. In addition, even if the interface between the first lower conductive layer 210 and the second lower conductive layer 220 is formed of different materials, the contact area is wide, thereby minimizing contact resistance. This is because, as the interface formed between the conventional contact plug and the lower conductive layer is made of different materials, the contact characteristics of the interface deteriorate and the contact area decreases and the contact resistance increases as the size of the contact plug decreases. Is compared to
제2실시예Second embodiment
이하, 도 3을 참조하여 제2실시예를 상세히 설명한다. 다만, 제1실시예와 동일한 점은 설명을 생략한다.Hereinafter, the second embodiment will be described in detail with reference to FIG. 3. However, description of the same point as the first embodiment will be omitted.
도 3을 참조하면, 하부도전부재가 형성된 반도체 기판(200) 상에 층간절연막(240)을 증착한다. 다음, 반도체 기판(200) 상의 활성영역과 후속공정에서 형성되는 제1 상부도전층(320)을 전기적으로 연결하기 위하여, 층간절연막(240)을 식각하여 콘택홀을 형성한다. 다음, 콘택홀의 표면에 티타늄막 및 티타늄질화막을 순차적으로 얇게 증착하여 장벽층(미도시)을 형성한다. 장벽층상에 콘택플러그용 도전물질을 증착한 후, 층간절연막(240)의 표면을 식각저지층으로 하여 층간절연막(240)의 표면 및 콘택플러그용 도전물질의 표면을 평탄화하여 콘택플러그(250')를 완성한다. 평탄화된 층간절연막(240) 및 콘택플러그(250') 상에 콘택플러그용 도전물질과 동일한 물질을 증착하여 제1 상부도전층(320)을 형성한 후, 제2 상부도전층(340)을 형성한다.Referring to FIG. 3, an interlayer insulating layer 240 is deposited on a semiconductor substrate 200 on which a lower conductive member is formed. Next, in order to electrically connect the active region on the semiconductor substrate 200 with the first upper conductive layer 320 formed in a subsequent process, the interlayer insulating layer 240 is etched to form a contact hole. Next, a barrier layer (not shown) is formed by sequentially depositing a titanium film and a titanium nitride film on the surface of the contact hole. After depositing the contact plug conductive material on the barrier layer, the surface of the interlayer insulating film 240 and the surface of the contact plug conductive material are planarized by using the surface of the interlayer insulating film 240 as an etch stop layer to form the contact plug 250 '. To complete. After forming the first upper conductive layer 320 by depositing the same material as the contact plug conductive material on the planarized interlayer insulating film 240 and the contact plug 250 ', the second upper conductive layer 340 is formed. do.
본 발명의 제2실시예는 콘택플러그(250') 및 제2 상부도전층(340) 사이에 콘택플러그용 도전물질과 동일한 물질로 이루어지는 제1 상부도전층(320)을 형성함으로써, 제2 상부도전층(340) 및 콘택플러그(250') 사이에 형성되는 접촉저항을 최소화할 수 있다.The second embodiment of the present invention forms a first upper conductive layer 320 made of the same material as the conductive material for the contact plug between the contact plug 250 'and the second upper conductive layer 340, thereby forming a second upper portion. The contact resistance formed between the conductive layer 340 and the contact plug 250 ′ may be minimized.
제3실시예Third embodiment
이하, 도 4를 참조하여 제3실시예를 설명한다. 다만, 제1실시예와 동일한 점은 설명을 생략한다.Hereinafter, a third embodiment will be described with reference to FIG. 4. However, description of the same point as the first embodiment will be omitted.
도 4를 참조하면, 단위소자가 형성된 반도체 기판(400) 상에 제1 하부도전층(410) 및 제2 하부도전층(420)을 형성한다. 다음, 제2 하부도전층(420)상에 층간절연막(440)을 형성한 후, 층간절연막(450)을 식각하여 제2 하부도전층(420)의 일부를 노출시키는 콘택홀을 형성한다. 콘택홀이 형성된 반도체 기판(400)의 전면에 제2 하부도전층(420)을 형성하는 물질과 동일한 콘택플러그용 도전물질을 증착한 후, 그 표면을 평탄화하여 콘택플러그(450)를 형성한다. 콘택플러그(450)가 형성된 반도체 기판(400)의 전면에 콘택플러그용 도전물질과 동일한 물질을 증착하여 제1 상부도전층(460)을 형성한 후, 제1 상부도전층(460) 상에 제2 상부도전층(480)을 형성한다.Referring to FIG. 4, the first lower conductive layer 410 and the second lower conductive layer 420 are formed on the semiconductor substrate 400 on which the unit devices are formed. Next, after the interlayer insulating film 440 is formed on the second lower conductive layer 420, the interlayer insulating film 450 is etched to form a contact hole exposing a part of the second lower conductive layer 420. After depositing the same contact plug conductive material as the material for forming the second lower conductive layer 420 on the entire surface of the semiconductor substrate 400 where the contact hole is formed, the surface of the contact plug 450 is formed by planarizing the contact plug 450. After forming the first upper conductive layer 460 by depositing the same material as the conductive material for the contact plug on the entire surface of the semiconductor substrate 400 on which the contact plug 450 is formed, the first upper conductive layer 460 is formed on the first upper conductive layer 460. 2 forms the upper conductive layer 480.
본 발명의 제3실시예는 콘택플러그(450)의 상,하부면에 콘택플러그용 도전물질과 동일한 물질로 이루어지는 제1 상부도전층(460) 및 제2 하부도전층(420)을 형성함으로써, 콘택플러그(450)와 상,하부도전층의 계면들의 접촉저항을 최소화시킬수 있으며, 후속공정에 의해 발생되는 콘택플러그의 분리현상 및 들뜸현상을 방지할 수 있다.In the third embodiment of the present invention, the first upper conductive layer 460 and the second lower conductive layer 420 made of the same material as the conductive material for the contact plug are formed on the upper and lower surfaces of the contact plug 450. The contact resistance of the contact plug 450 and the interfaces of the upper and lower conductive layers may be minimized, and the separation and lifting of the contact plug generated by the subsequent process may be prevented.
이상에서 살펴본 바와 같이 본 발명에 따른 반도체 소자의 다층배선 형성방법은, 콘택플러그와 상부 및/또는 하부도전층 사이에 콘택플러그용 도전물질과 동일한 물질로 이루어지는 도전층을 형성하는 단계를 더 구비함으로써, 콘택플러그와 상부 및/또는 하부도전층의 접촉면적을 증대시켜 계면의 접촉저항을 최소화할 수 있으며, 또한 후속공정에 의해 발생하는 콘택플러그의 분리현상 및 이탈현상을 방지할 수 있다.As described above, the method for forming a multilayer wiring of the semiconductor device according to the present invention further includes forming a conductive layer made of the same material as the contact plug conductive material between the contact plug and the upper and / or lower conductive layer. In addition, by increasing the contact area between the contact plug and the upper and / or lower conductive layer, the contact resistance of the interface can be minimized, and the separation and detachment of the contact plug caused by a subsequent process can be prevented.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980035720A KR100301045B1 (en) | 1998-08-31 | 1998-08-31 | Method for forming multilevel interconnect in a semiconduct or device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980035720A KR100301045B1 (en) | 1998-08-31 | 1998-08-31 | Method for forming multilevel interconnect in a semiconduct or device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000015683A KR20000015683A (en) | 2000-03-15 |
| KR100301045B1 true KR100301045B1 (en) | 2002-06-20 |
Family
ID=19549060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980035720A KR100301045B1 (en) | 1998-08-31 | 1998-08-31 | Method for forming multilevel interconnect in a semiconduct or device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100301045B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06236928A (en) * | 1992-12-14 | 1994-08-23 | Kawasaki Steel Corp | Semiconductor device and its manufacture |
-
1998
- 1998-08-31 KR KR1019980035720A patent/KR100301045B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06236928A (en) * | 1992-12-14 | 1994-08-23 | Kawasaki Steel Corp | Semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000015683A (en) | 2000-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7777337B2 (en) | Semiconductor device having damascene interconnection structure that prevents void formation between interconnections | |
| US6100177A (en) | Grooved wiring structure in semiconductor device and method for forming the same | |
| US6424036B1 (en) | Semiconductor device and method for manufacturing the same | |
| US6268283B1 (en) | Method for forming dual damascene structure | |
| US6251790B1 (en) | Method for fabricating contacts in a semiconductor device | |
| US20020153554A1 (en) | Semiconductor device having a capacitor and manufacturing method thereof | |
| US6335570B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2785768B2 (en) | Method for manufacturing semiconductor device | |
| EP1182708A2 (en) | High capacitance damascene capacitor | |
| US5327011A (en) | Semiconductor device with enhanced via or contact hole connection between an interconnect layer and a connecting region | |
| JPH0214552A (en) | Method of forming at least one additional level metal interconnection so as to be brought into contact with metal of lower level in semiconductor device | |
| US6211569B1 (en) | Interconnection lines for improving thermal conductivity in integrated circuits and method for fabricating the same | |
| US6974770B2 (en) | Self-aligned mask to reduce cell layout area | |
| CN211350636U (en) | Semiconductor device with a plurality of transistors | |
| KR100295054B1 (en) | Semiconductor device having multi-wiring and manufacturing method thereof | |
| US6281134B1 (en) | Method for combining logic circuit and capacitor | |
| KR100301045B1 (en) | Method for forming multilevel interconnect in a semiconduct or device | |
| US20220199531A1 (en) | Memory device and fabrication method thereof | |
| KR100590205B1 (en) | Interconnection Structure For Semiconductor Device And Method Of Forming The Same | |
| US6352919B1 (en) | Method of fabricating a borderless via | |
| US6087252A (en) | Dual damascene | |
| JP2001118923A (en) | Semiconductor device and manufacturing method therefor | |
| CN111211095A (en) | Method for manufacturing conductive interconnection line | |
| US6297144B1 (en) | Damascene local interconnect process | |
| KR100278274B1 (en) | A method for forming stack contact in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080602 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |