KR100300844B1 - Imdct circuit of ac-3 decoder - Google Patents

Imdct circuit of ac-3 decoder Download PDF

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KR100300844B1
KR100300844B1 KR1019970075184A KR19970075184A KR100300844B1 KR 100300844 B1 KR100300844 B1 KR 100300844B1 KR 1019970075184 A KR1019970075184 A KR 1019970075184A KR 19970075184 A KR19970075184 A KR 19970075184A KR 100300844 B1 KR100300844 B1 KR 100300844B1
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ifft
imdct
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decoder
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KR19990055256A (en
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김명식
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박종섭
주식회사 하이닉스반도체
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    • G—PHYSICS
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    • G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
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    • G10L19/0212—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using spectral analysis, e.g. transform vocoders or subband vocoders using orthogonal transformation
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Abstract

PURPOSE: An IMDCT circuit of an AC-3 decoder is provided to reduce a size of a chip and support two transform lengths according to "BSWITCH mode" by designing IMDCT algorithm as an exclusive circuit. CONSTITUTION: An IMDCT circuit of an AC-3 decoder includes a PRE_IFFT, a CIFFT, a POST_IFFT and an arithmetic unit. The PRE_IFFT is operated by start signal and calculates IFFT. The CIFFT is operated by "cifft_s" signal generated in the PRE_IFFT and performs complex IFFT. The POST_IFFT performs finally IFFT calculation according to "post_s" signal generated in the CIFFT, stores result data in a memory for downmix, and generates "imdct_end" signal indicating finish of IMCT. The arithmetic unit is selectively connected with the PRE_IFFT, the CIFFT and the POST_IFFT and performs arithmetic calculation of each transformer.

Description

에이씨-3 디코더의 아이엠디씨티 회로{Imdct circuit of ac-3 decoder}Imdct circuit of ac-3 decoder

본 발명은 AC-3 디코더의 IMDCT 기능 수행에 관한 것으로, 특히, 범용 DSP나 CPU에 의해 구현되던 IMDCT 알고리즘을 전용회로로 설계함으로써, 불필요한 하드웨어를 감소시켜 칩 크기를 감소시키고, "BSWITCH mode"에 따라 두가지의 변환길이(TRANSFORM LENGTH)를 지원하기 위한 것이다.The present invention relates to performing an IMDCT function of an AC-3 decoder. In particular, by designing an IMDCT algorithm implemented by a general-purpose DSP or a CPU as a dedicated circuit, it is possible to reduce unnecessary hardware and to reduce chip size, and to enter the "BSWITCH mode". Therefore, it is to support two transformation lengths (TRANSFORM LENGTH).

주지하다시피, AC-3 디코더는, 고화질 텔레비젼(HIGH DEFINITION TELEVISION : 이하 HDTV라 한다.)에서 오디오 압축 표준인 AC-3 규격에 의해 코딩(CODING) 된 신호를 디코딩(DECODING) 하는 장치이다.As is well known, the AC-3 decoder is a device that decodes a signal coded by an AC-3 standard, which is an audio compression standard, in a high definition television (hereinafter referred to as HDTV).

또한, AC-3 디코더의 IMDCT 블록은, 도1에서 도시되는 바와 같이, 언팩 맨티사 블록(UNPACK MANTISSA BLOCK)에서 계산된 채널의 맨티사(Mantissa)(tcbuf[256]) 값을 입력받아 미리 계산되어 있는 룩 업 테이블(LOOK-UP TABLE)의 COS과 SIN 값들과 3번의 IFFT 계산을 수행한 후, 다운믹스(DOWNMIX)를 위한 버퍼(MANTBUF[256])에 데이터를 저장하는 역할을 수행한다.In addition, as shown in FIG. 1, the IMDCT block of the AC-3 decoder is pre-calculated by receiving a Mantisissa (tcbuf [256]) value of a channel calculated in an UNPACK MANTISSA BLOCK. It performs COS and SIN values of LOOK-UP TABLE and three IFFT calculations, and then stores data in a buffer (MANTBUF [256]) for downmix.

그러나, 상기와 같은 종래의 IMDCT 기능은, 고속의 산술 연산을 위해 DSP나 범용 CPU에 의해 수행됨으로 인해, AC-3 디코더의 ASIC 설계시 DSP Core나 범용 CPU Core 내장으로 전체 칩 크기가 증가하게 된다는 문제점이 있었다.However, since the conventional IMDCT function is performed by the DSP or the general purpose CPU for high speed arithmetic operation, the overall chip size is increased by the DSP core or the general purpose CPU core in the ASIC design of the AC-3 decoder. There was a problem.

또한, IMDCT 알고리즘 구현을 DSP나 범용 CPU로 처리 할 경우는 불필요한 여분의 하드웨어가 상당부분 포함되어 그 효율성을 저하시키게 된다는 문제점 등이 있었다.In addition, when the IMDCT algorithm is implemented by a DSP or a general-purpose CPU, there is a problem that a large amount of unnecessary extra hardware is included, thereby reducing its efficiency.

본 발명의 목적은 상기와 같은 종래의 문제점을 해소하기 위한 것으로, 특히, 범용 DSP나 CPU에 의해 구현되던 IMDCT 알고리즘을 전용회로로 설계함으로써, 불필요한 하드웨어를 감소시켜 칩 크기를 감소시키고, "BSWITCH mode"에 따라 두가지의 변환길이를 지원할 수 있는 "AC-3 디코더의 IMDCT 회로"를 제공하는 데 있다.An object of the present invention is to solve the above-mentioned conventional problems, and in particular, by designing the IMDCT algorithm implemented by a general-purpose DSP or a CPU as a dedicated circuit, the chip size is reduced by reducing unnecessary hardware, and the "BSWITCH mode "The IMDCT circuit of the AC-3 decoder" can support two conversion lengths.

상기와 같은 목적을 달성하기 위하여 본 발명 "AC-3 디코더의 IMDCT 회로"는, "start" 신호에 의해 동작되어 IFFT 계산을 수행하는 PRE_IFFT와; 상기 PRE_IFFT에서 생성된 "cifft_s" 신호에 의해 동작되어 COMPLEX IFFT를 수행하는 CIFFT와; 상기 CIFFT에서 생성된 "post_s" 신호에 따라 마지막으로 IFFT 계산을 수행하여 최종 결과 데이터를 다운믹스를 위해 메모리에 저장한 후, IMDCT 수행 완료를 나타내는 "imdct_end" 신호를 발생하는 POST_IFFT와; MUX3_1과; ADD/SUB와; BITREV와; MEM_DEC와; 곱셈-덧셈, 곱셈-뺄셈을 수행하며, 상기 MUX3_1을 통해 3개의 IFFT에서 동통적으로 사용디는 산술연산부(Arithmetic Unit)를 포함하여 구성됨을 그 기술적 구성상의 특징으로 한다.In order to achieve the above object, the present invention "IMDCT circuit of the AC-3 decoder" includes a PRE_IFFT operated by a "start" signal to perform IFFT calculation; A CIFFT operated by the "cifft_s" signal generated in the PRE_IFFT to perform a COMPLEX IFFT; A POST_IFFT which performs an IFFT calculation according to the "post_s" signal generated by the CIFFT, stores final result data in a memory for downmixing, and generates an "imdct_end" signal indicating completion of IMDCT; MUX3_1; ADD / SUB; BITREV; MEM_DEC; Multiplication-addition, multiplication-subtraction are performed, and the technical configuration is characterized by including an Arithmetic Unit (Arithmetic Unit) used in three IFFT through the MUX3_1.

또한, 상기 PRE_IFFT, 또는 CIFFT, 또는 POST_IFFT는, "bswitch" 신호에 의해 변환길이를 256 샘플 길이, 또는 512 샘플 길이로 변환됨을 특징으로 한다.In addition, the PRE_IFFT, CIFFT, or POST_IFFT is characterized in that the conversion length is converted into 256 sample length or 512 sample length by the "bswitch" signal.

이러한 본 발명 "AC-3 디코더의 IMDCT 회로"는, 범용 DSP나 CPU에 의해 구현되던 IMDCT 알고리즘을 전용회로로 설계함으로써, 불필요한 하드웨어를 감소시켜 칩 크기를 감소시키고, "BSWITCH mode"에 따라 두가지의 변환길이를 지원할 수 있게 되는 것이다.In the present invention, the "IMDCT circuit of the AC-3 decoder" designes an IMDCT algorithm implemented by a general-purpose DSP or a CPU as a dedicated circuit, thereby reducing chip size by reducing unnecessary hardware, and according to the "BSWITCH mode". The conversion length can be supported.

도 1 은 IMDCT 블록의 인터페이스 상태를 나타낸 도면,1 is a view showing an interface state of an IMDCT block;

도 2 는 본 발명 "AC-3 디코더의 IMDCT 회로"의 입/출력 핀의 구성을 나타낸 도면,2 is a view showing the configuration of the input / output pins of the present invention "IMDCT circuit of the AC-3 decoder",

도 3 은 본 발명 "AC-3 디코더의 IMDCT 회로"의 기능적 블록을 나타낸 블록도,3 is a block diagram showing a functional block of the " IMDCT circuit of the AC-3 decoder " of the present invention;

도 4 는 본 발명 "AC-3 디코더의 IMDCT 회로"의 IMDCT 기능 수행시 사용되는 메모리의 내용을 나타낸 도면,4 is a view showing the contents of a memory used when performing the IMDCT function of the " IMDCT circuit of the AC-3 decoder "

도 5 는 본 발명 "AC-3 디코더의 IMDCT 회로" 중, PRE-IFFT 블록을 256 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 도면,FIG. 5 is a diagram showing software when the PRE-IFFT block is operated at a conversion length having 256 sample values in the " IMDCT circuit of the AC-3 decoder "

도 6 은 도5의 동작을 도식화한 도면,6 is a diagram illustrating the operation of FIG. 5;

도 7 은 본 발명 "AC-3 디코더의 IMDCT 회로" 중, PRE-IFFT 블록을 512 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 도면,FIG. 7 is a view showing software when the PRE-IFFT block is operated at a conversion length having a value of 512 samples in the " IMDCT circuit of the AC-3 decoder "

도 8 은 도7의 동작을 도식화한 도면,8 is a diagram illustrating the operation of FIG. 7;

도 9 는 본 발명 "AC-3 디코더의 IMDCT 회로" 중, Comlex IFFT 블록을 256샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 도면,FIG. 9 is a view showing software when the Comlex IFFT block is operated with a conversion length having 256 sample values in the "IMDCT circuit of the AC-3 decoder" of the present invention; FIG.

도 10 은 본 발명 "AC-3 디코더의 IMDCT 회로" 중, Comlex IFFT 블록을 512 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 도면,FIG. 10 is a view showing software when the Comlex IFFT block is operated at a conversion length having a value of 512 samples in the “IMDCT circuit of an AC-3 decoder” of the present invention; FIG.

도 11 은 도10의 동작을 도식화한 도면,11 is a diagram illustrating the operation of FIG. 10;

도 12 는 본 발명 "AC-3 디코더의 IMDCT 회로" 중, Post IFFT 블록을 256 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 도면,12 is a view showing the software when the Post IFFT block is operated with a conversion length having 256 sample values in the " IMDCT circuit of the AC-3 decoder "

도 13 은 본 발명 "AC-3 디코더의 IMDCT 회로" 중, Post IFFT 블록을 512 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 도면,FIG. 13 is a view showing software when the Post IFFT block is operated with a conversion length having a value of 512 samples in the "IMDCT circuit of the AC-3 decoder" of the present invention;

도 14 은 도13의 동작을 도식화한 도면,14 is a diagram illustrating the operation of FIG. 13;

도 15 는 본 발명 "AC-3 디코더의 IMDCT 회로"의 상세 구성을 나타낸 회로도,Fig. 15 is a circuit diagram showing the detailed construction of the " IMDCT circuit of AC-3 decoder " of the present invention;

도 16 은 도15 각 신호의 파형을 나타낸 타이밍도.FIG. 16 is a timing chart showing waveforms of each signal of FIG. 15; FIG.

이하, 상기와 같이 구성된 본 발명 "AC-3 디코더의 IMDCT 회로"의 기술적 사상에 따른 일 실시예를 들어 구성, 동작 및 작용 효과를 첨부된 도면에 의거 상세히 설명하면 다음과 같다.Hereinafter, with reference to the accompanying drawings, the configuration, operation and effect of the embodiment according to the technical idea of the present invention "IMDCT circuit of the AC-3 decoder" configured as described above in detail as follows.

<실시예><Example>

본 실시예에서는, 도2에서 도시되는 바와 같이, IMDCT_END, WR_SEMA, RD_SEMA, BSWITCH, START, CLK, RST, SRAM_IN[21:0], OEN, WEN ADDR[10:0], ROM_EN, ROM_OUT[21:0] 등의 입출력핀들을 사용한다.In this embodiment, as shown in Fig. 2, IMDCT_END, WR_SEMA, RD_SEMA, BSWITCH, START, CLK, RST, SRAM_IN [21: 0], OEN, WEN ADDR [10: 0], ROM_EN, ROM_OUT [21: 0] I / O pins are used.

여기서, 다운믹스 인터페이스(DOWNMIX Interface) 신호 중 IMDCT_END 신호는 IMDCT의 연산 수행 완료를 나타내며, WR_SEMA와 RD_SEMA 신호는 IMDCT에서 계산된 결과를 MANTBUF에 저장한 후, 다운믹스에서 이 데이터를 리드(READ) 시 충돌을 피하기 위한 신호이다.Here, the IMDCT_END signal of the downmix interface signal indicates completion of IMDCT operation, and the WR_SEMA and RD_SEMA signals store the result calculated in the IMDCT in MANTBUF, and then read this data in the downmix. This is a signal to avoid collisions.

또한, Configuration Input 신호인 BSWITCH 신호는 변환길이 중 하나를 선택하는 모드(MODE) 신호이며, Control Signal 중 START 신호는 IMDCT의 시작신호이다.The BSWITCH signal, which is a configuration input signal, is a mode signal for selecting one of the conversion lengths, and the START signal of the control signal is a start signal of the IMDCT.

또한, SRAM Interface와, SRAM Interface 신호들은, 메모리에 대한 데이터 리드/라이트(READ/WRITE)를 위한 신호들이다.Also, the SRAM Interface and SRAM Interface signals are signals for data read / write to the memory.

도3은 IMDCT의 기능적 구성을 나타낸 블록도로, 3번의 IFFT 계산부인 Pre_IFFT와, CIFFT와, POST_IFFT는 순차적으로 수행되며, 각 블록은 AC-3에서 인간의 청각 특성을 고려한 512 샘플, 또는 256 샘플의 두가지 변환길이를 지원한다.3 is a block diagram showing the functional configuration of the IMDCT, in which three IFFT calculation units, Pre_IFFT, CIFFT, and POST_IFFT, are performed in sequence, and each block includes 512 samples or 256 samples in consideration of the human auditory characteristics in AC-3. Two conversion lengths are supported.

한편, IMDCT 블록의 계산 과정은 입력을 받은 각 채널의 Mantissa 값과 룩 업 테이블을 참조하여 다음과 같은 스탭을 거쳐 완료된다.On the other hand, the calculation process of the IMDCT block is completed by the following steps with reference to the Mantissa value and the lookup table of each channel received.

1) Pre-IFFT Complex Multiply Step1) Pre-IFFT Complex Multiply Step

2) Complex IFFT Multiply Step2) Complex IFFT Multiply Step

3) Post-IFFT Complex Multiply Step3) Post-IFFT Complex Multiply Step

이때 사용되는 각 메모리의 양은 도4에서 도시되는 바와 같다.The amount of each memory used at this time is as shown in FIG.

도5는, 상기 Pre-IFFT 블록이 256 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 것이며, 도6은 이를 도식화한 것이다.Fig. 5 shows the software when the Pre-IFFT block is operated with a conversion length having 256 sample values, and Fig. 6 illustrates this.

또한, 도7는, 상기 Pre-IFFT 블록이 512 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 것이며, 도8은 이를 도식화한 것이다.Fig. 7 shows software when the Pre-IFFT block is operated with a conversion length having a value of 512 samples, and Fig. 8 illustrates this.

한편, 도9는 Complex IFFT 블록이 256 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 것이고, 도10은 512 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 것이며, 도11은 도10의 동작을 도식화 한 것이다.On the other hand, Fig. 9 shows the software when the Complex IFFT block is operated with a conversion length having 256 sample values, and Fig. 10 shows the software when it is operated with a conversion length having 512 sample values. It is a schematic of the operation.

또한, 도12는 Post IFFT 블록이 256 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 것이고, 도13은 512 샘플 값을 갖는 변환길이로 동작될때의 소프트웨어를 나타낸 것이며, 도14은 도13의 동작을 도식화 한 것이다.Fig. 12 shows software when the Post IFFT block is operated with a conversion length having 256 sample values, and Fig. 13 shows software when it is operated with a conversion length having 512 sample values. It is a schematic of the operation.

한편, 도15는 IMDCT의 세부 블록을 나타낸 도면으로, 이의 동작을 설명하면 다음과 같다.On the other hand, Figure 15 is a view showing a detailed block of the IMDCT, the operation thereof will be described as follows.

먼저, IMDCT의 입력신호인 bswitch 신호에 의해 변환길이가 결정되어지고, Start 신호에 의해 PRE-IFFT 블록이 IFFT 계산을 수행하게 된다.First, the conversion length is determined by the bswitch signal, which is an input signal of the IMDCT, and the PRE-IFFT block performs the IFFT calculation by the Start signal.

이때, IFFT 계산 데이터는 각 메모리(ROM, SRAM)에서 읽어오며, 계산이 완료되면 그 값을 다시 메모리에 저장하고 CIFFT 블록의 시작 신호인 cifft_s 신호를한 클럭동안 발생하게 된다.At this time, the IFFT calculation data is read from each memory (ROM, SRAM). When the calculation is completed, the value is stored in the memory again and the cifft_s signal, which is the start signal of the CIFFT block, is generated for one clock.

상기 CIFFT 블록은 cifft_s 신호에 따라 Complex IFFT 계산을 수행한 후, POST_IFFT 블록의 시작 신호인 post_s를 역시 한 클럭 동안 발생한다.The CIFFT block performs Complex IFFT calculation according to the cifft_s signal and then generates post_s, which is the start signal of the POST_IFFT block, for one clock.

POST_IFFT 블록은 post_s 신호에 따라 마지막으로 IFFT 계산을 수행하여 최종 결과 데이터를 다운믹스를 위해 메모리에 저장한 후, IMDCT 수행 완료를 나타내는 imdct_end 신호를 발생한다.The POST_IFFT block performs the final IFFT calculation according to the post_s signal, stores the final result data in memory for downmixing, and generates an imdct_end signal indicating completion of IMDCT.

즉, 각각 서로 다른 IFFT 계산을 수행하는 이들 세 블록은 순차적으로 처리된다.That is, these three blocks, each of which performs different IFFT calculations, are processed sequentially.

또한, IMDCT에서 가장 많은 연산부분을 차지하는 Arithmetic Unit 블록은 곱셈-덧셈, 곱셈-뺄셈을 수행하며, MUX3_1 블록을 통해 3개의 IFFT 블록에서 공통적으로 사용된다.In addition, the Arithmetic Unit block, which occupies the largest part of the IMDCT, performs multiplication-addition and multiplication-subtraction, and is commonly used in three IFFT blocks through the MUX3_1 block.

도16은 상기 제어신호들의 파형을 나타낸 타이밍도이다.16 is a timing diagram showing waveforms of the control signals.

이상에서 살펴본 바와 같이, 본 발명 "AC-3 디코더의 IMDCT 회로"는, 특히, 범용 DSP나 CPU에 의해 구현되던 IMDCT 알고리즘을 전용회로로 설계함으로써, 불필요한 하드웨어를 감소시켜 칩 크기를 감소시키고, "BSWITCH mode"에 따라 두가지의 변환길이를 지원할 수 있게 되는 효과가 있는 것이다.As described above, the present invention "IMDCT circuit of the AC-3 decoder", in particular, by designing the IMDCT algorithm implemented by a general-purpose DSP or CPU as a dedicated circuit, by reducing the unnecessary hardware to reduce the chip size, " According to the BSWITCH mode, it is possible to support two conversion lengths.

Claims (2)

AC-3 디코더의 IMDCT 회로에 있어서,In the IMDCT circuit of the AC-3 decoder, 상기 IMDCT 회로는, 시작(start) 신호에 의해 동작되어 역 고속 푸리에 변환(IFFT) 계산을 수행하는 전치 역 고속 푸리에 변환기(PRE_IFFT)와;The IMDCT circuit includes a pre-inverse fast Fourier transformer (PRE_IFFT) operated by a start signal to perform an inverse fast Fourier transform (IFFT) calculation; 상기 전치 역 고속 푸리에 변환기에서 생성된 "cifft_s"신호에 의해 동작되어 복소 IFFT를 수행하는 복소 역 고속 푸리에 변환기(CIFFT)와;A complex inverse fast Fourier transformer (CIFFT) operated by a "cifft_s" signal generated by the preinverse fast Fourier transformer to perform a complex IFFT; 상기 복소 역 고속 푸리에 변환기에서 생성된 "post_s" 신호에 따라 최종적으로 IFFT 계산을 수행하여 그 결과 데이터를 다운믹스를 위해 메모리에 저장하고, IMDCT 수행 완료를 나타내는 "imdct_end"신호를 발생하는 포스트 역 고속 푸리에 변환기(POST_IFFT)와;Finally, IFFT calculation is performed according to the " post_s " signal generated by the complex inverse fast Fourier transformer, and the resultant data is stored in memory for downmixing, and a post inverse fast signal for generating an " imdct_end " Fourier transformer (POST_IFFT); 상기 전치 역 고속 푸리에 변환기와 복소 역 고속 푸리에 변환기 및 포스트 역 고속 푸리에 변환기와 선택적으로 연결되어 각각의 변환기에서 곱셈-덧셈 또는 곱셈-뺄셈 계산 수행시 산술 연산 동작을 수행해주는 산술연산부(Arithmetic Unit)로 구성된 것을 특징으로 하는 AC-3 디코더의 IMDCT 회로.An Arithmetic Unit that is selectively connected to the pre-inverse fast Fourier transformer, the complex inverse fast Fourier transformer, and the post-inverse fast Fourier transformer to perform arithmetic operations when performing multiplication-addition or multiplication-subtraction calculations in each transducer. And an IMDCT circuit of the AC-3 decoder. 제1항에 있어서, 상기 전치 역 고속 푸리에 변환기 및 복소 역 고속 푸리에 변환기 및 포스트 역 고속 푸리에 변환기는 "bswitch" 신호에 의해 변환길이를 256 샘플 길이 또는 512 샘플 길이로 변환하는 것을 특징으로 하는 AC-3 디코더의 IMDCT 회로.2. The AC inverter of claim 1, wherein the pre-inverse fast Fourier transformer and the complex inverse fast Fourier transformer and the post-inverse fast Fourier transformer convert the conversion length into a 256 sample length or 512 sample length by a "bswitch" signal. 3 IMDCT circuit of the decoder.
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KR100205225B1 (en) * 1996-11-27 1999-07-01 Samsung Electronics Co Ltd Idct method in mpeg audio decoder
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Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695698A (en) * 1992-09-11 1994-04-08 Sony Corp Digital signal coder decoder, digital signal coder and digital signal decorder
KR950703190A (en) * 1993-06-30 1995-08-23 오오가 노리오 Method and apparatus for encoding digital signal, method and apparatus for decoding digitial signal, and recording medium for encoded signals
KR950029923A (en) * 1994-04-27 1995-11-24 김광호 Data Computation Processing Speed Improvement Circuit in Digital Audio Decoder
KR960043830A (en) * 1995-05-22 1996-12-23 김광호 MPEG and AC-3 Combined Digital Audio Signal Decoder
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