KR100793799B1 - Apparatus for generating address and method for processing audio signal using for the same - Google Patents

Abstract

The present invention relates to an address generating apparatus by bit conversion and an audio signal processing using the same. In particular, the present invention can efficiently generate a plurality of address values required in the pre-processing of the high-speed MDCT / IMDCT filter bank operation in one address value, and also, if the dual MAC structure and the memory bus has two or more, Simultaneous loading allows for efficient data movement without the need for additional address generators.

Address, IDMCT, MDCT

Description

Apparatus for generating address and method for processing audio signal using for the same}

1 is a view showing an embodiment of a general address generation device

2 is a diagram showing an example of reverse address generation according to the present invention;

3 is a view showing an embodiment of an address generation device according to the present invention;

4 is a diagram illustrating an embodiment of a reverse address generator of FIG. 3;

5 illustrates an embodiment of the control signal generator of FIG.

6 is a diagram showing an embodiment of an audio signal processing method to which an address generation method according to the present invention is applied;

Explanation of symbols for main parts of the drawings

210: address generator 220: reverse address generator

230: result output unit 610: preprocessing unit

620: IFFT unit 630: post-processing unit

640: reverse interleaver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to address generation of a programmable processor, and more particularly, to an address generation device by bit conversion and an audio signal processing using the same.

Recently, as the demand for multichannel high quality audio increases, the interest in the digital multichannel audio compression algorithm area is increasing. Such multi-channel audio compression algorithms are typically MP3, MPEG2, Dolby AC-3, DTS (Digital theater systems), and most audio compression algorithms are transform coding method using Modified Discrete Cosine Transform (MDCT). After the signal is transformed using, the signal is compressed by allocating bits based on the psychoacoustic model.

However, not only most audio compression algorithms use MDCT-based operations, but also the process of converting a time domain signal into an internal time-frequency representation or performing inverse conversion from the viewpoint of computation amount is the encoding of the audio signal. Or, it takes a relatively large amount of computation in the decoding process. For example, in the case of MP3, the IMDCT processing process generally takes about 42% of the total decoding operation, about 52% for MPEG2, about 50% for Dolby, and MPEG2-AAC. Accounts for about 48%. In other words, the efficient processing of the time-frequency conversion process can greatly reduce the overall load on the processor, contributing to improved performance.

In order to process such IMDCT operations, most compression standards apply a high-speed IMDCT algorithm that can reduce the amount of computation at the algorithm level. The fast IMDCT algorithm is an IMDCT implementation algorithm that is the easiest to implement a hardware for a 2 ^N point IMDCT operation and has a small amount of computation, and is a method of performing an IMDCT operation using an N / 4 point IFFT.

This fast IMDCT algorithm consists of two stages as shown in Equations 1 and 2.

은 N/4 포인트 IFFT 연산이며,

와

는 각각 IFFT 연산의 전처리, 후처리 과정이다. 상기 수학식 2는 역 인터리빙(de-interleaving) 과정으로 yr = real{y(n)}, yi = image{y(n)}를 각각 의미한다.In Equation 1

Is an N / 4 point IFFT operation,

Wow

Are preprocessing and postprocessing processes of IFFT operation respectively. Equation 2 denotes yr = real {y (n)} and yi = image {y (n)} as a de-interleaving process.

When performing a fast IMDCT filterbank operation with a commercially available programmable processor, the complex value of X (N / 2-2k-1) + jX (2k) is represented as X (k) stored in memory to perform the preprocessing process. Should be. However, since it does not support specific instruction and hardware structure to express it directly, when moving real X (k) data stored in memory, X (N / 2-2k-1) data and X (2k) data should be read separately. Inefficiency exists.

1 illustrates a hardware structure for a preprocessing process of a conventional fast IMDCT operation, and includes a first address generator 110, a second address generator 120, and a result outputter 130. The first and second address generator 110 includes an address register for storing an address, and the result output unit 130 adds data read from addresses generated by the first and second address generators 110 and 120. It includes an output adder.

를 곱하는 연산이 필요하다. 이때, X(N/2-2k-1) 데이터와 X(2k) 데이터는 메모리에 저장되어 있고 일반적으로 두개의 주소 생성부(110,120)를 이용해서 X(2k), X(N/2-2k-1)에 해당하는 두 데이터를 읽어오기 위한 메모리 주소를 생성시킨다. 즉, 상기 X(2k) 데이터를 읽어오기 위해서 제1 주소 생성부(110) 는 주소 레지스터를 2씩 포스트 인크리먼트(post increment)시키면서 데이터를 이동하고, X(N/2-2k-1) 데이터를 읽어오기 위해서 제2 주소 생성부(120)는 주소 레지스터를 2씩 포스트 디크리먼트(post decrement)시키면서 데이터를 이동하게 된다.That is, in order to perform the preprocessing process according to Equation 1, X (N / 2-2k-1) + jX (2k) and

You need to multiply by. At this time, the X (N / 2-2k-1) data and the X (2k) data are stored in the memory and generally X (2k) and X (N / 2-2k) using two address generators 110 and 120. Create a memory address for reading two data corresponding to -1). That is, in order to read the X (2k) data, the first address generator 110 moves the data while post-incrementing the address register by 2 and X (N / 2-2k-1). In order to read the data, the second address generator 120 moves the data while post decrementing the address register by two.

However, in a general commercially available programmable processor, most of the post increment / decrement address generation mode supports only +1 and -1, and +2 and -2 do not support well. In addition, since two address registers must be used, resource usage is high, and a processor that can move two data at the same time needs to process +2 and -2 simultaneously. There is this.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method and apparatus for improving the computational performance of a programmable processor.

Another object of the present invention is to provide an apparatus for generating an address through bit conversion with a small hardware resource and an audio signal processing method using the same.

An address generating apparatus according to the present invention for achieving the above object, the address generating unit for generating a first memory address using the address register; A reverse address generator configured to generate a second memory address by inverting each bit of the first memory address using an inverting element; And a result output unit configured to read and output corresponding data from the first and second memory addresses.

In the audio signal processing method according to the present invention, after generating a first memory address corresponding to an input real value, inverting each bit of the first memory address to generate a second memory address, the first and second A preprocessing step of reading the data from the memory address and outputting the data in a complex form; An IFFT step of performing an inverse fast Fourier transform (IFFT) on the complex signal output in the preprocessing step and outputting the signal in the time domain; A post-processing step of processing and outputting the complex signal in the time domain in real form; And deinterleaving the real signal of the post-processing step, wherein the IMDCT is performed on the audio signal.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

In the present invention, when generating an address in a programmable processor, two address values can be simultaneously generated in parallel using only one address generator and simple additional logic. In particular, the present invention allows a single signal generator to generate two specific address values in the same pipeline cycle in a digital signal processor (DSP).

When performing a fast IMDCT filter bank operation with a commercially available programmable processor, the preprocessing process reads the complex value X (N / 2-2k-1) + jX (2k) corresponding to the input X (k) value from the memory first. This is done.

However, looking at the relationship between X (2k) and X (N / 2-2k-1), it can be seen that the relationship is inverse. For example, if input data X (k) is 0, X (0), X (N / 2-1), X (k) is 1, X (2), X (N / 2-3), .. It can be seen that.

FIG. 2 is a diagram illustrating an example of the reverse address generation mode of the present invention. When N is 512, the reverse address 255 (11111111) is generated when the address 0 (00000000) is inverted by the inverter, and the address 2 ( Inverting 00000010 by an inverter generates reverse address 253 (11111101).

In other words, using the inverse addressing mode as shown in FIG. 2, only one data address register and a simple bit manipulation circuit for inverting each corresponding bit of the data address register are complex samples required for preprocessing of a fast IMDCT operation. Can be read from memory in one cycle and moved to the source register, making it very efficient.

3 shows a hardware structure for a fast IMDCT / MDCT filter bank preprocessing operation according to the present invention, and includes an address generator 210, a reverse address generator 220, and a result output unit 230. do.

The address generator 210 includes an address register for storing an address, and the reverse address generator 220 includes an inverter for inverting each address of the address register. The result output unit 230 includes an adder that adds data read from the address generated by the address generator 210 and the reverse address generator 220 and outputs the complex data.

When comparing the present invention with the prior art, as shown in Figure 3, the number of address registers used in the operation is reduced from two to one, and the value of the address register increasing from 0-> 2-> 4-> 8 ... etc. is increased. By converting bit by bit, 0xFF-> 0xFD-> 0xFB-> 0xF9 ... address value can be generated.

If a programmable processor using the hardware structure of the present invention has a dual MAC structure, two data can be simultaneously brought into the source register, which is very advantageous not only in terms of hardware resources but also in terms of operation cycles.

That is, when used in digital audio signal processing using IMDCT filter bank operation in a programmable processor having two or more data memory buses and dual MAC (multiply-accumulate) structures, the address generation time for the preprocessing operation of the IMDCT filter bank This can improve overall processor performance.

FIG. 4 is a detailed block diagram illustrating an example of the reverse address generator of FIG. 3, and includes a plurality of parallel configured mux and MDCT / IMDCT point numbers in order to inversely convert address data generated by the address generator 210 into bits. Accordingly, the control signal generation unit for providing a selection signal to each mux is configured.

In FIG. 4, 14 muxes are provided to represent address data up to 8192 points (14 bits). Each mux inverts and outputs the address data generated by the address generator 210 according to the control signal generated by the control signal generator. That is, each bit of the address data generated by the address generator 210 is applied to the corresponding mux, wherein an address bit not inverted into the first input terminal 0 of the corresponding mux is transferred to the second input terminal 1. The address bits inverted by the inverter are applied. The mux selects an inverted address bit when the corresponding selection signal output from the control signal generator is '0', and selects and outputs an inverted address bit when '1'.

FIG. 5 is a detailed block diagram illustrating an exemplary embodiment of the control signal generator of FIG. 4, and includes a plurality of OR gates 501 ˜ 508 outputting a selection signal by logically combining the upper 8 bits of the number of MDCT / IMDCT points as an input. It consists of.

For example, if the number of MDCT / IMDCT points is 1024, 0001000, which is the upper 8 bits of 00010000000000, is input to the respective OR gates 501 to 507. Then, the output of the OR gate 504 becomes '1', and thus the output of the lower OR gates 506 and 507 becomes '1'. In addition, the output of the OR gate 508 that rings all the upper 8 bits also becomes '1'. The lowest 6-bit MUX control signal is commonly generated at the output terminal of the OR gate 508. Therefore, the lower 14 bit mux select signal is 00001111111111 and is provided to the mux.

Then, the upper four muxes of FIG. 4 select and output address bits that are not inverted, and the lower ten muxes select and output inverted address bits.

For example, if the lower 14-bit address generated by the address generator 210 is 00000011001111 and the number of MDCT / IMDCT points is 1024, the output of each mux is 00001100110000.

As described above, when the IMDCT / MDCT calculation process used in digital audio signal processing is performed by preprocessing, N / 4 point IFFT / FFT, postprocessing, and deinterleaving process, the data movement cycle of the preprocessing process can be effectively reduced. Will be.

6 is a block diagram showing an embodiment of hardware for the fast IMDCT algorithm of the present invention, and includes a preprocessor 610, an IFFT unit 620, a post processor 630, and a reverse interleaving unit 640. It is configured by.

The preprocessor 610 receives an audio signal in real form and converts it into a complex form by applying the address generation process according to the above-described bit conversion of the present invention and then outputs the complex signal to the IFFT unit 620. The IFFT unit 620 converts the complex signal of the preprocessor 610 into a time domain by IFFT and outputs the complex signal to the post processor 630. The post processor 630 converts the output signal of the IFFT unit 620 into a real signal and outputs the signal to the inverse interleaving unit 640. The reverse interleaving unit 640 reversely interleaves the output signal of the post processor 630 and outputs the reverse signal.

For example, MPEG audio technology applies MDCT to a digital filter bank of a decoding block and IMDCT to a digital filter bank of a coding block.

As described above, the present invention can efficiently generate a plurality of address values required in a preprocessing process of a high-speed MDCT / IMDCT filter bank operation from one address value, and also, if there are two or more dual MAC structures and two memory buses, Simultaneously fetching allows efficient data movement without the need for additional address generators.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

According to the address generation method and apparatus and the audio signal processing method using the same according to the present invention described above, in the MDCT / IMDCT filter bank-based digital audio signal processing, the same performance using the less hardware resources than the existing hardware, The operating frequency of the programmable processor can also be lowered. Therefore, in the mobile environment, where chip power consumption is becoming important, the present invention can be applied to any application that uses a programmable processor for processing digital audio signals.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (3)

An address generator configured to generate a first memory address corresponding to an input real value using an address register; A reverse address generator configured to generate a second memory address by inverting each bit of the first memory address using an inverting element; And A result output unit for reading the corresponding data from the first and second memory addresses and outputting a complex signal; The reverse address generator A plurality of muxes for outputting a corresponding bit of the first memory address as it is or inverting the bit; Control signal generator for controlling the output of each mux according to the number of MDCT / IMDCT points Address generation apparatus comprising a. delete After generating the first memory address corresponding to the input real value using the address register, and inverting each bit of the first memory address to generate a second memory address, the corresponding data from the first and second memory addresses A preprocessing step of reading and outputting a complex signal; An IFFT step of performing an inverse fast Fourier transform (IFFT) on the complex signal output in the preprocessing step and outputting the signal in the time domain; A post-processing step of processing and outputting the complex signal in the time domain as a real signal; And And deinterleaving the real signal of the post-processing step, wherein the IMDCT is performed on the audio signal.

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