KR100300277B1 - Apparatus for decoding a variable length code - Google Patents

Abstract

The variable length code decoding processing unit for decoding the variable length code from the code bit string of the compressed image data includes an N length code length detection unit and a variable length code detection unit for detecting different variable length codes, respectively. The code length detection unit has a code length table in which a minimum bit string (code length detection entry) common to a variable length code having the same code length and a code length are associated with each other. The code length of the variable length code is detected. When N = 2, first, the detection start bit of the variable length code with respect to the code bit string in the second-stage variable length code detector is determined based on the code length obtained by the code length detector. In addition, the adder adds the code lengths respectively detected by the code length detection unit, and based on the obtained value, the bit position processing unit stores the code storage register 32 in the code storage register 32 in the next machine cycle and provides the start position of the code bit string provided to the decoding process. To control. For this reason, the decoded data of variable length code according to the stage in one machine cycle is output from each variable length code detection part.

Description

Variable Length Code Decoding Device {APPARATUS FOR DECODING A VARIABLE LENGTH CODE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus for picture compressed data, and more particularly, to a configuration of a decoding device for decoding a variable length code based on a code bit string of picture compressed data consisting of variable length codes.

In the JPEG, MPEG1 and MPEG2 standards, etc., which are known as image compression coding schemes, quantization of discrete cosine transformed (DCT) still image data or moving image data, and Huffman code or the like are performed on the obtained quantized DCT coefficients. The compressed data is further subjected to variable length encoding to obtain compressed data.

In the case where the decoding device for decoding the compressed image data is thus configured with LSI, a variable length code decoder for variable length code decoding the compressed image data, an inverse quantizer for dequantizing the decoded data, and an inverse quantization DCT coefficient An inverse discrete cosine transform unit for inverse discrete cosine transforming to obtain image data, and in the case of MPEG1 or MPEG2, since moving picture compression is performed, motion compensation for performing motion compensation on image data obtained by inverse discrete cosine transform. It is equipped with a part.

In such a compressed image decoding apparatus, it is necessary to decode the image compressed data obtained from the reception or storage medium and supply the decoded display image to the display unit in order to display it, so that the processing speed is required in the circuit block constituting each decoded portion. High speed circuits have been realized for inverse quantization units, inverse discrete cosine transform units, and the like.

In addition, also for the variable length code decoding circuit, the processing speed is demanded as in the other circuits. However, in the variable length code circuit, since the code to be decoded is of variable length, if the decoding of any variable length code does not end, the start bit of the next variable length code cannot be specified, and the speedup by parallel processing is achieved. It is difficult.

Thus, for example, in (Theology Bulletin ICD 94-86 (1994-08) "Development of a Decoding LSI of a 110 MHz MPEG2-adaptive variable length code"), the decoding is performed to speed up the variable length decoding process. Disclosed is a configuration in which circuits are separated and pipelined. In this configuration, the variable length code decoding circuit separates the variable length code decoding circuit into a cut section of the variable length code, a run level detection unit from the variable length code, and the like. During the processing, run level detection is performed on the truncated variable length code. In addition, the level represents a DCT coefficient other than "0" in the code bit string obtained by zigzag scanning of the provided one-block data (quantized DCT coefficients), and the run is continued prior to the level. The number of "0" is shown.

However, in the conventional variable length code decoding circuit, the variable length code is cut using the variable length code data using the standardized Huffman code to obtain a run level output corresponding to the variable length code, and at the same time, The code length was detected from the length code. For this reason, in order to know the code length of the variable length code, all of the 114 variable length codes stored in the table must be compared with the code bit string. Therefore, the speedup of the processing speed in the variable length code decoding process does not progress very much.

Further, in the above-described configuration of the variable length code decoding circuit, the cutting process of the variable length code itself is not parallelized, and the cutting of the variable length code from the code bit string of the compressed image data is performed by one code / 1 cycle (1 Machine cycle), and the processing speed is not significantly improved.

In the case of decoding a moving image, in particular, it is necessary to cope with high resolution while maintaining the number (frame rate) of the pictures decoded and displayed for one second. Therefore, it is considered to correspond to such high resolution by increasing the operation frequency of the one cycle, that is, the circuit. Here, the resolution used in a digital video disk, a digital TV, or the like is 720 pixels x 480 pixels, which can be coped to some extent by the improvement of the operating frequency. However, when corresponding to a higher resolution of 1440 pixels x 1080 pixels, there is a limit in raising the operating frequency of the circuit to correspond.

On the other hand, it is necessary to respond to a request for reduction of power consumption in the LSI circuit, and for this purpose, it is effective to lower the operating frequency of the circuit. However, since decoding of the display image must maintain the frame rate, in order to lower the operating frequency while maintaining the frame rate, the decoding process is not accompanied by the cutting speed of a variable length code of 1 code / 1 cycle. There is.

This invention is made | formed in order to solve the said subject, and it aims at speeding up the decoding process of a variable length code. Another object of the present invention is to provide a variable length code decoding apparatus capable of decoding a plurality of variable length codes in one machine cycle.

In order to achieve the above object, the variable length code decoding apparatus according to the present invention has the following features.

That is, in a variable length code decoding apparatus for performing a decoding process on a code bit string of data having a variable length code, a plurality of stages of code length detection means for detecting a code length of the variable length code from a code bit string and a code bit And variable length code detecting means for decoding means for detecting the variable length code from a column and outputting corresponding variable length code decoded data. The detection start bit of the variable length code with respect to the code bit string in each variable length code detection means is controlled based on the code length detected by the plurality of code length detection means.

In this way, a plurality of stages (N stage) of code length detection means and variable length code detection means are provided, and based on the code lengths detected by the code length detection means, respectively, for the code bit strings in the variable length code detection means. Controls the detection start bit of variable length code.

Further, in a variable length code decoding apparatus for performing a decoding process on a code bit string of data having a variable length code, a plurality of stages of code length detection means for detecting a code length of the variable length code from the code bit string, respectively, A plurality of stages of variable length code detecting means for detecting the variable length code from a code bit string and outputting corresponding variable length code decoded data, and the code length detected by code length detecting means up to a predetermined stage of the plurality of stages. Detection start bit control means for controlling the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means in the next stage based on the total length.

Taking N = 2 as an example, the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means in the second stage is determined based on the code length obtained in the code length detection means in the first stage. Further, based on the code lengths detected by the code length detection means in the first stage and the code length detection means in the second stage, the start position of the code bit string of the variable length code to be processed in the next machine cycle is controlled.

Therefore, decoded data of variable length code in the unit machine cycle period, i.e., in one machine cycle, is output from each variable length code detecting means.

As described above, by parallelizing the decoding processing units having the variable length codes and decoding the plurality of variable length codes within one machine cycle, the present invention can achieve a markedly higher speed of the decoding processing speed.

In addition, since a plurality of variable length codes can be detected within one machine cycle, the operating frequency of the variable length code decoding device can be lowered, and power consumption can be reduced when the device is LSI-ized.

In addition, when the image data to be handled becomes higher resolution, for example, even when the present invention is used in a high resolution system such as an HDTV, a plurality of variable length codes can be detected within one machine cycle, so that the operating frequency of the apparatus is increased. It is possible to obtain the decoding processing speed of the required variable length code without raising.

In addition to the above configuration, the present invention includes detection start bit control means (point selector in the following embodiment), code storage register, and bit position control means. Then, the detection start bit control means controls the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means in the next stage based on the code length detected by the code length detection means up to the predetermined stage. The code storing register sequentially stores the code bit strings for each unit machine cycle and supplies them to the variable length code detecting means and the code length detecting means, and the bit position control means adds the code lengths respectively detected by the code length detecting means. Based on this, the storage start bit position of the code bit string stored in the code storage register at the timing of the next machine cycle is controlled.

In addition, the variable length code decoding device according to the present invention has another aspect as follows.

A variable length code decoding apparatus for decoding a code bit string of data having a variable length code, comprising: code length detection means for detecting a code length of the variable length code from a code bit string, and the variable length from a code bit string And variable length code detecting means for detecting a code and outputting corresponding variable length code decoded data. The code length detection means further includes a code length table in which the common minimum bit strings common in the variable length codes of the same code length and the code lengths of the corresponding variable length codes are stored. Compares the common minimum bit string of the code length table with the supplied code bit string, detects the common minimum bit string, and outputs the code length of the corresponding variable length code.

The code length detection means refers to such a code length table, and obtains the code length by cutting the bit string corresponding to the common minimum bit string stored in the table from the variable length code bit string without truncating the variable length code itself.

Although there are many 114 variable length codes defined, the number of common minimum bit strings required to specify the code length is very small compared with the 114 types. For this reason, the code length detection can be performed within a very short period compared with the time required for the variable length code detector to cut the variable length code from the code bit string to obtain the decoded data. In addition, the circuit scale required for the detection of the code length is also reduced.

Further, in still another aspect of the present invention, in addition to the above configuration, the code length detecting means includes a plurality of stages of code length detecting means for detecting the code lengths of the variable length codes consecutive from the code bit strings. The detecting means comprises a plurality of stages of variable length code detecting means for detecting a variable length code corresponding to the code length detected by the code length detecting means from the code bit string, and the code lengths detected by the plurality of code length detecting means. Based on this, the detection start bit of the variable length code with respect to the code bit string in each variable length code detection means is controlled.

In addition to the above configuration, the present invention controls the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means of the next stage based on the code length detected by the code length detection means up to the predetermined stage. Detection start bit control means. The code storage register is sequentially stored for each unit machine cycle and supplied to the variable length code detecting means and the code length detecting means, and based on the addition value of each code length detected by each code length detecting means. And bit position control means for controlling the storage start bit position of the code bit string stored in the code storage register at the timing of the next machine cycle.

Further, the present invention is characterized in that different variable length codes are detected by respective variable length code detecting means within a unit machine cycle period, and a plurality of decoded data corresponding to the detected variable length codes are output.

In the present invention, the code length detecting means comprises a plurality of code length detecting means for detecting the code lengths of the variable length codes consecutive from the code bit string, and the variable length code detecting means. Is composed of a plurality of stages of variable length code detection means for respectively detecting a variable length code corresponding to the code length detected by the code length detection means from the code bit string, and a predetermined stage of the plurality of stages of variable length code detection means. Detection start bit control means for controlling the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means of the next stage based on the total length of the code lengths detected by the code length detection means up to It is provided.

In the above configuration, the N-stage code length detection means and the variable length code detection means are provided, and are variable with respect to the code bit string in each variable length code detection means based on the code lengths detected by the code length detection means, respectively. Controls the detection start bit of the length code.

Thus, without cutting off the variable length code itself, the code length is detected by referring to the code length table, and the detection start bit of the variable length code with respect to the code bit string in each variable length code detection means is controlled. It becomes easy to make a decoding apparatus into a multistage structure. Therefore, a plurality of variable length codes can be detected within one machine cycle, the operating frequency of the variable length code decoding device can be lowered, and power consumption when the device is LSI-ized is reduced.

In addition, when the image data to be handled becomes higher resolution, for example, even when the apparatus is used in a high resolution system such as an HDTV, a plurality of variable length codes can be detected within one machine cycle. It is possible to obtain the decoding processing speed of the necessary variable length code without raising.

BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a diagram showing a schematic configuration of a decoding device of compressed image data according to an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of the variable length code decoding processing unit 12 of FIG.

3 is a diagram illustrating a configuration of a code length table of FIG. 2.

4 is a diagram illustrating a configuration of a variable length code table.

5 is a diagram showing another configuration of the variable length code decoding processing unit 12 of FIG.

<Explanation of symbols for the main parts of the drawings>

10: header detection parameter separation unit

12: variable length code decoding processing unit

14: dequantization unit

16: inverse discrete cosine transform unit

18: motion compensation unit

20: picture memory

22: Memory area for I picture

24: Memory area for P picture

26: display memory

32: sign storage register

34, 44: variable length code table

36, 38, 46, 48: comparators

40, 50: Sign length table

42, 42-2: point selector

52, 52-2: adder

54: bit position processing unit

60-1, 60-2, 60-3: variable length detector

62-1, 62-2, 62-3: code length detector

(Embodiment of the Invention)

EMBODIMENT OF THE INVENTION Hereinafter, embodiment (henceforth an embodiment) of this invention is described using drawing. In addition, the same code | symbol is attached | subjected to the part corresponding to drawing already demonstrated, and description is abbreviate | omitted.

[Configuration of Decoding Device for Compressed Image Data]

1 shows a schematic configuration of a decoding device of compressed image data according to the present embodiment. In the present embodiment, an explanation will be given taking an apparatus for decoding moving image compressed data as an example.

The code bit string of the moving picture compressed data obtained by the storage medium or the like or the like is supplied to the header detection / parameter separator 10, where the header of each layer is first detected from the code bit string having a hierarchical structure. On the basis of the detected header of each layer, the parameters are separated for each parameter, that is, GOP (Group of Pictures), pictures of I, B, and P, a macro block (MB) constituting each picture, and 8 × constituting the macro block. 8 pixel blocks are separated.

Next, the variable length code decoding processing unit 12, which is a feature of the present embodiment, cuts the variable length code into multiple (N) codes / 1 cycle as described later from the variable length code bit string separated for each unit block. The run-level output corresponding to the variable length code, that is, the quantized DCT coefficient code string is output.

The code string of the quantized DCT coefficients from the variable length code decoding processing unit 12 is supplied to the inverse quantization unit 14 to inverse quantization, and the inverse discrete cosine transform unit 16 converts the inverse quantized DCT coefficients before the DCT conversion. The data is inversely converted into each data.

When the image data obtained by the inverse discrete cosine transform is an I picture (in-frame coded image), the motion compensation unit 18 outputs this to the display memory 26 of the image memory 20 as it is, and furthermore, the memory for the I picture. It also outputs to the area 22. The I picture memory area 22 is then stored with the data of the I picture until the next I picture is obtained as the reference image 1.

In the case of a P picture (inter-frame forward predictive coded image), the motion compensator 18 outputs P picture data to the P picture memory area 24, and simultaneously reads I picture data from the memory area 22. Operation compensation is performed by adding to the P picture data, and the obtained decoded display image is stored in the display memory 26 once. In addition, similarly to the I picture, the P picture memory area 24 is stored as the reference picture 2 until the next P picture is obtained.

In the case where the image data obtained by the inverse discrete cosine transform is a B picture (bidirectional predictively coded image), I or P picture data stored in the memory areas 22 and 24, respectively, is added to the B picture data to perform motion compensation. The obtained decoded display image is once stored in the display memory 26.

As described above, the decoded display image after the motion compensation sequentially obtained based on the I picture, the P picture, and the B picture is displayed on a display (not shown), for example, [I picture, B picture, B picture, P picture, B picture, B picture, P picture. ,… , I picture].

[Configuration of Variable Length Code Decoding Processing Unit]

Next, the specific configuration of the variable length code decoding processing unit 12 of FIG. 1 having the variable code detection unit and the code length detection unit will be described with reference to FIG.

The variable length code bit string is supplied to the code storage register 32 from the header detection and parameter separation unit 10 of FIG. In the code storing register 32, the variable length coded bit string has a predetermined number of bits per one machine cycle (specifically, the maximum number of bits × number of stages (N) based on the control of the bit position processing unit 54. Are stored one by one. In the present embodiment, when the variable length coded bit string output from the header detection and parameter separation unit 10 shown in FIG. 1 is in the order of the variable length codes A, B, C, D, ..., the singular number (N = 2) In this case, the code storing register 32 stores, for example, a bit string of two variable length codes A and B in the first one machine cycle.

The variable length code bit strings output from the code storage register 32 are supplied to the variable length code detector 60-1 and the code length detector 62-1 in the first stage, respectively. This variable length coded bit string is also supplied to the point selector 42. The point selector 42 is a variable length code detection unit 60-2 and code length detection unit 62-2 at a later stage, based on the code length LA detected by the code length detection unit 62-1 as described later. The start start bit point of the variable length code bit stream into the row, i.e., the start bit of the variable length code B following the variable length code A. Therefore, from the point selector 42, the variable length code bit string, that is, the bit string of the variable length code B from the designated bit, is the variable length code detector 60-2 and the code length detector 62-2 of the second stage. ) Will be supplied.

The code length detectors 62-1 and 62-2 of the N-stage (N = 2) include the comparators 38 and 48 and the code length tables 40 and 50, respectively, and the code length tables 40 and 50 respectively. As shown in Fig. 3 to be described later, the common minimum bit string and the code length of the variable length code are stored correspondingly. Each of the comparators 38 and 48 compares the variable length coded bit strings supplied to the common minimum bit strings stored in the code length tables 40 and 50, and compares the corresponding code lengths LA and LB. Output

The code length LA output from the first-stage code length detection section 62-1 is supplied to the point selector 42 as described above, used for designating the supply start bit point of the variable length code bit string, and adder. It is also supplied to 52.

The code length LA and the code length LB detected by the second code length detection part 62-2 are supplied to the adder 52. The adder 52 obtains the sum of the code length LA and the code length LB on the basis of these, and outputs the operation result to the bit position processor 54.

The bit position processing unit 54 selects the start bit of the variable length code C following the variable length codes A and B in the variable length code bit string based on the sum output of the code lengths from the adder 52. The read start position of the code bit string to the code storage register 32 in the next machine cycle is controlled.

In addition, each variable length code detection unit 60-1, 60-2 includes comparators 36, 46 and variable length code tables 34, 44, respectively. It is the structure as shown in FIG. 4, Comprising: Standard variable length codes, such as a Huffman code, and the run level corresponding to these are stored correspondingly. Each of the comparators 36 and 46 compares the variable length code bit strings supplied with the 114 variable length codes in Fig. 4 to cut variable length codes A and B from the variable length code bit strings. The run level outputs A 'and B' corresponding to the length codes A and B are output.

[Configuration of Code Length Detection Unit]

Next, the structure of each code length detection part 62-1, 62-2 of this embodiment, and more specifically, the structure of code length table 40, 50 is demonstrated.

3 shows the configuration of the code length tables 40 and 50. A characteristic of the code length table shown is that a common minimum bit string (code length detection entry) and a code length necessary for knowing the code length of the variable length code are stored in correspondence with each other. The code length detectors 62-1 and 62-2 of the embodiment can detect the code length without detecting the variable length code itself.

Since the variable length code is fixedly assigned in accordance with the probability of occurrence of the run level as shown in Fig. 4, when the variable length code is specified and the code length of the variable length code is detected, for example, currently defined All of the 114 variable length codes and the variable length code bit strings from the code storage register 32 must be compared.

However, this variable length code can detect the code length without specifying any of 114 types as shown in FIG. For example, in Fig. 4, there are eight kinds of variable length codes of code lengths 9. That is, even if either of [00100110s] or [00100001s] is input as the code bit string, the code length is nine. Each variable length code of these code lengths 9 has the first 5 bits in common. Therefore, in the code length table shown in FIG. 3, a constant code length is set for a common minimum bit string of a variable length code having the same code length. For example, a code length (for a common minimum bit string) is set. 9) is set.

In this way, by configuring the code length table as the code detection entry using the common minimum bit string, the code length can be detected without checking even the last bit of the variable length code.

Further, as the number of bits of the variable length code increases, the type of the variable length code having the same code length increases, but it is not necessary to specify the variable length code itself in the code length detectors 62-1 and 62-2. Therefore, as shown in Fig. 3, the code length table has only 16 common minimum bit strings and the code length corresponding thereto. Therefore, the number of comparisons in each of the comparators 38 and 48 of the code length detection units 62-1 and 62-2 is remarkably compared with the case where the variable length code detection unit compares with all 114 variable length codes. Less. Also for this reason, the detection of the code length is performed more quickly.

3, code length "2" or "3" is associated with code length detection entry "11". The code length is determined by, for example, whether the code bit string is the head of a block constituting the macro block. In addition, it is determined by the block detection position signal provided in the header detection signal supplied separately from the header detection and parameter separation unit 10 of FIG. 1 and the variable length code decoding processing unit 12 of FIG. Can be.

In the figure, the code length "Escape" corresponding to the code length detection entry "000001" differs depending on the image compression method. For example, in the case of MPEG2, the code length is "24".

As described above, in the present embodiment, the code length detectors 62-1 and 62-2 are provided, and the code length detectors 62-1 and 62-2 do not cut the variable length code itself in common, and thus the common minimum bits. By cutting the columns, it is possible to detect the respective code lengths LA and LB in a very short period of time. Therefore, as described above, when the variable length code decoding processing unit is parallelized, the variable length code detection unit 60-2 in the second stage can cut the variable length code B more quickly.

In addition, the adder 52 has a code length A at a relatively early time before one machine cycle ends. Since the data of code lengths LA and LB] are supplied in the case of multiplexing, the bit position processing section 54 must store the code storage register 32 in the next machine cycle based on the sum of these code lengths. The starting position of the variable length code bit string can be specified more quickly.

In addition, when the variable length code detection is parallelized as in the present embodiment, N variable length codes corresponding to the number N in each machine cycle are truncated, and corresponding N run level outputs are obtained. However, it is possible to speed up the decoding process of the variable length code.

In the variable length code decoding processing unit shown in Fig. 2, when the number N is larger than 2, N = 3 is taken as an example, for example, the configuration shown in Fig. 5 is applicable.

First, the configurations of the variable length code detector and the code length detector of the first and second stages are the same as in FIG. The extended point selector 42-for the supply start bit positions of the code bit strings supplied from the code storage register 32 to the variable-length code detector 60-3 and the code length detector 62-3 in the third stage. 2) is controlled based on the sum output of the code lengths LA and LB from the adder 52, and it is set from the beginning of the bit string of the variable length code C.

The sum output of the code lengths LA and LB from the adder 52 and the code length LC detected by the third-length code length detection unit are inputted into the adder 52-2, and the adder ( 52-2) obtains these three sums (LA + LB + LC) and outputs them to the bit position processor 54.

Even in the case of N> 3, it is possible to cope with the addition of the point selector and the adder as well.

As described above, the variable length code decoding apparatus according to the present invention can speed up the decoding process of the variable length code, and can perform the decoding process for the plurality of variable length codes in one machine cycle.

Claims (9)

A variable length code decoding apparatus for performing a decoding process on a code bit string of data having a variable length code, A plurality of code length detection means for detecting a code length of the variable length code from the code bit string; A plurality of stages of variable length code detecting means for detecting the variable length code from the code bit string and outputting corresponding variable length code decoded data; Detection start bit control means for controlling the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means in the next step based on the code length detected by the code length detection means up to a predetermined stage; A code storage register for sequentially storing the code bit strings for each unit machine cycle and supplying the variable length code detection means and the code length detection means; and Bit position control means for controlling the storing start bit position of the code bit string stored in the code storing register at the next machine cycle timing based on the addition value of the code length detected by the respective code length detecting means, respectively. Variable length code decoding device comprising a. The variable length code detecting means for detecting the different variable length codes in the unit machine cycle period and outputting a plurality of decoded data corresponding to the detected plurality of variable length codes in the unit machine cycle period. Variable length code decoding device. A variable length code decoding apparatus for performing a decoding process on a code bit string of data having a variable length code, A plurality of code length detection means for detecting the code length of the variable length code from the code bit string, respectively; A plurality of stages of variable length code detecting means for detecting the variable length code from the code bit string and outputting corresponding variable length code decoded data; Based on the total length of the code lengths detected by the code length detection means up to a predetermined one of the plurality of stages, the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means of the next stage is controlled. Detection start bit control means A code storage register for sequentially storing the code bit strings for each unit machine cycle and supplying the variable length code detecting means and the code length detecting means to each of the variable length code detecting means, and A bit position control unit for controlling the storing start bit position of the code bit string stored in the code storing register at the next machine cycle timing based on the addition value of the respective code lengths detected by the respective code length detecting means, respectively. Variable length code decoding device comprising a. A variable length code decoding apparatus for performing a decoding process on a code bit string of data having a variable length code, Code length detecting means for detecting a code length of the variable length code from the code bit string; and Variable length code detecting means for detecting the variable length code from the code bit string and outputting corresponding variable length code decoded data And The code length detecting means comprises a code length table in which a common minimum bit string common to a variable length code having the same code length and a code length of a corresponding variable length code are stored in association with each other, and the common minimum bit of the code length table. A code length of a variable length code is detected by comparing a string and the code bit string; The code length detecting means comprises a plurality of code length detecting means each detecting a code length of the variable length code consecutive from the code bit string; The variable length code detecting means comprises a plurality of stages of variable length code detecting means for detecting variable length codes corresponding to code lengths detected by the code length detecting means from the code bit string, A variable length code decoding device characterized by controlling the detection start bit of the variable length code with respect to the code bit string in the variable length code detection means based on the code lengths detected by the plurality of code length detection means . The variable length code of the variable length code detecting means detects a different variable length code and outputs a plurality of decoded data corresponding to the detected plurality of variable length codes within a unit machine cycle period. Variable length code decoding device. 5. The method according to claim 4, wherein the detection start bit of the variable length code with respect to the code bit string in the variable length code detecting means of the next stage is controlled based on the code length detected by the code length detecting means up to a predetermined stage. Detection start bit control means, A code storage register for sequentially storing the code bit strings for each unit machine cycle and supplying the variable length code detecting means and the code length detecting means to each of the variable length code detecting means, and A bit position control unit for controlling the storing start bit position of the code bit string stored in the code storing register at the next machine cycle timing based on the addition value of the respective code lengths detected by the respective code length detecting means, respectively. Variable length code decoding device further comprising. 7. The method according to claim 6, wherein different variable length codes are detected by the variable length code detecting means in unit machine cycle periods, and a plurality of decoded data corresponding to the detected plurality of variable length codes are output. Variable length code decoding device. The code bit string in the variable length code detecting means of the next stage is based on the total length of the code lengths detected by the code length detecting means up to a predetermined stage among the variable length code detecting means of the plurality of stages. And a detection start bit control means for controlling a detection start bit of the variable length code for the variable length code. 9. The apparatus according to claim 8, further comprising: a code storage register for sequentially storing the code bit strings for each unit machine cycle and supplying the variable length code detection means and the code length detection means; A bit position control unit for controlling the storing start bit position of the code bit string stored in the code storing register at the next machine cycle timing based on the addition value of the respective code lengths detected by the respective code length detecting means, respectively. Variable length code decoding device further comprising.

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