JPH06244736A - Encoder - Google Patents

Abstract

PURPOSE:To improve an encoding efficiency by successively reading a predicted part, and variable length-encoding it. CONSTITUTION:A hierarchizing circuit 50 hierarchizes a quantized output from a quantizing circuit 15. A variable length encoding circuit 70 reads the output of the hierarchizing circuit 50, and variable length-encodes it. At that time, the variable length encoding circuit 70 reads the part predicted by using the hierarchized output of the higher layer in advance. The quantized output turned to 0 by the prediction is successively read, and the number of code words of the variable length encoding circuit 70 is decreased. Thus, the encoding efficiency can be improved.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device for hierarchically coding a video signal.

[0002]

2. Description of the Related Art In recent years, digital compression of images has been studied. In particular, various standardization proposals have been proposed for high-efficiency coding using DCT (discrete cosine transform). The high-efficiency coding technique is for coding image data at a smaller bit rate in order to improve the efficiency of digital transmission and recording. The DCT divides one frame into a plurality of blocks (m pixels × n horizontal scanning lines) and converts the video signal into frequency components in units of these blocks, thereby reducing redundancy in the spatial axis direction. In high-efficiency coding, not only is compression by DCT (intraframe compression) performed within one frame, but interframe compression that reduces the redundancy in the time axis direction by utilizing the correlation between frames is also adopted. The inter-frame compression is to further reduce the bit rate by utilizing the property that a general moving image is very similar to the preceding and following frames and obtaining the difference between the preceding and following frames and performing the DCT process on the difference value. .

FIG. 6 is a block diagram showing a conventional coding apparatus adopting such high efficiency coding.

The luminance signal Y and the color difference signals Cr and Cb are given to a multiplexing processing circuit 11 and multiplexed in block units of m pixels × n horizontal scanning lines. For example, for the color difference signals Cr and Cb, the sampling rate in the horizontal direction is set to 1/2 of the luminance signal Y. In this case, one m × n block of the color difference signals Cr and Cb is sampled during a period in which two m × n luminance blocks are sampled. The multi-processing circuit 11 configures a macro block by two luminance blocks Y and four color difference blocks Cr and Cb. The two luminance blocks Y and the respective color difference blocks Cr and Cb represent the same position on the screen. The output of the multi-processing circuit 11 is DC through the subtractor 12.
It is given to the T circuit 13.

When performing the intra-frame compression, as will be described later, the switch 14 is off, and the output of the multi-processing circuit 11 is directly input to the DCT circuit 13 via the subtracter 12. A signal in which one block is composed of m × n pixels is input to the DCT circuit 13, and the DCT circuit 13 is an m × n two-dimensional D
The input signal is converted into frequency components by CT (discrete cosine transform) processing. This makes it possible to reduce spatial correlation components. That is, the output (transformation coefficient) of the DCT circuit 13 is given to the quantization circuit 15, and the quantization circuit 15 requantizes the transformation coefficient with a predetermined quantization coefficient to reduce the redundancy of the signal of one block. . A block pulse is supplied to the multiplexing processing circuit 11, the DCT circuit 13, the quantization circuit 15 and the like which operate in block units.

The quantized data from the quantizing circuit 15 is given to the variable length coding circuit 16 and, for example, Huffman coding is performed based on the result calculated from the statistical code amount of the quantized output. As a result, data having a high appearance probability is assigned a short bit, and data having a low appearance probability is assigned a long bit to further reduce the transmission amount. In this way, the intra-frame compressed encoded output is obtained from the variable length encoding circuit 16.

The output of the variable length coding circuit 16 is also given to the code amount control circuit 18. The data amount of the output data greatly changes depending on the input image. Therefore, the code amount control circuit
Reference numeral 18 monitors the output data amount from the variable length coding circuit 16 and controls the quantization coefficient of the quantization circuit 15 to adjust the output data amount. The code amount control circuit 18 may control the variable length coding circuit 16 to limit the output data amount.

On the other hand, when the switch 14 is on,
The current frame signal from the multiplex processing circuit 11 is subtracted from the motion compensated previous frame data, which will be described later, in the subtracter 12 and is applied to the DCT circuit 13. That is, in this case, interframe coding is performed in which the difference data is coded by utilizing the redundancy of images between frames. In inter-frame coding, if the difference between the previous frame and the current frame is simply obtained, the difference becomes large when the image has a motion. Therefore, the position of the previous frame corresponding to the predetermined position of the current frame is obtained to detect the motion vector,
By calculating the difference at the pixel position corresponding to the motion vector, motion compensation is performed to reduce the difference value.

That is, the output of the quantization circuit 15 is also given to the inverse quantization circuit 21. The quantized output is inversely quantized by the inverse quantization circuit 15, and further inverse DC by the inverse DCT circuit 22.
T-processed and restored to the original video signal. In the DCT processing, requantization, inverse quantization, and inverse DCT processing, the original information cannot be completely reproduced, and some information is lost. In this case, since the output of the subtractor 12 is difference information, the output of the inverse DCT circuit 22 is also difference information. Inverse DCT
The output of the circuit 22 is given to the adder 23. The output of the adder 23 is fed back through a variable delay circuit 24 and a motion correction circuit 25 which delays the signal for about 1 frame period, and the adder 23 adds the difference data to the data of the previous frame and the data of the current frame. Is reproduced and output to the variable delay circuit 24.

The previous frame data from the variable delay circuit 24 and the current frame data from the multiplex processing circuit 11 are applied to the motion detection circuit 26 to detect a motion vector. The motion detection circuit 26 obtains a motion vector by, for example, full search type motion detection by matching calculation. In full search type motion detection, the current frame is divided into predetermined blocks, and a search range of, for example, horizontal 15 pixels × vertical 8 pixels is set in each block. For each block, matching calculation is performed in the corresponding search range of the previous frame to calculate the approximation between patterns. Then, the block of the previous frame that gives the minimum distortion in the search range is calculated, and the vector obtained by the block of the current frame is detected as the motion vector. The motion detection circuit 26 outputs the calculated motion vector to the motion correction circuit 25.

The motion correction circuit 25 extracts the data of the corresponding block from the variable delay circuit 24, corrects it according to the motion vector, outputs it to the subtracter 12 via the switch 14, and after the time adjustment. Output to the adder 23. Thus
The motion-compensated previous frame data is supplied from the motion compensation circuit 25 to the subtracter 12 via the switch 14, and when the switch 14 is on, the inter-frame compression mode is set. It is in compression mode.

The switch 14 is turned on and off based on the motion determination signal. That is, the motion detection circuit 26 creates a motion determination signal depending on whether or not the magnitude of the motion vector exceeds a predetermined threshold value and outputs it to the logic circuit 27. The logic circuit 27 controls on / off of the switch 14 by a logic judgment using the motion judgment signal and the refresh cycle signal. The refresh cycle signal is a signal indicating the intra-frame compressed frame I. When the refresh cycle signal indicates that the frame I is input, the logic circuit 27 turns off the switch 14 regardless of the motion determination signal.
When the motion determination signal indicates that the motion is relatively fast and the minimum distortion due to the matching calculation exceeds the threshold value, the logic circuit 27 turns off the switch 14 even if the frame P is input, and the block unit is selected. In-frame compression coding is performed with. Table 1 below shows ON / OFF control of the switch 14 by the logic circuit 27.

[0013]

[Table 1] FIG. 7 is a block diagram showing a decoding device.

On the decoding side, the encoded signal is given to the variable length decoding circuit 33 via the code buffer memory circuit 32.
The variable length decoding circuit 33 decodes the input coded signal into fixed length data. The code buffer memory circuit 32 may be omitted.

The output of the variable length decoding circuit 33 is an inverse quantization circuit.
Inverse quantization is performed in 34, and inverse DC is performed in the inverse DCT circuit 35.
T processing, decoding to the original video signal, terminal a of the switch 36
Give to. On the other hand, the output of the variable length decoding circuit 33 is also given to the header signal extraction circuit 37. The header signal extraction circuit 37 retrieves a header indicating whether the input data is the intra-frame compressed data or the inter-frame compressed data and outputs it to the switch 36. The switch 36 selects the terminal a and outputs the decoded data from the inverse DCT circuit 35 when the header indicating the in-frame compressed data is given.

The interframe compressed data is obtained by adding the output of the inverse DCT circuit 35 and the output of the previous frame from the predictive decoding circuit 39 by the adder 38. That is, the output of the variable length decoding circuit 33 is the motion vector extraction circuit 40.
To obtain the motion vector. This motion vector is given to the predictive decoding circuit 39. On the other hand, the decoded output from the switch 36 is delayed by the frame memory 41 for one frame period. The predictive decoding circuit 39 motion-compensates the decoded data of the previous frame from the frame memory 41 with the motion vector and outputs the motion-compensated data to the adder 38. The adder 38 adds the output of the predictive decoding circuit 39 and the output of the inverse DCT circuit 35 to decode the data compressed between frames and outputs the decoded data to the terminal b of the switch 36. When the inter-frame compressed data is input, the switch 36 selects the terminal b by the header and outputs the decoded data from the adder 38. In this way, the compression and decompression operations are performed without delay in both the intra-frame compression mode and the inter-frame compression mode.

By the way, as described above, the DCT circuit 13
Outputs a transform coefficient by orthogonally transforming an input signal by two-dimensional DCT processing. The transform coefficients from the DCT circuit 13 are sequentially arranged from horizontal and vertical low frequency components to high frequency components. For example, when processing is performed in block units of 8 × 8 pixels, 64 transform coefficients of 8 × 8 that are sequentially arranged horizontally and vertically from a low band to a high band are generated. The conversion coefficient consists of one DC coefficient indicating the average value of all data and 63 AC coefficients, and is read from the horizontal and vertical low frequencies to high frequencies, that is, the DC coefficients are sequentially zigzag scanned and read. It

In the case of a relatively coarse pattern, the value of the high frequency component of the conversion coefficient is small, and the quantized output of the high frequency component is zero. That is, a rough image can be reproduced by transmitting only the low band of the conversion coefficient, and a fine image can be reproduced by transmitting the high band component. When the transform coefficient is inversely transformed, a reproduced image having the number of pixels corresponding to the number of transform coefficients is obtained. That is, when only the low band of the transform coefficient is inversely transformed, the reproduced image of each block becomes a reduced image according to the number of transform coefficients. Therefore, when it is not possible to set a sufficient transmission rate, when only a part of the bitstream is used for reproduction like special reproduction in a VTR, or when a small screen is displayed using a part of the bitstream. Considering this, a method of layering and quantizing transform coefficients may be adopted.

FIG. 8 is an explanatory diagram for explaining this hierarchization. FIG. 8A shows a layer (hereinafter, referred to as layer 2 × 2) for encoding the low-frequency 2 × 2 portion (hatched portion) of each block, and FIG. 8B shows the low-frequency region of each block. FIG. 8C shows a layer (hereinafter, referred to as a layer 4 × 4) in which a 4 × 4 portion (hatched portion) is encoded, and FIG.
Layer (hatched portion) will be encoded (hereinafter referred to as layer 8 × 8).
It means that).

In the hierarchy 2 × 2, as shown by the slanted lines in FIG. 8A, low-frequency 2 × 2 transform coefficients including DC coefficients among 8 × 8 transform coefficients are used. These four transform coefficients are quantized, further variable-length coded and output. Tier 4
In x4, up to 4x4 transform coefficients in the low frequency band are quantized and variable length coded, and output together with the coded output of layer 2x2. Similarly, in the layer 8 × 8, the transform coefficients in the entire region are quantized and variable-length coded, and are output together with the encoded outputs of the layer 2 × 2 and the layer 4 × 4. For example, depending on the transmission rate, it is determined whether to transmit up to layer 2 × 2, up to layer 4 × 4, or up to layer 8 × 8.

On the other hand, on the decoding side, it is possible to reproduce an image with a definition according to which layer the decoding is performed. For example, when a layer 2 × 2 coded output is decoded, a relatively coarse image can be reproduced, and when a layer 8 × 8 coded output is used for decoding, a fine image is reproduced. be able to.

FIG. 9 is a block diagram showing a conventional coding apparatus in which coding is hierarchical as described above. FIG. 10 is a block diagram showing a specific configuration of the hierarchized circuit in FIG.
Further, FIG. 11 is an explanatory diagram showing an example of zigzag scanning for each layer, and FIG. 12 is a quantized output q (2 ×) for each layer.
It is an explanatory view for explaining 2), q (4x4), and q (8x8). The mark x in FIG. 12 indicates a coefficient which is not zero.

The coding apparatus of FIG. 9 gives the quantized output of the quantizing circuit 15 to the layering circuit 50 and the output of the layering circuit 50 to the variable length coding circuit 51 and the dequantizing circuit 21. The variable length coding circuit 51 is adapted to perform variable length coding on the quantized output of each layer from the layering circuit 50 and output it. The encoded output of the variable length encoding circuit 51 is given to the encoding control circuit 53. The coding control circuit 53 controls the quantization coefficient of the quantization circuit 15 based on the code amount of the coded output, and also controls the variable length coding circuit 51 to suppress the total code amount within the set code amount.

Now, it is assumed that the DCT circuit 13 performs two-dimensional DCT conversion in block units of 8 × 8 pixels. The 64 transform coefficients from the DCT circuit 13 are quantized in the quantization circuit 15 and given to the layering circuit 50. Hierarchical circuit 50
Of the quantized output of the quantization circuit 15, the low-frequency 2 × 2 quantized output is d (2 × 2), the low-frequency 4 × 4 quantized output is d (4 × 4), The quantized output of 8 × 8 is d (8 ×
8). Further, the layering circuit 50 outputs four quantized outputs as the quantized output q (2 × 2) of the layer 2 × 2,
16 quantized outputs are output as the quantized output q (4 × 4) of the layer 4 × 4, and the quantized output q (8 × 8) of the layer 8 × 8 is output.
As 8), 64 quantized outputs are output.

In FIG. 10, the quantized outputs d (2 × 2), d (4 × 4) and d (8 × 8) from the quantizer 15 are subtractors 55, 55 and 56 of the hierarchical circuit 50, respectively. Give to. The hierarchization circuit 50 has four low-frequency 2 × 2 quantized outputs d (2 × 2) as the quantized output q (2 × 2) of the layer 2 × 2, that is, the DC coefficient and the three ACs. The quantized output for the coefficient is output as it is. Subtractor 55 quantized output d (4 × 4)
Then, the quantized output q (2 × 2) is subtracted from to obtain the quantized output q (4 × 4) of the layer 4 × 4. This gives a hierarchy of 4x
In Layer 4, as shown in FIG.
Twelve quantized outputs, excluding the four quantized outputs that are coded at, have coefficients.

The quantized output q (4 × 4) of the layer 4 × 4 is also given to the subtractor 56. Subtractor 56 outputs 8 × 8 quantized output d
The quantized output q (4 × 4) is subtracted from (8 × 8) to obtain the quantized output q (8 × 8) of the layer 8 × 8. That is,
As shown in FIG. 12C, 48 in the high frequency range in the hierarchy 8 × 8.
The (= 64-16) quantized outputs have coefficients, and the 16 low-frequency coefficients are 0.

The variable-length coding circuit 51 reads the quantized output of each layer for each layer in the order of the numbers shown in FIG. 11, that is, in the zigzag scan order from the low band to the high band in the horizontal and vertical directions, and reads each quantized output. Variable length coding is performed for each layer and output. For example, for the layer 2 × 2, the variable-length coding circuit 51 uses the four quantized coefficients of the quantized output q (2 × 2) as shown in FIG.
Are read and encoded in the order of numbers. Similarly, the variable-length coding circuit 51 has a quantized output q (4 × 4) of 1 in the layer 4 × 4.
The six outputs are read and coded in the zigzag scan order shown by the numbers in FIG. 11B, and the quantized output q
The 64 (8 × 8) outputs are read out and coded in the order of the numbers shown in FIG. The variable length coding circuit 51 reduces redundancy by entropy coding such as Huffman coding and run length coding.

The run-length encoding reduces the redundancy by converting the coefficients read in the zigzag scan order into the continuous number of the same code. Huffman coding is
For example, the number of consecutive 0s (hereinafter, referred to as zero run), which is the coefficient having the highest appearance frequency, and a non-zero coefficient that appears next to 0 are paired, and a code is assigned to the data of this group according to the appearance frequency. To allocate. That is, in Huffman coding, a Huffman code table is used according to the frequency of appearance of data of a set of zero-run and non-zero coefficients, and the higher the frequency of occurrence, the shorter the code amount is converted. Therefore, in Huffman coding, the larger the zero run, the smaller the number of code words and the more efficient coding is performed.

The coding control circuit 53 obtains the code amount of the coded output from the variable length coding circuit 51 for each layer. The coding control circuit 53 accumulates the generated code amount for each layer, and determines the quantization width of each layer in consideration of the set code amount and the generated code amount assigned to each layer. In this way, the code amount is controlled for each layer.

FIG. 13 is a block diagram showing a decoding device for decoding a coded output that is hierarchically coded.

The encoded output input through the code buffer memory circuit 32 is given to the variable length decoding circuit 60. The variable length decoding circuit 60 performs variable length decoding on the encoded output for each layer, and the variable length decoding output is the inverse layering circuit 61 in the original matrix scan state.
Give to. The inverse layering circuit 61 inversely layers the variable length decoded output. FIG. 14 is a block diagram showing a specific configuration of the reverse hierarchy circuit 61.

The variable length decoding outputs r (2 × 2), r (4 × 4), r (8 × 8) from the variable length decoding circuit 60 for each layer are the adders 65 of the inverse layering circuit 61, respectively. Give to 65, 66. The inverse layering circuit 61 outputs the variable length decoding output r (2 × 2) to the layer 2 × 2.
The variable length decoded output s (2 × 2) is output as it is. As a result, the quantized output q of the layer 2 × 2 on the encoding side
A variable length decoded output s (2 × 2) corresponding to (2 × 2) is obtained.

The variable length decoded output s (2 × 2) is also given to the adder 65. The adder 65 outputs variable-length decoded output r of hierarchy 4 × 4
(4 × 4) and variable length decoding output s (2 × 2) of layer 2 × 2
Is added to obtain a variable-length decoded output s (4 × 4) of the layer 4 × 4 corresponding to the quantized output q (4 × 4) of the encoding side layer (4 × 4). This variable length decoded output s (4
X4) is also given to the adder 66. The variable length decoding output s (4 × 4) variable length decoding output of the layer 4 × 4 is added by the adder 66 to obtain the layer 8 × 8 corresponding to the variable length coding b (8 × 8) on the transmission side. Obtain the variable length decoded output s (8 × 8).
Depending on the transmitted layer and the layer to be displayed, variable length decoding outputs s (2 × 2), s (4 ×
4) or s (8 × 8) is given to the inverse quantization circuit 34. The dequantized color 34 dequantizes the variable length decoded output and supplies it to the inverse DCT circuit 63.

The inverse DCT circuit 63 inverse DCT-processes the input inverse quantized output to restore the original data and supplies it to the terminal a of the switch 36. The inverse DCT circuit 63 processes the high-frequency AC component having no valid data as 0 when performing the inverse DCT processing on the dequantized output of the hierarchy 2 × 2 or the hierarchy 4 × 4. Note that the inverse DCT circuit 63 performs DCT processing based on the size of the screen corresponding to each layer when the input encoded output is used for small screen display. Further, in this case, the predictive decoding circuit 62 performs predictive decoding according to the screen size to be displayed.

By the way, as described above, the variable length coding circuit 51 reads the quantized output from the hierarchization circuit 50 in zigzag scan order and performs Huffman coding on the data of the set of zero run and non-zero coefficient. . That is, hierarchy 2 × 2
Quantized output q given to the variable length coding circuit 51 at
(2 × 2) is, as can be seen from FIGS. 11 and 12,
They are {x}, {x}, {x}, and {x}. In addition, x indicates a coefficient that is not 0, and {} indicates a set of zero run and non-zero coefficient in Huffman coding.

Similarly, in the layer 4 × 4, the quantized output q (4 × 4) given to the variable length coding circuit 51 is 0,
0, 0, ×, 0, ×, ×, ×, ×, ×, ×, ×, ×,
X, x, x. The set in Huffman coding is {(0x3), x}, {0, x}, {x},
{X}, {x}, {x}, {x}, {x}, {x},
It becomes {x}, {x}, {x}, {x}. In addition, (0x
n) indicates that n 0s are continuous. Since four quantized outputs in the low frequency band are transmitted in the layer 2 × 2, four quantized outputs in the layer 2 × 2 are predicted to be 0 in the layer 4 × 4. However, 0s are not continuous due to zigzag scanning and reading, and 13 sets of data must be encoded even in the layer 4 × 4.

In the layer 8 × 8, the quantized output q (8 × 8) given to the variable length coding circuit 51 is 0, 0,
0,0,0,0,0,0,0,0, x, 0,0,0,
×, ×, ×, 0, 0, ×, ×, ×, ×, ×, 0, ×,
×, ... In terms of Huffman coding,
{(0x10), x}, {(0x3), x}, {x},
{X}, {(0x2), x}, {x}, {x},
{X}, {x}, {0, x}, {x}, {x}, ... Even in this case, although the 16 quantized outputs already transmitted in the upper layer 4 × 4 are predicted to be 0, 0s are discontinuously input by the zigzag scan, so that the number of codewords is increased. However, there was a problem that the coding efficiency was low.

[0038]

As described above, in the above-described conventional coding apparatus, by predicting the quantized output of the lower layer by using the quantized output of the upper layer, it is possible to lower the quantized output of each layer other than the uppermost layer. Although the quantized output of the range is set to 0, there are problems that 0s do not continue due to zigzag scanning, the number of code words is large, and the coding efficiency is low.

It is an object of the present invention to provide an encoding device capable of improving the encoding efficiency by continuously reading out a predicted portion and performing variable length encoding.

[Structure of the Invention]

An encoding apparatus according to the present invention comprises orthogonal transformation means for orthogonally transforming a digital signal and outputting a transformation coefficient composed of a DC component and a plurality of AC components,
The conversion coefficient is hierarchized into a plurality of layers from the uppermost layer corresponding to the low frequency component to the lowermost layer corresponding to the high frequency component according to the frequency, and the lower layer side of the lower layer output uses the upper layer output. And a scanning means for reading out a portion predicted by using the upper layer output of the layer output of a predetermined layer prior to other portions.

[0041]

In the present invention, the layering means performs layering based on the frequency of the transform coefficient of the orthogonal transforming means. The hierarchizing means predicts the lower band of the lower layer output by using the upper layer output. The scanning means reads this predicted part before other parts. As a result, data having a relatively low power is continuously read, and the coding efficiency is improved.

[0042]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an encoding device according to the present invention. In FIG. 1, the same components as those in FIG. 6 are designated by the same reference numerals.

The luminance signal Y and the color difference signals Cr and Cb are input to the multi-processing circuit 11. The multiplex processing circuit 11 multiplexes the input signals in block units of, for example, 8 pixels × 8 horizontal scanning lines, and multiplexes them in macroblock units consisting of two luminance blocks Y and one color difference block Cr, Cb. And outputs it to the subtracter 12. The subtractor 12 receives the data of the previous frame via the switch 14, subtracts the data of the reference frame from the output of the multiplex processing circuit 11 and outputs it to the DCT circuit 13 during the interframe compression processing, and the intraframe compression processing is performed. Sometimes the output of the multi-processing circuit 11 is used as it is for the DCT circuit.
It is designed to output to 13.

The DCT circuit 13 subjects the output of the subtractor 12 to the 8 × 8 two-dimensional DCT processing and gives it to the quantization circuit 15. The quantization circuit 15 quantizes the DCT transform coefficient and outputs it to the hierarchical circuit 50. The hierarchization circuit 50 has the same configuration as that of FIG. 10, and hierarchizes the quantized output from the quantization circuit 15. For example, the hierarchization circuit 50 hierarchizes into three hierarchies of hierarchy 2 × 2, hierarchy 4 × 4, and hierarchy 8 × 8. The layering circuit 50 outputs the output d (2 × 2) of the layer 2 × 2 quantization circuit 15 as it is as a layer 2 × 2 quantization output q (2 × 2). Hierarchical circuit 50
Subtracts the quantized output q (2 × 2) from the output d (4 × 4) of the 16 low-frequency quantization circuits 15 to obtain the quantized output q (4 × 4) of the layer 4 × 4. . That is, in the layer 4 × 4, the four low-frequency quantized outputs are predicted to be 0, and the low-frequency 1 is quantized.
2 (= 16-4) quantized outputs have coefficients.

Further, the layering circuit 50 is the quantization circuit 15 for the entire area.
The quantized output q (4 × 4) is subtracted from the output d (8 × 8) to obtain the quantized output q (8 × 8) of the layer 8 × 8. That is, in the hierarchy 8 × 8, 48 (= 64−16) quantized outputs in the high frequency range have coefficients, and 16 low frequency coefficients are predicted to be 0.

The quantized output q (2 ×
2), q (4 × 4) and q (8 × 8) are variable length coding circuits.
Give to 70. The variable length coding circuit 70 includes a coding control circuit 18
The input data is converted into a variable-length code for each layer, and the bit rate is further reduced and output. The variable length code from the variable length coding circuit 70 is also given to the coding control circuit 18. The coding control circuit 18 outputs a control signal for changing the quantization coefficient for each layer to the quantization circuit 15 based on the output of the variable length coding circuit 70. The coding control circuit 18 also limits the number of output bits of the variable length coding circuit 70 to limit the total code amount. In addition, the multi-processing circuit 11, D
A block pulse is supplied to a circuit that performs processing on a block-by-block basis, such as the CT circuit 13 and the quantization circuit 15.

The output of the layering circuit 50 is given to the inverse quantization circuit 21, and the inverse quantization circuit 21 gives the inverse quantization output to the inverse DCT circuit 22. The inverse DCT circuit 22 performs inverse DCT processing on the inverse quantized output to restore the original data before the DCT processing and outputs it to the adder 23. The output of the adder 23 is fed back via the variable delay circuit 24 and the motion correction circuit 25 that delays for one frame period, and the adder 23 adds the difference data of the current frame and the data of the previous frame, The original data (local decoded data) before the difference processing by the subtracter 12 is restored and output to the variable delay circuit 24. The output of the variable delay circuit 24 is also given to the motion detection circuit 26.

The motion detection circuit 26 receives the output of the multi-processing circuit 11 as well, obtains a motion vector by, for example, matching calculation by full search type motion vector detection, and outputs the motion vector to the motion correction circuit 25. A motion determination signal based on whether or not a predetermined threshold is exceeded is output to the logic circuit 27. The motion compensation circuit 25
The output of the variable delay circuit 24 is motion-corrected based on the motion vector, and the motion-corrected previous frame data is output to the subtractor 12 via the switch 14 as a reference image. Logic circuit 27
The switch 14 controls ON / OFF of the switch 14 based on the motion determination signal and the refresh cycle signal indicating the intra-frame compressed frame.

In this embodiment, the variable length coding circuit 70 is used.
Is designed to read the output of the hierarchization circuit 50 in the scan order shown by the numbers in FIG. That is, in the hierarchy 2 × 2, as in FIG. 11A, the reading is performed in the normal zigzag scan order. In tier 4 × 4, first, tier 2 × 2, 4
Read the quantized outputs q (2 × 2), then the hierarchy 2 ×
The 4th output of 2 and the quantized outputs of the 3rd row and 1st column and the 1st row and 3rd column diagonally arranged are read out.
As in (b), reading is performed in the normal zigzag scan order. In the layer 8 × 8, the DC component to the 16th quantized output are read in the normal zigzag scan order of the layer 4 × 4, and the quantized outputs of the 17th and subsequent layers are 16 quantized layers of the layer 4 × 4. Except for the digitized output, zigzag reading is performed from the horizontal and vertical low frequencies to the high frequencies. Figure 26 is the 26th and subsequent figures
This is the same as the normal zigzag scan order of 1 (c).

In the embodiment constructed as described above,
The compression process before the variable length coding process is the same as the conventional one. That is, the luminance signal Y and the color difference signal C are generated by the multiple processing circuit 11.
r and Cb are multiplexed in a block unit of 8 pixels × 8 horizontal scanning lines, and further, in a macro block unit by four blocks of two luminance blocks Y and one color difference block Cr and Cb. Give to the calculator 12. When the intra-frame compressed frame data is created, the switch 14 is turned off, and the output of the multiplex processing circuit 11 is DCT processed by the DCT circuit 13 and given to the quantization circuit 15. The quantization circuit 15 quantizes the DCT transform coefficient and outputs it to the hierarchical circuit 50.

The hierarchization circuit 50 hierarchizes the quantized outputs, and the quantized output q (2 × 2) of the layer 2 × 2, the quantized output q (4 × 4) of the layer 4 × 4, and the quantized output q of the layer 8 × 8. Quantized output q (8
X8) is output. Output b (8 × from the hierarchical circuit 50
8) is given to the variable length coding circuit 70 and the inverse quantization circuit 21.

The inverse quantization output from the inverse quantization circuit 21 is the inverse D
CT circuit 22, adder 23, variable delay circuit 24, motion correction circuit
It is delayed by one frame period via 25 and the switch 14 and fed back to the subtractor 12. When creating the inter-frame compressed frame data, the subtractor 12 subtracts the data of the previous frame from the output of the multi-processing circuit 12. And outputs the difference to the DCT circuit 13. The data rate of the difference data is reduced by the DCT circuit 13 and the quantization circuit 15, and is converted into a variable length code by the variable length coding circuit 70 and output.

The variable length coding circuit 70 receives the quantized output of each layer from the layering circuit 50, and variable length codes the quantized output for each layer. For example, the variable-length coding circuit 70 two-dimensionally Huffman-codes the data of the set of zero-run and non-zero coefficient of the quantized output and outputs it as the coded output. The coding control circuit 18 is provided with the coding output of the variable length coding circuit 70, counts the generated code amount for each layer, and the quantization circuit 15 and the variable length so that the generated code amount falls within the set code amount. The encoding circuit 70 is controlled.

In the present embodiment, the variable length coding circuit 70
Reads the output of the hierarchical circuit 50 in the scan order of FIG. The scan order of the hierarchy 2 × 2 is the same as the conventional one, and the quantized output q (2 × 2) read by the variable length coding circuit 70 is {×},
{X}, {x}, and {x}. Quantized output q (4 × 4) read by the variable length coding circuit 70 in the next layer 4 × 4
Is 0, 0, 0, 0, ×, ×, ×, ×, ×, ×, ×,
X, x, x, x, x. The set in Huffman coding is {(0x4), x}, {x}, {x},
{X}, {x}, {x}, {x}, {x}, {x},
It becomes {x}, {x}, and {x}. That is, the number of codewords coded in the layer 4 × 4 in the variable length coding circuit 70 is 12
It is an individual. Also, in the layer 8 × 8, the variable length coding circuit
The quantized output q (8 × 8) read by 70 is 0, 0, 0,
0,0,0,0,0,0,0,0,0,0,0,0,
0, ×, ×, ×, ×, ×, ×, ×, ×, 0, ×, ×, ...
Is. The set in Huffman encoding is {(0
x16), x}, {x}, {x}, {x}, {x},
{X}, {x}, {x}, {x}, ..., And the number of code words is 48. That is, the number of code words can be reduced as compared with the conventional case.

As described above, in this embodiment, the coefficient predicted to be 0 is first read by using the upper layer output, and then the remaining unpredicted coefficient to be coded is read. , 0 in succession reduces the number of code words to be coded and improves coding efficiency.

FIG. 3 is a block diagram showing the decoding side.
In FIG. 3, the same components as those in FIG. 13 are designated by the same reference numerals.

The code buffer memory circuit 32 is supplied with the coded output of the variable length coding circuit 70 on the coding side. The encoded output from the code buffer memory circuit 32 is given to the variable length decoding circuit 80. The variable length decoding circuit 80 outputs the encoded output to each layer 2 ×
Variable length decoding is performed for each 2, 4 × 4, 8 × 8 and converted into fixed length data r (2 × 2), r (4 × 4), r (8 × 8). The variable length decoding circuit 80 uses fixed length data r (2 × 2), r
(4 × 4) and r (8 × 8) are output in the scan order shown in FIG. The output of the variable length decoding circuit 80 is given to the de-hierarchization circuit 61, and the de-hierarchization circuit 61 de-hierarchizes the fixed length data and gives it to the de-quantization circuit 34, the header signal detection circuit 37 and the motion vector extraction circuit 40.

The inverse layering circuit 61 outputs the output r (2 × 2) of the variable length decoding circuit 80 as it is as an inverse quantization output s (2 × 2). The inverse layering circuit 61 adds the output r (4 × 4) of the variable length decoding circuit 80 and the decoding output r (2 × 2) of the layer 2 × 2 to obtain the variable length decoding output s (of the layer 4 × 4. Output as 4 × 4). Further, the inverse layering circuit 61 outputs the decoded output r (8
X8) and the variable length decoded output s (4 × 4) of the layer 4 × 4 are added and output as the variable length decoded output s (8 × 8) of the layer 8 × 8.

The inverse quantization circuit 34 inversely quantizes the variable length decoded output and supplies the inverse quantized output to the inverse DCT circuit 63. Reverse DC
The T circuit 63 performs inverse DCT processing on the inverse quantized output for each layer to restore the original code and outputs it to the terminal a of the switch 36 and the adder 38. A header signal extraction circuit 37 for extracting a header signal, a motion vector extraction circuit 40 for extracting a motion vector, a frame memory 41 for delaying the output signal for one frame period, an output of the inverse DCT circuit 63 and an output of the predictive decoding circuit 62 are added. The configurations of the adder 38 for decoding the inter-frame compressed frame data and the switch 36 for switching and outputting the decoded data of the intra-frame compressed data and the decoded data of the inter-frame compressed data are the same as the conventional one. The predictive decoding circuit 62 performs motion compensation on the output of the frame memory 41 with the motion vector from the motion vector extraction circuit 40 and adds it to the adder 38.
Give to.

In the embodiment constructed as described above,
The variable length decoding circuit 80 outputs the variable length decoding output in the matrix scan order shown in FIG. As a result, the circuits after the inverse layering circuit 61 can be decoded by the same decoding operation as the conventional one.

FIG. 4 is an explanatory diagram showing another scan order applicable to this embodiment.

The scan order of hierarchy 2 × 2 and hierarchy 4 × 4 is the same as in FIG. Tier 4 × 4 in Tier 8 × 8
2C is different from FIG. 2C in that the 16 scan orders of are the same as the scan order of the hierarchy 4 × 4 in FIG. 2B.

FIG. 5 is a block diagram showing a hierarchical circuit according to another embodiment of the present invention. The embodiment of FIG. 5 employs a layering circuit 91 including a quantizing circuit and an inverse quantizing circuit.
15 is different from the embodiment of FIG. 1 in that the inverse quantization circuit 21 is omitted.

Of the DCT transform coefficients from the DCT circuit 13, four transform coefficient outputs of hierarchy 2 × 2 are set as d (2 × 2),
The 16 transform coefficient outputs of the hierarchy 4 × 4 are defined as d (4 × 4), and the 64 transform coefficient outputs of the hierarchy 8 × 8 are defined as d (8 × 8).
And These conversion coefficient outputs d (2 × 2), d (4
X4) and d (8x8) are quantizers 95 of the layering circuit 91, respectively.
And the subtracters 97 and 101. The quantizer 95 uses the transform coefficient d
(2 × 2) is quantized and output.

The layering circuit 91 also outputs an inverse quantized output, and the inverse quantizer 96 outputs a quantized output q (2 ×).
2) is inversely quantized and output. This dequantized output b (2
X2) is given to the subtractor 97 and the adder 100.

In the next layer 4 × 4, layer 2 is originally
Predict the four transform coefficients coded with × 2 as 0,
Quantization may be performed on the remaining 12 transform coefficients.
However, in doing so, when decoding at the level of hierarchy 4 × 4, the inverse quantized output for hierarchy 2 × 2 is used for the encoded output based on the four transform coefficients in the low frequency band. The quantization error in the hierarchy appears in the decoded output. Therefore, with respect to the four low-frequency transform coefficients of layer 4 × 4, the actual transform coefficient is predicted using the dequantized output of layer 2 × 2. That is, for the four low-frequency transform coefficients, the dequantized output of layer 2 × 2 is used to quantize the difference between the actual transform coefficient and the predicted value. That is, the dequantized output b (2 × 2) of the dequantizer 96 is given to the subtractor 97 and subtracted from the transform coefficient output d (4 × 4). Thus, the quantizer 98 is supplied with the predicted transform coefficients for the four low-frequency bands.

The quantizer 98 quantizes the input transform coefficient and outputs the quantized output q (4 × 4) to the variable length coding circuit 70 (see FIG. 1) and the inverse quantizer 99. The inverse quantizer 99 multiplies the quantized output by the quantized coefficient and outputs it to the adder 100. The four low-frequency components of the dequantized output from the dequantizer 99 are the actual transform coefficient and the dequantized output b (2
X2) is the inverse quantized output of the quantized output, so that the adder 100 returns the original transform coefficient to the output of the inverse quantizer 99 and the inverse quantized output b (2 × 2). ) And are added. Thus, the dequantized output b (4 × 4) of the layer 4 × 4
Is obtained.

Also in the next layer 8 × 8, in order to reduce the decoding error due to the quantization error, the subtractor 101 uses the dequantized output b (4 × 4) as the prediction value and transforms the layer 8 × 8. The difference between the coefficient output d (8 × 8) and the predicted value is calculated. The quantizer 102 quantizes the output of the adder 101 to obtain a quantized output q
Variable-length coding circuit 52 and inverse quantizer for obtaining (8 × 8)
Output to 103. The inverse quantizer 103 has a quantized output q (8 ×
8) is multiplied by a coefficient to give an inverse quantized output to the adder 104, and the adder 104 adds the inverse quantized output to the inverse quantized output b.
(4 × 4) is added and corrected, and the inverse quantized output b (8 × 8) of the layer 8 × 8 is output to the inverse DCT circuit 22 (FIG. 1).

Also in the embodiment configured as described above,
The low frequency DCT transform coefficient is data having a power of 0 or close to 0. Therefore, it is possible to improve the coding efficiency by performing variable length coding in the scan order of FIG. 2 or 4.

[0070]

As described above, according to the present invention, it is possible to improve the coding efficiency by continuously reading the predicted portion and performing the variable length coding.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an encoding device according to the present invention.

FIG. 2 is an explanatory diagram for explaining a read order (scan order) of the variable-length coding circuit in FIG.

FIG. 3 is a block diagram showing a decoding device.

FIG. 4 is an explanatory diagram for explaining another scan order.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional encoding device.

7 is a block diagram showing the decoding device of FIG.

FIG. 8 is an explanatory diagram for explaining layering.

FIG. 9 is a block diagram showing a conventional encoding device.

10 is a block diagram showing a specific configuration of the hierarchization circuit in FIG.

FIG. 11 is an explanatory diagram for explaining zigzag scanning.

FIG. 12 is an explanatory diagram for explaining a quantized output of each layer.

FIG. 13 is a block diagram showing the decoding device of FIG. 9.

FIG. 14 is a block diagram showing a specific configuration of the inverse hierarchy circuit in FIG.

[Explanation of symbols]

 50 ... Hierarchical circuit, 70 ... Variable length coding circuit

Claims (1)

[Claims] 1. An orthogonal transform means for orthogonally transforming a digital signal to output a transform coefficient composed of a direct current component and a plurality of alternating current components, and the transform coefficient from the uppermost layer corresponding to a low frequency component in accordance with its frequency. Hierarchical means for hierarchizing into a plurality of layers up to the lowest layer corresponding to the region component, and for the low frequency side of the lower layer output, a layering means for predicting using the upper layer output, and a layer output of the upper layer of the predetermined layer output An encoding device, comprising: a scanning unit that reads out a portion predicted using hierarchical output before other portions.