KR100297465B1 - Multiple writes per a single erase for a nonvolatile memory - Google Patents

Abstract

A method of performing a plurality of writes before deleting the memory cell 500 is described. M bits are stored in a first group of levels of the memory cells. Subsequent M replacement bits are stored at the level of the second group of memory cells 550 without erasing the memory cells. Another memory cell writing method includes storing m bits in a first group of levels of memory cells. The group indicator is adjusted to identify the level of a subsequent group of memory cells. Next, m replacement bits are stored following the memory cell's level without erasing the memory cell. The step of adjusting the group indicator and the subsequent step of storing the m replacement bits are repeated. A method of delaying the deletion of a memory cell is also described. The group indicator is adjusted to identify one group of 2 ^m adjacent levels of the memory cell that can be used to store m bit values. The memory cell read method includes providing a group indicator. The group indicator identifies one group of 2 ^m adjacent levels of the memory cell. Next, the m bit value is read by detecting the group of 2 ^m adjacent levels identified by the group indicator.

Description

Multiple writes per erase of non-volatile memory {MULTIPLE WRITES PER A SINGLE ERASE FOR A NONVOLATILE MEMORY}

In general, semiconductor memory devices are composed of a number of individual cells for storing data. In a conventional binary memory device, each cell can store one of two states to represent one bit of data. Each memory cell can also store more than one bit of data. Such memory devices are referred to as multi-level memory devices or multi-bit memory devices. Multilevel memory devices increase storage capacity and density beyond conventional binary devices. For example, a memory device capable of storing two bits of data per unit cell has a capacity capable of storing twice the data that can be stored in the same number of conventional binary memory devices.

The programming operation of a conventional binary memory device consists of storing or programming one level or state of one of two levels or states in a memory cell to represent all possible values for one bit of data. For example, a conventional memory cell stores a first voltage or threshold level to represent a first state and, when accessed during a write operation, and stores a second voltage or threshold level to represent the second state. However, to represent more than one bit of data in a multilevel memory device, typically one of n states is stored. The ability to store one bit requires the ability to store at least two levels as in the conventional binary memory cell, but the term "multilevel" as used herein refers to two or more levels or states (ie, one or more levels). It is intended to refer to a cell capable of storing one level or state of one of the binary digits, and a "binary" only refers to a cell capable of storing one of two levels (one binary digit). For example, to store two bits in each multi-level memory cell, each cell must be able to store one of at least four levels. A multi-level cell capable of storing n bits must be able to support 2 ⁿ threshold levels since each bit can have one of two levels.

One type of multilevel memory cell is a flash multilevel memory cell. Generally, flash memory cells include floating gate field effect transistors. Each floating gate transistor has a select gate, a floating gate, a source, and a drain. Information is stored in the flash cell by varying the amount of charge stored on the floating gate. When the information is stored, the threshold voltage V _t of the floating gate field effect transistor may vary. A conventional conventional binary flash memory cell can be in one of two possible states, a "programming state" or a "erasing state." In theory, the flash cell has a separate state of each electron applied to the floating gate. In practice, however, conventional flash cells have a limited number of states due to various constraints, including inconsistencies of the flash cell structure, charge loss over time, and limitations in sensing charge stored on the floating gate.

The actual charge stored on the programmed cell can vary from one programmed cell to another programmed cell or from one erased cell to another erased cell. In order to accommodate this factor, by which the binary flash cell is V _t is stored in a "1" is within a first range of values, and V _t is to be storing a "0" is within a second range of values Judging. The first range and the second range are separate and may be separated by “separation range”. In other words, if the threshold voltage V _t is programmed to a value within a set of values, the cell state is "1". If the threshold voltage V _t is programmed to a value within another set of values, the cell state is " 0 ". The difference between these sets of values is called the separation range.

When a flash cell is read, the current conducted by this flash cell is compared with the current conducted by the reference flash cell with a threshold voltage V _t set to a predetermined voltage within the isolation range. When a flash cell is selected for reading, a bias voltage is applied to the selection gate of the field effect transistor. At the same time, the same bias voltage is applied to the select gate of the reference cell. If the flash cell is "programmed," excess electrons are collected on the floating gate, and the threshold voltage V _t of the flash cell is increased, so that the selected flash cell has a drain current less than that of the reference flash cell. Evangelize The programming state of the conventional binary flash cell is generally associated with logic zero. If the conventional flash cell is "erased," the floating gate will have fewer electrons, and the flash cell conducts more drain-source current than the reference cell. The erase state of the conventional binary flash cell is typically associated with logic one.

A multi-level flash cell can store one of two or more levels. For example, a multi-level flash cell capable of storing two bits may be placed in one of four states. This means that one state is uniquely assigned to one of four possible combinations of two bits, one of "00", "01", "10" and "11". 2 to distinguish the different states of ⁿ it requires 2 ⁿ -1 of reference. Thus, for the four states, there must be three reference voltages and three separation ranges. For comparison, the conventional binary flash cell typically uses one reference voltage to distinguish two states.

These multi-level flash cells are read by comparing each of the 2 ⁿ -1 voltage references with a voltage determined by the drain-source current of the memory cell. At this time, a decoding logic circuit is used to convert the outputs of the 2 ⁿ -1 comparators into n bits.

Generally, flash memory devices include an array of flash memory cells. In general, these arrays are divided into blocks or separated again. Conventional flash memory can be programmed on a cell-by-cell basis, but flash memory can only be erased into several cell blocks.

One disadvantage of the conventional recording technique is that once data is written to a block, the data in this block cannot be modified without first deleting the block. In other words, in the conventional recording technique, only one write cycle is allowed per erase cycle.

One application of flash memory is in solid state "disks". To mimic a conventional computer disk storage device, a solid state disk uses a nonvolatile memory such as flash memory. In general, disk sectors are physically or logically mapped onto a block of flash memory cells. Since only one write cycle is possible for each erase cycle in a conventional storage system, in order to be able to reuse the cell for storing data, a method of "deleting" previously written to the cell is needed. . In general, valid data in a block is copied into update data at another block position. At this time, for deletion, the previous block position is displayed. The deletion process deletes the entire block and makes the block available again for storage.

One disadvantage of the conventional write once method for each deletion of the cell is the required energy consumption. Thus, in applications where stored data must be frequently modified, significant amounts of energy are consumed when moving valid data to a new location and when information is deleted from previously stored blocks.

Another disadvantage that exists when performing an erase step to reprogram the cell is that the delete process generally requires significantly longer execution time than the programming process.

Another disadvantage of erasing every programming cycle is the reliability error that occurs periodically. The flash memory cell deteriorates with each program / erase cycle.

This application is part of a continuation of US patent application Ser. No. 08 / 537,132, filed on September 29, 1995, in Hasbun et al.

The present invention relates to the field of memory circuits. In particular, the present invention relates to performing a plurality of write operations without an erase operation in an electrically programmable nonvolatile memory.

1 illustrates one embodiment of an erase state for a block of a multilevel memory cell.

2 illustrates programming of levels within a block of a multilevel memory cell.

3 illustrates different levels of programming within a block of multilevel memory cells.

4 illustrates programming of levels of a multilevel memory cell using a "backfill" technique.

5 shows four levels of multi-level memory cells.

Figure 6 illustrates one embodiment of a multilevel memory cell having n levels categorized into k groups of j levels.

In view of the limitations of existing systems and methods, one of the objectives of the present invention is to provide a method of performing m-bit multiple writes for a non-volatile memory cell without erasing. The method includes storing m bits in a first group of levels of the memory cells, and storing m replacement bits in a second group of levels of the memory cells without deleting the memory cells.

Another write method includes storing m bits in a first group of levels of the memory cells. The group indicator is adjusted to identify a subsequent group of levels of the memory cell. Without deleting the memory cell, the subsequent m replacement bits are stored in the subsequent group of levels. Adjusting the group indicator and storing the subsequent m replacement bits are repeated.

Another object is to provide a method of reading a memory cell capable of storing up to k m replacement bit values. The method includes providing a group indicator to identify a group of 2 ^m adjacent levels of the memory cell, and sensing the group of the identified level to read an m bit value.

Also provided is a method of delaying an erase operation for a nonvolatile memory cell. The erase operation is delayed by adjusting a group indicator, where the group indicator identifies 2 ^m adjacent levels of the memory cell to store an m bit value.

Backfill techniques are introduced as a method of ensuring constant programming time for a given group of levels of memory cells.

Other objects, features and advantages will be apparent from the accompanying drawings and from the detailed description below.

The invention has been described by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference characters indicate similar elements.

By using a multilevel cell as a single bit storage device, a single bit can be written multiple times before erasing is performed. Consider an n-level multilevel flash memory cell. The flash memory cell may have up to n distinct levels. One level is reserved for the deletion state. The remaining n -1 levels are available for programming.

During the erase operation, charge is removed from the floating gate of the flash memory cell. Charge may be placed on the floating gate of the flash memory cell during a programming operation. The programming or erasing state should be distinguished from the program or deleting operation. The programming state of a conventional binary flash cell (i.e., charge on a floating gate) is generally associated with logic zero, and the erase state (i.e., charge removed from a floating gate) is typically associated with logic 1 Related. The erase operation is a process of depletion of charge from the floating gate. During the erase operation, charge above the given threshold level on the floating gate is consumed to ensure that the charge level on the floating gate is below the threshold level after the erase operation. However, a programming operation may or may not charge on the floating gate depending on the value to be stored. Conventional binary flash cells can always be programmed to zero (i.e. they can have a charge placed on the floating gate). However, after being programmed to zero, an erase operation must be performed before the conventional binary cell can again store one.

In the multilevel cell, a single multilevel value may not be stored by selecting a charge level, but a single bit may be stored at a given level. In other words, a plurality of alternate writes to a multilevel memory cell may include storing (or writing) a first bit at a first level of an n-level multilevel memory cell, and subsequently to a second level of the multilevel memory cell. This is accomplished by performing the step of storing the second bit. The first value is overwritten by storing the second bit at the second level. Thus, in essence, multiple writes can be made to the multi-level cell before an erase operation is needed.

In order to determine the value stored in a given cell, one must know the last recorded level. This means that a tracking mechanism is needed to keep track of the current level (or reference voltage suitable for use). This mechanism is equipped with a state machine, a memory, or a counter. The degree to which tracking is performed (ie, cell level, block, block group, or device level) is called tracking resolution. In one embodiment, the tracking mechanism is implemented on a cell basis. However, tracking on a cell basis may be inefficient due to practical considerations when implementing the tracking mechanism. In addition, tracking can be proved to be most efficient at the block level or even at the device level since all flash cells in the block must be deleted in order to delete one flash cell in the block anyway. Therefore, other embodiments use block level tracking resolution, multiple cell level tracking resolutions, or device level tracking resolutions. For example, multi-cell tracking may be used in solid state disk applications where disk sectors are logically mapped to multiple cells that are physically arranged as a subset of cells in a cell block.

1 to 3 illustrate the results of performing a plurality of recordings for four four level cells. 1 illustrates one group of deleted multi-level cells 110, 120, 130 and 140. In Fig. 2, the recording of the sequence " 0101 " into the cell is illustrated. In FIG. 3 a subsequent record of " 0110 " is illustrated. (The filled circles represent the charge on the floating gate, and placing the charge on the floating gate is associated with logic "0.") Although the separation range is not illustrated in these figures, see FIG. 1 again. The reference voltages described above correspond to the separation lines 160, 162 and 164 and are used to determine the values stored in the cells 110, 120, 130 and 140. The first level 150 indicates a deletion state. An empty circle (e.g., 170) indicates that the threshold isolation level (1,2) is exceeded because the floating gate does not contain sufficient charge. When sensing the cell 140 and comparing the result with the reference voltage corresponding to the dividing line 160, it is determined that the cell 140 should be deleted (ie, having to store "1" of level 1), This is because there is not enough charge to exceed the threshold level set by the separation line 160. Indeed, as long as the charge level does not exceed the threshold level of separation line 160, the charge may be present at level 1 (ie, a filled circle or a partially filled circle may appear).

2 illustrates storing "0101" (viewed from left to right, starting from cell 210) in a previously deleted cell. A "filled circle" or dot of a given level is intended to indicate that the floating gate of the cell has been charged to that level. For example, a dot 270 at level 2 is considered to store "0" at the opposite level 2 or "1" at level 2 when the cell is erased when a reference voltage corresponding to 260 is used. In other words, it means that the floating gate of the cell 210 has a sufficient charge. In other words, the dot 270 implies that any voltage measured from the cell 210 is higher than the threshold level of the reference voltage corresponding to the dividing line 260.

In order to store the zero at level 2 represented by dot 270, the amount of charge on the floating gate will exceed the threshold level set for level one. Thus, the dot 28 (corresponding to the empty circle 180 of FIG. 1) becomes a filled circle if the circle is previously empty as illustrated in FIG. 1.

3 illustrates storing "0110" in a cell of the group previously storing "0101". Note that charge is continuously placed in the floating gate of the cell 310 and that charge is not yet placed in the floating gate of the cell 320. However, sufficient charge must lie in the floating gate of cell 340 through level 1 350 and level 2 352. Since cell 340 did not previously have any significant amount of charge on the floating gate, more time and energy is needed at this point to add the appropriate amount of charge. Since level 3 354 is being used, the level indicator must be set so that an appropriate split line (ie, reference voltage) can now be used.

All reference voltages are used to determine the multi bit value stored in the multi level cell used in the conventional method described above. In this case, however, the current level indicated by the level indicator should specify which of the reference levels should be used.

Level 3 is not used, so this level 3 can be used for recording. Thus, in the case of n-level multi-level cells, at most n-1 writes can be performed before the erase operation. The multi-level memory cell may be written one or more times before performing an erase operation as follows: First, a first bit is stored in a first level of an n-level multi-level memory cell. In order to find a reference voltage suitable for use in reading the cell, a level indicator must be set to indicate this first level. When a second replacement bit is to be written to the cell, the second bit is stored at the second level of the n level memory cell. At this point, the level indicator is updated to indicate that the second level of the cell is now in use.

The multilevel memory cell can be pseudo erased and made available for storing a value by increasing the level indicator, whereby the level indicator can indicate the next level of the multilevel cell to be written. This procedure can be performed up to n-1 levels before the actual deletion is needed.

Consider a solid state disk as one application for multiple writes before performing the erase of the multilevel memory cell. Flash cells are programmed once at a time, but in general, flash cells can only be block erased at one time. Conventional binary cells can be individually programmed to logic 0 at any time, but once the cell is programmed to logic 0, the cell must be deleted to store logic 1. If a bit associated with a binary cell in a block thus needs to be changed from 0 to 1, the entire block must be deleted before the cell can store 1 again.

In one embodiment, "valid" information and update information are copied to the free area of the flash memory. The previous block position is displayed for deletion, so that the storage space is deleted and freed for future storage. Thus, the erasing procedure that allows to improve the performance of the solid state disk is delayed.

The erase operation is intended to require more time and more energy than the programming operation. Reducing the execution time of either operation can improve the performance of the system. If a multi-level cell is used instead of a conventional binary cell, the pseudo erase operation may be achieved by simply increasing the level indicator for that block of cells. Although a complete erase is not performed, the technique can be used to delay the erase operation until the block is written n-1 times for a block of n level multilevel cells. This technology has the potential to save energy and erase time. Since no actual erase is done, the energy supplied during normal erase operations is conserved except for the amount needed to increase the level indicator for a block of memory cells. The only time needed is the time required to increase the level indicator for the block. Thus, the use of this technique can save energy and time, and thus improve the performance of solid state disks.

An additional technique that can improve system performance is to "backfill". This technique recognizes that the operation of programming a bit to "0" at the qth level of a cell requires a different time depending on whether the previously stored bit is "1" or "0". In other words, the amount of time required to program the cell to a particular level is directly related to the amount of charge already placed on the floating gate.

4 illustrates an alternative to FIG. 3 using a backfill technique. It should be noted that when writing to level 3 in FIG. 3, due to the fact that three "1s" are written to the cell, cell 320 still has substantially no charge on the floating gate. If "0" is to be written at level 4, then due to the amount of charge already placed on the floating gate of cell 310, more time is needed than the time required to program cell 310 to "0". ) Is required to program "0". As such, the programming operation is sensitive to values previously stored in the multilevel cell. However, FIG. 4 illustrates the same value stored at level 3 that was stored in FIG. 3. Before proceeding to the next level, there is a difference that the preceding first and second levels are now programmed to "0". Note that 370 in FIG. 3 is an empty circle and 470 in FIG. 4 is a filled circle, but the value stored in level 3 is the same in both figures.

The backfill technique helps to ensure that at some level the operation of programming the cell to "0" requires approximately the same amount of time. This technique has the disadvantage of requiring time and energy to add charge to the floating gate each time the level indicator is increased. However, an advantage of using this technique is that the programming time is constant at subsequent higher levels that are substantially independent of the current value stored in the multilevel cell. Referring back to FIG. 1, in line with the backfill technique, the floating gates of the four cells may be charged to (but do not exceed) this threshold level 160. Thus, 170 and 180 and the other circles are filled to indicate the presence of charge. However, level 1 still represents the erase state, and programming of level 2 now requires a shorter time due to the amount of charge already placed on the floating gate.

The examples presented above represent performing a plurality of alternate writes to a memory without having to perform an erase operation between write operations. In particular, up to n-1 single-bit writes can be performed on multilevel cells having at least n levels without erasing.

Fig. 5 is useful for deriving a general formula relating to the number of records that can be performed without erasure for multi-level cells having n levels. 5 illustrates a multi-level cell 500 having four levels 501, 502, 503, 504. 2 ^m levels are required to store m bits. Thus, for example, two levels are required to store a single bit. To store the first single bit, charge is placed at level 504 or levels 503 and 504, and thus the reference 530 can determine whether 1 or 0 is stored after the first write operation. Each criterion may determine one of two states from two related levels. The reference 530 is associated with the levels 503 and 504 indicated by 570. Reference 520 is associated with levels 502 and 503 indicated by 560. The reference 510 is associated with the levels 501 and 502 indicated by 550. As such, 540, 550, and 560 represent several groups of levels associated with the replacement record, such that 550 is an alternative record group for 560 and 540 is an alternative record group for 550.

Each write operation requires 2 ^m levels per bit, but subsequent write operations use the highest level of the previously recorded bit to indicate the lowest level of the bit that is subsequently written. Thus, at least one of the levels required for subsequent write operations effectively overlaps one of the levels required for a previous write operation, so only 2 ^m-1 additional levels are required for writing the subsequent set of bits. This is necessary. 5, this is evidenced by the intersection between two adjacent recording groups. Thus, each recording group 560, 550 requires two levels, but level 503 is used by both recording groups, so only one additional level is needed to support two recording groups. . Thus, the number of additional levels required to represent m bits for a given subsequent write operation is 2 ^m −1.

6 illustrates a multi level cell 600 having n levels. These n levels are classified into k groups of j levels. In order for each group's level to be able to store m bit values, j ≧ 2 ^m . Each group 610 of j levels is also called a recording group, and can be identified by a group indicator.

Assuming efficient use of cell memory levels to allow each group to store one m bit value without wasting any level, then j = 2 ^m . However, the number of bits that can be stored per recording group is int (log ₂ (j)). The result of the function int (x) is the integer component of x. Thus, for example, int (5/3) = 1. The result of the function log ₂ (x) is the logarithm of x (base 2), so if x = 2 ^a then log ₂ (x) = a. In one embodiment j is an integer square of two, so j = 2 ^m .

A method of performing a plurality of recordings without erasing may be generalized to a method of performing k recordings, where the m bit value is recorded for each recording. In the general case, there are k groups (i.e. k recording groups) at levels available for recording. Each recording group following the first recording group shares a level with the preceding recording group. The first recording group requires 2 ^m levels. Each subsequent k-1 recording groups require 2 ^m −1 additional values. Accordingly, it is possible to determine the total number n of levels necessary for enabling k recording of m-bit values without performing erasure.

To write up to k m replacement bit values in one memory cell, each subsequent write replaces the m bit values stored by the previous write operation, and the memory cells must have n levels, At this time,

n≥k (2 ^m -1) +1

to be.

The variable k indicates the maximum number of write operations to be performed before the erase operation is needed. Solving for k, we get:

Applying this equation in the case of a single bit (i.e. m = 1) yields k = n-1 which corresponds to the single bit example presented above.

The variable (n, m) may be chosen such that k is not an integer. However, in one embodiment, partial writing is not allowed, so k must be an integer. Given int (x) ≦ x (where x> 0), the variable k can be selected as any integer, so long as the following equation holds:

In one embodiment, at least one of n and m is not an integer. In another embodiment, n and m are integers and are selected such that the following formula is true:

Unlike the case of a single bit, there is no one-to-one correspondence between the voltage reference and the write group when multiple bits are written (i.e., m> 1). In order to determine at least one of the 2 ^m states from each group, 2 ^m -1 criteria are needed. Thus, a given recording group is associated with 2 ^m -1 criteria. (In the case of single bits, and m = 1, ^m 2 - 1 2 = ¹ - a 1 = 1 standard, so there is a one-to-one relationship between the reference record and the group.)

Once an m bit value is written to a given write group, the m replacement bit value can be written to the multilevel cell without writing to the next write group to perform an erase. In other words, the memory cell write method includes writing a first m-bit value to a first write group of the memory cell. A second m replacement bit value is written to the second write group of the memory cell.

Even for the single bit case, a group indicator similar to the level indicator presented above may be used. The group indicator is used to determine which of the k groups is being used to store the m bit value. The group indicator also indicates the number of records already performed without deletion. Without increasing the single level to store the value, the group indicator is adjusted such that the next group of records available for subsequent alternate writing of the m bit value can be determined.

In one embodiment, the group indicator is incremented to identify the next group of records available for subsequent replacement records.

As such, one memory cell write method includes storing m bits in a first group of levels of the memory cell, adjusting a group indicator to identify the next available group, and without deleting the memory cell. Storing the m replacement bits following the second group of levels of memory cells.

Once k write operations have been performed, the memory cell must be physically erased before additional write operations can be performed. The group indicator should be adjusted depending on whether full physical deletion or partial physical deletion is allowed.

In one embodiment, partial physical deletion is possible. In partial physical erase, the charge stored in one write group of the memory cell is removed until no charge remains in this one write group. In such a case, the group indicator should be initialized according to how the plurality of recording groups are deleted. If the current write group is write group i and sufficient charge is removed to erase b write groups, the group indicator should be reduced or initialized to i-b. In other words, partial deletion can be achieved by removing the charge from an n-level memory cell having k write groups so that the write groups kb (where b <k) through k do not store substantially any charge. have.

However, in another embodiment, if only complete physical erase is allowed, all charges are substantially removed from the multilevel memory cell during the physical erase operation. In this case, the group indicator should be initialized after the complete physical erase operation so that the group indicator can indicate the first group of k available groups in the memory cell.

As in the case of the example presented above for the single bit erasure, the memory cell appears to be deleted in terms of m bits when the group indicator is properly adjusted. If the group indicator is adjusted to identify a set of available ^2m adjacent levels of the memory cell, the memory cell appears to be deleted in terms of m bits. However, it is effective to delay the erasure for k recording operations. As such, the memory cell is " deleted " by incrementing the group indicator to the next available set of 2 ^m adjacent levels. However, after k writes, the memory cell must be completely erased before another value can be stored in the memory cell.

A read operation uses the group indicator to determine which set of 2 ^m levels needs to be detected to determine the m bit value stored in the memory cell. 2 each set of ^m level 2 because it requires a ^m -1 of reference, if the group indicator is set which is used in the 2 ^m -1 different criteria to determine the m-bit value stored in the memory cell, Efficiently identify As such, the group indicator is provided to identify 2 ^m adjacent levels of the memory cell. At this time, an m bit value is read from the memory cell by determining the states of the 2 ^m adjacent levels.

The backfill technique presented above for a single bit of memory can be similarly applied to storing multiple bits. In particular, the backfill is achieved by storing a predetermined value in the first write group before storing the m replacement bits in the second write group.

Using n-level multilevel memory cells to perform multiple writes of m-bit values (where m≥1) reduces the total number of sense amplifiers needed to detect the values stored in the memory cells. have. All voltage references within a given recording group are needed to sense the values stored in that recording group. However, under normal operation, all n levels belong to the same recording group so that the n level cells can be used to store log ₂ (n) bits. Thus, the cell must be deleted before a new value can be programmed to the cell. To read the contents of the cell, all n-1 voltage references are needed at the same time. However, if each recording group is composed of 2 ^m levels, only 2 ^m −1 voltage references are needed for each sensing operation. As long as 2 ^m <n, that means less than n-1 sense amplifiers are needed for each sensing operation.

If a programmable sense amplifier is used, the total number of sense amplifiers required to read the memory cell can be reduced from n-1 to approximately 2 ^m −1. In general, a sense amplifier is a comparator that compares the sensed value with a reference voltage. Referring to FIG. 1, three sense amplifiers having corresponding provisional voltages set to 160, 162, and 164 are required to determine values stored in the cells 110, 120, 130, and 140. 6, only a sense amplifier is needed for reading the current write group for a given read operation. To read the next write group, the same 2 ^m -1 sense amplifiers can be used if the reference voltage of each sense amplifier is adjusted to 2 ^m levels. Thus, the reference voltages of all 2 ^m -1 all sense amplifiers can be shifted to correspond to the reference voltages required for reading the m bit values stored in the next write group.

In one embodiment, a programmable 2 ^m -1 sense amplifier is used to read the m bit values stored in the first group of 2 ^m adjacent levels. In order to read the m bit value in which a second group of 2 ^m adjacent levels is stored, a programmable 2 ^m -1 identical sense amplifier is reprogrammed. The reference voltage level programmed for a given sense amplifier is determined from a programmable value. In one embodiment, the programmable value is the group indicator. Thus, each time the group indicator is increased or decreased, the reference voltage of a given sense amplifier is adjusted to 2 ^m levels.

Thus, another method of reading m bit values from a multilevel memory cell is described. A first group of 2 ^m adjacent levels of the memory cell is identified. The first group is sensed using a first set of 2 ^m -1 sense amplifiers. Next, a second group of 2 ^m adjacent levels of the memory cells is identified. The second group is sensed using the same first set of 2 ^m -1 sense amplifiers. In one embodiment, the 2 ^m -1 sense amplifiers are programmed according to the group indicator, wherein each time the group indicator is increased or decreased, the reference voltage (or reference level) of each sense amplifier is 2 ^m. The level is adjusted. As such, in one embodiment, increasing the group indicator increases the reference level of each 2 ^m -1 sense amplifier by 2 ^m levels. Similarly, if the group indicator is reduced, the reference level of each 2 ^m -1 sense amplifier is reduced to 2 ^m levels.

Although flash memories have been used in the examples presented above, these methods can be applied to any memory that allows for the continuous storage of charges during subsequent programming operations and the detection of continuously variable charge amounts (ie, positive or negative charge variations). have. Examples of such memories include non-MLC flash, electrically erasable and programmable read only memory (EEPROM), erasable and programmable read only memory (EPROM), read only memory (ROM). , And the multi-level flash (MLC flash) cells described above.

In the foregoing detailed description, the invention has been described with reference to specific embodiments. Various modifications and variations may be made without departing from the broader spirit and scope of the invention described in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (15)

Storing m bits in a first group of levels of a nonvolatile memory multilevel cell; Storing m replacement bits in a second group of levels of the nonvolatile memory multilevel cell without deleting the nonvolatile memory multilevel cell; And Adjusting a group indicator to identify a second group of levels, where m is an integer greater than or equal to 2, the nonvolatile memory multilevel cell has at least n levels, and n is greater than or equal to 2 A non-volatile memory multilevel cell writing method, wherein n is an integer, and n levels contain k groups, each of which contains j levels of n levels, and k is an integer greater than or equal to two. . The method of claim 1, wherein the nonvolatile memory multilevel cell is a flash memory cell. 2. The method of claim 1, wherein j &gt; 2 ^m . 4. The method of claim 3, wherein j = 2 ^m . The method of claim 1, And a nonvolatile memory multilevel cell writing method. The method of claim 1, wherein the first group and the second group of levels overlap to include at least one level in common. 2. The non-volatile memory multilevel cell of claim 1, further comprising storing a predetermined value in the first group of levels before the step of storing the m replacement bits in a second group of levels. Recording method. Reading a value stored in the group indicator; Identifying one group of adjacent levels of the n-level nonvolatile memory cell based on the value stored in the group indicator; And sensing said one group to read an m bit value, wherein n is greater than or equal to two. 8. The method of claim 7, wherein said nonvolatile memory cell is a flash memory cell. Reading a value stored in the group indicator; Identifying a first group of 2 ^m adjacent levels of memory cells based on the value stored in the group indicator; sensing the first group using a first set of 2 ^m −1 sense amplifiers to read m bit values; Identifying a second group of 2 ^m contiguous levels of memory cells based on values stored in the group indicator; And Sensing the second group using a first set of 2 ^m −1 sense amplifiers equal to the first set of 2 ^m −1 sense amplifiers to read another m bit value, wherein m is 2 A method of reading a memory cell, characterized by being greater than or equal to. 11. The method of claim 10, further comprising setting each reference level of the 2 ^m -1 sense amplifiers according to the group indicator. 12. The method of claim 11, further comprising increasing each reference level of the 2 ^m -1 sense amplifiers to a 2 ^m level when the group indicator is increased. 12. The method of claim 11, further comprising reducing the reference level of each of the 2 ^m -1 sense amplifiers to a 2 ^m level when the group indicator is reduced. a) storing m bits in a first group of levels of memory cells; b) adjusting a group indicator to identify a subsequent group of levels of the memory cell; c) storing the m replacement bits following the subsequent group of levels without deleting the memory cells; And d) repeating steps b) and c), wherein m is greater than or equal to two. The method of claim 14, e) deleting the memory cell; And f) initializing the group indicator.