KR100293460B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR100293460B1
KR100293460B1 KR1019940012101A KR19940012101A KR100293460B1 KR 100293460 B1 KR100293460 B1 KR 100293460B1 KR 1019940012101 A KR1019940012101 A KR 1019940012101A KR 19940012101 A KR19940012101 A KR 19940012101A KR 100293460 B1 KR100293460 B1 KR 100293460B1
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South Korea
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shield ring
surface roughness
semiconductor device
particles
exposed
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KR1019940012101A
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Korean (ko)
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KR950034623A (en
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이원상
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구자홍
엘지전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve reliability of a semiconductor device by minimizing the generating amount of deposit particles and quartz particles. CONSTITUTION: A shield ring(1) is installed in an etch chamber for semiconductor fabrication in order to fix a gas injection part and an upper electrode of an upper portion of the etch chamber. A surface of an edge portion(P) of the shield ring(1) used for adhering deposit particles in an etch process has maximum surface roughness within a predetermined range. A surface of an exposed portion(Q) of the shield ring(1) exposed by plasma has minimum surface roughness within the predetermined range. The surface of the exposed portion(Q) of the shield ring(1) is polished by a grinding method, a lapping method, and a thermal processing method. An etch profile is obtained correctly by minimizing an influence due to deposit particles and quartz particles since the surface of the edge portion(P) of the shield ring(1) has maximum surface roughness within the predetermined range.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 발명은 반도체소자 제조를 위한 식각용 챔버의 쉴드 링에 관한 것으로서, 더욱 상세하게는 옥사이드(Oxide) 식각용 챔버의 쉴드 링의 표면조도(surface roughness)를 영역별로 달리하여 식각공정에 영향을 각종 파티클(particle)의 발생을 최소화할 수 있도록 한 것이다.The present invention relates to a shield ring of an etching chamber for manufacturing a semiconductor device, and more particularly, by varying the surface roughness of the shield ring of an oxide etching chamber for each region to affect the etching process. It is to minimize the generation of particles (particle).

일반적으로, 쉴드 링(1)(shield ring)은 식각용 챔버(도시는 생략함) 상부의 가스 인젝션 파트(도시는 생략함), 상부전극(2), 상기 상부전극(2) 상부의 쿨링 플레이트(3), 상부전극 고정구(4) 등의 부분을 밀착 고정시켜 주는 역할을 하는 구성품으로서, 쉴드 링(1)의 일부분은 식각 진행시 플라즈마(plasma)에 노출되어 상기 플라즈마에 의해 식각되므로써 석영 파티클(Quartz particle)들을 발생시키게 된다.In general, the shield ring 1 (shield ring) is a gas injection part (not shown) above the etching chamber (not shown), the upper electrode (2), the cooling plate on the upper electrode (2) (3), which is a component that serves to fix the upper electrode fixture (4), etc. in close contact, a portion of the shield ring 1 is exposed to the plasma (plasma) during the etching proceeds by being etched by the plasma, the quartz particles Will generate (Quartz particles).

석영 파티클의 발생량은 특히 고전압(High power)이 요구되는 공정에서 심하며, 표면조도와 밀접한 관련이 있다.The amount of quartz particles generated is particularly severe in processes requiring high power, and is closely related to surface roughness.

즉, 쉴드 링(1)의 전체적인 표면조도가 크면 클수록 석영 파티클의 발생량도 이에 비례하여 증가하게 된다.That is, as the overall surface roughness of the shield ring 1 increases, the amount of quartz particles generated increases proportionally.

따라서, 쉴드 링(1)의 표면을 한층 더 정밀하게 연마하여 표면조도를 낮추면 식각 진행시 생성되는 석영 파티클의 발생량은 줄일 수가 있으나, 그 대신 후술하는 바와 같은 문제점을 야기하게 된다.Therefore, if the surface of the shield ring 1 is polished more precisely and the surface roughness is lowered, the amount of quartz particles generated during the etching process may be reduced, but instead, it causes problems as described below.

즉, 식각 진행시 쉴드 링(1)의 플라즈마에 노출되지 않는 가장자리 부분(P)의 표면에 반응가스로부터 생성된 퇴적성 파티클(deposit particle)인 폴리머(polymer)가 쉽게 부착되어야만 웨이퍼의 오염을 줄일 수 있는데, 이를 위해서는 전술한 바와는 반대로 쉴드 링(1)의 표면조도가 커야만 한다.That is, when etching is performed, a polymer, which is a deposition particle generated from the reaction gas, is easily attached to the surface of the edge portion P that is not exposed to the plasma of the shield ring 1 to reduce contamination of the wafer. To this end, the surface roughness of the shield ring 1 must be large, as opposed to the above.

따라서, 식각 공정시 플라즈마의 영향에 의해 발생하는 석영 파티클을 줄이기 위해서는 쉴드 링(1)의 표면조도를 작게 해야 하고, 퇴적성 파티클인 폴리머가 웨이퍼 표면에 떨어지지 않도록 폴리머에 대한 쉴드 링(1)의 부착성을 좋게 하기 위해서는 쉴드 링(1)의 표면조도를 크게 해야 한다.Therefore, in order to reduce the quartz particles generated by the influence of plasma during the etching process, the surface roughness of the shield ring 1 should be reduced, and the polymer of the depositing particle should not fall on the wafer surface. In order to improve adhesion, the surface roughness of the shield ring 1 should be increased.

그러나, 종래의 쉴드 링(1) 표면은 도 1 및 도 2에 나타낸 바와 같이, 전체적으로 동일한 값의 표면조도를 갖도록 제작되므로 인해, 석영 파티클 감소 및 퇴적성 파티클에 대한 부착성 향상이라는 두가지 목적중 어느 한 가지만을 만족시킬 수 있을 뿐, 두 가지 목적을 동시에 만족시킬 수는 없었다.However, since the surface of the conventional shield ring 1 is manufactured to have the same surface roughness as a whole, as shown in Figs. 1 and 2, either of the two objectives of reducing quartz particles and improving adhesion to deposited particles are shown. Only one thing could be satisfied, but not two purposes at the same time.

본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 옥사이드(Oxide) 식각용 챔버의 쉴드 링의 표면조도를 영역별로 달리하여 식각 공정에 악영향을 미치는 퇴적성 파티클 및 석영 파티클의 발생을 최소화할 수 있도록 한 반도체소자 제조를 위한 식각용 챔버의 쉴드 링을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, by varying the surface roughness of the shield ring of the oxide (Oxide) etching chamber for each region to minimize the generation of depositing particles and quartz particles that adversely affect the etching process It is an object of the present invention to provide a shield ring of an etching chamber for manufacturing a semiconductor device.

도 1은 종래의 쉴드 링을 나타낸 종단면도1 is a longitudinal sectional view showing a conventional shield ring

도 2는 도 1의 A부 확대도2 is an enlarged view of a portion A of FIG.

도 3a 및 도 3b는 쉴드 링의 표면조도와 각종 파티클과의 관계를 나타낸 그래프로서,3A and 3B are graphs showing the relationship between the surface roughness of the shield ring and various particles;

도 3a는 쉴드 링의 표면조도와 웨이퍼 표면으로의 퇴적성 파티클 낙하량과의 관계를 나타낸 그래프3A is a graph showing the relationship between the surface roughness of the shield ring and the amount of deposited particles falling to the wafer surface;

도 3b는 쉴드 링의 표면조도와 석영 미립자 파티클 발생량과의 관계를 나타낸 그래프3B is a graph showing the relationship between the surface roughness of the shield ring and the amount of quartz fine particle generation

도 4는 본 발명에 따른 쉴드 링을 나타낸 종단면도Figure 4 is a longitudinal cross-sectional view showing a shield ring according to the present invention

도 5는 도 4의 B부 확대도5 is an enlarged view of a portion B of FIG.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

1:쉴드 링 2:상부전극1: shield ring 2: upper electrode

3:쿨링 플레이트3: cooling plate

P:쉴드 링의 플라지마에 노출되지 않는 가장자리 부분P: Edge part which is not exposed to plasma of shield ring

Q:쉴드 링의 플라즈마에 노출되는 부분Q: part exposed to plasma of shield ring

상기한 목적을 달성하기 위해, 본 발명은 반도체소자 제조를 위한 식각용 챔버 내에 설치되어 챔버 상부의 가스 인젝션 파트 및 상부전극 등의 파트들을 밀착 고정시켜주는 역할을 하는 쉴드 링에 있어서; 상기 쉴드 링의 표면중 식각 진행시 퇴적성 파티클이 부착되는 부분의 표면은 표면조도가 일정범위 내에서 최대치가 되도록 하는 대신, 식각 진행시 플라즈마에 노출되는 부분의 표면은 표면조도가 최소치가 되도록 한 것을 특징으로 하는 반도체소자 제조를 위한 식각용 챔버의 쉴드 링이 제공된다.In order to achieve the above object, the present invention is a shield ring installed in the etching chamber for manufacturing a semiconductor device serves to closely fix the parts such as the gas injection part and the upper electrode of the upper chamber; The surface of the portion of the shield ring to which the deposition particles are attached during the etching process has a maximum surface roughness within a predetermined range, but the surface of the portion exposed to the plasma during the etching process has a minimum surface roughness. Provided is a shield ring of an etching chamber for manufacturing a semiconductor device.

이하, 본 발명의 일실시예를 첨부도면 도 4 및 도 5를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.

도 4는 본 발명에 따른 쉴드 링을 나타낸 종단면도이고, 도 5는 도 4의 B부 확대도로서, 반도체소자 제조를 위한 식각용 챔버 내에 설치되어 챔버 상부의 가스 인젝션 파트 및 상부전극(2) 등의 파트들을 밀착 고정시켜주는 역할을 하는 쉴드 링(1)에 있어서; 상기 쉴드 링(1)의 표면중 식각 진행시 퇴적성 파티클이 부착되는 가장자리 부분(P)의 표면은 표면조도가 일정범위 내에서 최대치가 되도록 하는 대신, 식각 진행시 플라즈마에 노출되는 부분(Q)의 표면은 표면조도가 최소치가 되도록하여 구성된다.4 is a longitudinal sectional view showing a shield ring according to the present invention, Figure 5 is an enlarged view of the portion B of Figure 4, the gas injection part and the upper electrode (2) is installed in the chamber for etching for manufacturing a semiconductor device In the shield ring (1) which serves to close and secure the parts of the back; In the surface of the shield ring 1, the surface of the edge portion P, to which the deposition particles are attached during the etching process, does not allow the surface roughness to be the maximum within a predetermined range, but is exposed to the plasma during the etching process (Q). The surface of is composed of the surface roughness to the minimum value.

이 때, 상기 쉴드 링(1)에 있어서, 식각 진행시 플라즈마에 노출되는 부분(Q)의 표면은 글라인딩(grinding) 또는 랩핑(lapping) 또는 열처리 기법에 의해 폴리싱(polishing)된다.At this time, in the shield ring 1, the surface of the portion Q exposed to the plasma during the etching process is polished by grinding or lapping or heat treatment.

이와 같이 구성된 본 발명의 쉴드 링(1)은 식각 진행시 플라즈마에 노출되지 않는 가장자리 부분(P)의 표면조도가 최대치여서 퇴적성 파티클이 쉽게 부착되므로 인해 퇴적성 파티클로 인한 웨이퍼의 오염을 최소화할 수 있게 된다.The shield ring 1 of the present invention configured as described above has a maximum surface roughness of the edge portion P which is not exposed to the plasma during the etching process so that the deposition particles are easily attached, thereby minimizing the contamination of the wafer due to the deposition particles. It becomes possible.

또한, 본 발명의 쉴드 링(1)은 식각 진행시 플라즈마에 노출되는 부분(Q)이 글라인딩(grinding) 또는 랩핑(lapping) 또는 열처리에 의해 폴리싱되어 표면조도가 최소화된 상태이므로, 플라즈마에 의해 식각되어 발생하는 석영 파티클의 발생량 또한 최소가 된다.In addition, since the shield ring 1 of the present invention is polished by grinding, lapping, or heat treatment, the portion Q exposed to the plasma during etching proceeds to minimize the surface roughness. The amount of quartz particles generated by etching is also minimized.

따라서, 본 발명에 따른 쉴드 링(1)을 이용하여 옥사이드(Oxide) 식각 공정을 진행할 경우에는 퇴적성 파티클인 폴리머로 인한 영향 및 석영 파티클로 인한 영향을 최소화하여 정확한 식각 프로파일(profile)을 얻을 수 있는 등 식각 공정의 신뢰성을 향상시킬 수 있게 된다.Therefore, when the oxide (etch) process is performed using the shield ring 1 according to the present invention, an accurate etching profile can be obtained by minimizing the effects of polymer particles and quartz particles. It is possible to improve the reliability of the etching process.

이상에서와 같이, 본 발명은 옥사이드(Oxide) 식각용 챔버의 쉴드 링(1)의 표면조도를 영역별로 달리한 것이다.As described above, in the present invention, the surface roughness of the shield ring 1 of the oxide etching chamber is changed for each region.

이에 따라, 본 발명은 식각 공정에 악영향을 미치는 석영 파티클을 최소화하는 한편 퇴적성 파티클로 인한 악영향을 최소화하여 식각 공정의 수율 및 신뢰성을 향상시킬 수 있게 된다.Accordingly, the present invention can minimize the quartz particles adversely affecting the etching process while minimizing the adverse effects due to the deposition particles, thereby improving the yield and reliability of the etching process.

Claims (2)

반도체소자 제조를 위한 식각용 챔버 내에 설치되어 챔버 상부의 가스 인젝션 파트 및 상부전극 등의 파트들을 밀착 고정시켜주는 역할을 하는 쉴드 링에 있어서;A shield ring installed in an etching chamber for manufacturing a semiconductor device, the shield ring serving to closely fix parts such as a gas injection part and an upper electrode in an upper part of the chamber; 상기 쉴드 링의 표면중 식각 진행시 퇴적성 파티클이 부착되는 가장자리 부분(P)의 표면은 표면조도가 일정범위 내에서 최대치가 되도록 하는 대신, 상기 실드 링의 표면중 식각 진행시 플라즈마에 노출되는 상기 가장자리 부분(P) 내측 부분(Q)의 표면은 표면조도가 최소치가 되도록 한 것을 특징으로 하는 반도체소자 제조를 위한 식각용 챔버의 쉴드 링.In the surface of the shield ring, the surface of the edge portion P to which the deposition particles are attached during the etching process is not exposed to the plasma during the etching process in the surface of the shield ring, instead of allowing the surface roughness to be the maximum within a predetermined range. The surface of the inner edge portion (Q) of the edge portion (P) is a shield ring of the etching chamber for manufacturing a semiconductor device, characterized in that the surface roughness to the minimum value. 제 1 항에 있어서,The method of claim 1, 상기 쉴드 링의 식각 공정시 플라즈마에 노출되는 부분의 표면은 글라인딩(grinding) 또는 랩핑(lapping) 또는 열처리 기법에 의해 폴리싱됨을 특징으로 하는 반도체소자 제조를 위한 식각용 챔버의 쉴드 링.The surface of the portion exposed to the plasma during the etching process of the shield ring is polished by grinding, lapping or heat treatment techniques, the shield ring of the etching chamber for manufacturing a semiconductor device.
KR1019940012101A 1994-05-31 1994-05-31 Method for fabricating semiconductor device KR100293460B1 (en)

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KR100293460B1 true KR100293460B1 (en) 2001-11-30

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910015016A (en) * 1990-01-30 1991-08-31 이헌조 InGaAs / GaAs MESFET Manufacturing Method
JPH04369841A (en) * 1991-06-19 1992-12-22 Sumitomo Electric Ind Ltd Compound semiconductor device and manufacture thereof
JPH05206171A (en) * 1992-01-27 1993-08-13 Sumitomo Electric Ind Ltd Semiconductor device and manufacture thereof
KR930017203A (en) * 1992-01-14 1993-08-30 김광호 Compound Semiconductor Device and Manufacturing Method Thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910015016A (en) * 1990-01-30 1991-08-31 이헌조 InGaAs / GaAs MESFET Manufacturing Method
JPH04369841A (en) * 1991-06-19 1992-12-22 Sumitomo Electric Ind Ltd Compound semiconductor device and manufacture thereof
KR930017203A (en) * 1992-01-14 1993-08-30 김광호 Compound Semiconductor Device and Manufacturing Method Thereof
JPH05206171A (en) * 1992-01-27 1993-08-13 Sumitomo Electric Ind Ltd Semiconductor device and manufacture thereof

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