KR100293066B1 - Multi-level memory device having an ecc circuit - Google Patents

Abstract

The read-only multi-level memory device stores memory cells 11 ₁ , 11 ₂ , 11 ₃ storing read-only data and memory cells 11 ₄ , 11 ₅ storing parity data for correcting one bit of read-only data. Contains a block of). Each memory cell 11 includes a cell transistor having a threshold voltage selected from a plurality of levels. The two read data read by the read circuits 12, 13 and 16 from cell transistors having adjacent voltage thresholds have only one bit different and the remaining bits are the same. Read data can be effectively corrected by using parity bits.

Description

MULTI-LEVEL MEMORY DEVICE HAVING AN ECC CIRCUIT}

The present invention relates to a multi-level memory device having an ECC (Error Checking and Correcting) circuit, and more particularly to an ECC capable of increasing the possibility of error correction by having a 1-bit ECC function for data stored in a multi-level memory cell. It is about a circuit.

ECC circuits are widely used in semiconductor integrated circuits including multi-level memory devices for reliable data transfer. A conventional ECC circuit having a 1-bit ECC function for a multi-level memory cell is disclosed, for example, in JP-A-7-238423. Such conventional ECC circuits will be described below with reference to read-only memory devices having multi-level memory cells for respectively storing 2-bit data. The ECC circuit has a 1-bit ECC function by using 4-bit parity data for 6-bit read-only data.

Referring to FIG. 1, a conventional multi-level semiconductor ROM includes a plurality of multi-level memory cells 11 and memory cells arranged in a matrix and forming a plurality of blocks each including memory cells 11 ₁ to 11 ₅ . A sense amplifier 12 for detecting data on each bit line 20 arranged for the corresponding column of the < RTI ID = 0.0 >),< / RTI > three latch circuits 13A, 13B, respectively connected to the output of the corresponding sense amplifier 12, and 13C), an encoder 26 for encoding outputs from latch circuits 13A, 13B, and 13C, a syndrome calculator 17 for processing output from encoders 26 to generate syndrome parameters, syndrome A syndrome decoder 18 for decoding syndrome parameters output from the calculator 17 and a correction circuit for correcting one bit of the outputs from the encoders 26 based on the output from the syndrome decoder 18. Including 19 . Sense amplifiers 12, latch circuits 13A, 13B, and 13C, and encoders 26 constitute a read circuit for reading data from an array of memory cells. The syndrome calculator 17 and syndrome decoder 18 configure a syndrome data generator for generating syndrome parameters for read data.

2, each multi-level memory cell 11 is implemented by a cell transistor. A plurality of cell transistors (n-channel MOSFETs) arranged in a column are connected between the bit line 20 and ground. Referring to FIG. 3, encoder 26 includes NAND gates NAND1 to NAND5 and inverters INV1 to INV4, and outputs Ln1, Ln2 from latch circuits 13A, 13B, and 13C. And Ln3) and deliver a pair of encoded outputs an0 and an1, where n = 0, 1, 2 for the three memory cells _{1 1} to 11 _{3 in} a block.

Referring to FIG. 4, the syndrome calculator 17 includes twelve Ex-OR gates and outputs a00, a01, a10, a11, a20, a21, a30, a31, from one block of encoders 26. Input values are received via a40 and a41 to generate 4-bit ECC codes ECC0 to ECC3. ECC0 is obtained as Ex-OR of a00 and a01 and Ex-OR of Ex10 to a10 and a30. ECC1 is obtained as Ex-OR of a00 and a11 and Ex-OR of Ex-OR of a20 and a31. ECC2 is obtained as Ex-OR of a01 and a11 and Ex-OR of a21 and a40 Ex-OR. ECC3 is obtained as an Ex-OR of a10 and a20 and an Ex-OR of a21 and a41 Ex-OR.

Referring to FIG. 5, the syndrome decoder 18 includes inverters, NAND gates, and receives the ECC codes ECC0 to ECC3 to decode the outputs a00 ', a01', a11 ', a20', And a21 ').

6, each correction circuit 19 receives the output ani (n = 0, 1, 2 and i = 0, 1) from the encoder 26 and outputs Ex- for outputting the corrected data Dni. Implemented by the OR gate. The 6 bit data D00, D01, D10, D11, D20, and D21 output from the correction circuits 19 are used as read data read from the multi-level ROM.

Each memory cell 11 has a specified threshold voltage level selected from four levels of predetermined threshold voltages. 7 shows a gate voltage applied to the gate of each cell transistor. The waveform includes a first level of the first stage, a second level of the second stage, and a third level of the third stage, which rises with time. Table 1 shows the relationship between the threshold voltage Vth of the cell transistor and the latch circuits 13A, 13B, and 13C and the outputs of the encoder 26.

Vth Latch A Latch B Latch C Encoder Ln1 Ln2 Ln3 An0 an1 First level 0 0 0 0 0 Second level One 0 0 0 One 3rd level One One 0 One 0 High level One One One One One

That is, the outputs Ln1 to Ln3 (n = 0, 1, 2) of the latch circuits 13A, 13B, and 13C connected to the sense amplifier 12 are based on the stage at which the cell transistors are turned on. Will be values as indicated in Table 1. For example, if the cell transistor of the designated cell is turned on to the second level, the outputs Ln1, Ln2, and Ln3 of the latch circuits 13A, 13B, and 13C corresponding to the designated cell (n = 0) , 1, 2) becomes (Ln1, Ln2, and Ln3) = (1, 0, 0) as indicated in the second row of Table 1. The outputs of the three latch circuits 13A, 13B, and 13C are supplied to a corresponding encoder 26, which outputs encoded outputs '01'. Thus, 2-bit data can be read from the cell transistor as the outputs of encoder 26.

Each output pair (a00 and a01, a10 and a11, or a20 and a21) constitutes 2-bit data read from a designated read-only memory cell in the block, and each output pair (a30 and a31, or a41 and a42). Configures 2-bit parity data output from a parity cell or a redundant cell in a block. Parity cells (11 ₄ and 11 ₅₎ is also implemented as a multilevel cell stores a 4-bit parity data in the memory cells (11 ₄ and 11 ₅₎ in the block.

Referring back to FIG. 1, one of the read data including the ten bits a00, a01, a10, a11, a20, a22, a30, a31, a41, and a42 output from the five encoders 26. Assume a bit has an error. In this case, one of the outputs a00 ', a01', a10 ', a11', a20 ', and a21' of the syndrome decoder 18 corresponding to the error bit is based on the 1-bit ECC function of the ECC circuit. Assume '1'.

Outputs from the syndrome decoder 18 are supplied to correction circuits 19, one of which is based on the Ex-OR shown in FIG. 6 and outputs a00 ', of the outputs a00, a01, a10, a11, a20, and a21 from the encoder 26 corresponding to the bits assumed to be '1' among a01 ', a10', a11 ', a20', and a21 '. By inverting one, the error output from the encoder 26 is corrected.

In one case, the memory cells 11 ₁ , 11 ₂ , and 11 ₃ are scheduled such that each transistor is turned on to the second stage, the first stage, and the third stage, respectively. In this case, the three output groups of the latch circuits 13A, 13B, and 13C are (L01, L02, L03) = (1, 0, 0), (L11, L12, L13) = (0, 0, 0), and (L21, L22, L23) = (1, 1, 0). Thus, the outputs of encoder 26 are (a00, a01, a10, a11, a20, a21) = (0, 1, 0, 0, 1, 0) as can be seen from Table 1. The parity bit stored in the parity cells (11 ₄ and 11 ₅₎ in this case are (1, 1, 1, 1) corresponding to the bit (a30, a31, a40, a41).

In this case, if the outputs a00, a01, a10, a11, a20, a21, a30, a31, a40, and a41 from the encoders 26 do not contain an error, all of the syndrome decoder 18 The outputs will be '0', so that the outputs of the correction circuits D00 and D01, D10 and D11, D20 and D21 match (a00, a01, a10, a11, a20, a21) (0, 1) , 0, 0, 1, 0).

However, in the multi-level memory as described above, there is a problem that the EEC circuit sometimes cannot correct an error when the cell transistor has a defect turned on at a level different from the desired level.

For example, if the memory cell 11 ₁ corresponding to the outputs D00 and D01 is turned on to the first level differently from the desired second level in this case, the first group of latch circuits 13A, 13B , And 13C) outputs (L01, L02, L03) = (0, 0, 0), and the outputs of encoders 26 are (a00, a01, a10, a11, a20, a21) = (0, 0, 0, 0, 1, 0). Thus, the outputs of the syndrome encoder 18 are (a00 ', a01', a10 ', a11', a20 ', a21') = (0, 1, 0, 0, 0, 0), so that the correction circuit 19 ) Outputs (D00, D01, D10, D11, D20, D21) = (0, 1, 0, 0, 1, 0) after valid correction of a01 bit. In this case, the ECC circuit has a valid 1 bit ECC function.

Instead of the above case, if the memory cell _{1 1 1} has a defect in which the cell transistor is turned on to a third level different from the desired second level, the first group of latch circuits 13A, 13B, and 13C. ) Outputs (L01, L02, L03) = (1, 1, 0), and the outputs of encoders 29 are (a00, a01, a10, a11, a20, a21) = (1, 0, 0 , 0, 1, 0). In this case, the outputs of the syndrome decoder 18 are (a00 ', a01', a10 ', a11', a20 ', a21') = (0, 0, 0, 1, 0, 0), so that the correction circuit The outputs of are (D00, D01, D10, D11, D20, D21) = (1, 0, 0, 1, 1, 0) after the wrong correction of all bits. Thus, the ECC circuit cannot correct the error in the outputs of the memory device.

Such defects sometimes occur when the cell has a defect such that the voltage level at which the cell transistor is turned on deviates to the next lower or higher level.

In view of the above, it is an object of the present invention to provide a memory device having an ECC circuit for a multi-level memory cell that can increase the possibility of valid error correction in the event of a defect occurring in the memory cell.

The present invention provides a plurality of multi-level memory cells for storing multi-level data, a read circuit for reading data from memory cells and outputting read data including a plurality of bits, and bits corresponding to the number of bits of the read data. A syndrome data generator for generating parity data having a number, and a correction circuit for correcting one of the bits of the read data based on the corresponding one of the bits of the parity data. In this regard, the readout circuitry reads the read data such that two adjacent levels of multi-level data stored in each memory cell provide two different read data having values common to all bits, not for a single bit. Create

According to the memory device of the present invention, when a memory cell has a defect in which a cell transistor is turned on at a level different from a desired level, the ECC circuit of the memory device has a valid 1-bit ECC function for correcting an error caused by the defect. Will have

The above and other objects, features, and advantages of the present invention will become more apparent by reference to the following detailed description in conjunction with the accompanying drawings.

1 is a block diagram of a conventional multi-level memory having an ECC circuit.

2 is a circuit diagram of a typical memory cell shown in FIG.

3 is a logic circuit diagram of the encoder shown in FIG.

4 is a logic circuit diagram of the syndrome calculator shown in FIG.

5 is a logic circuit diagram of the syndrome decoder shown in FIG. 1;

6 is a logic circuit diagram of the correction circuit shown in FIG.

7 is a timing chart showing waveforms of gate voltages supplied to the cell transistors shown in FIG. 2;

Fig. 8 is a block diagram of a multi level memory having an ECC circuit according to the first embodiment of the present invention.

9 is a logic circuit diagram of the encoder shown in FIG. 8;

10 is a logic circuit diagram of a parity circuit used to store parity bits in the parity cell shown in FIG.

Fig. 11 is a block diagram of a multilevel memory having an ECC circuit according to a second embodiment of the present invention.

12 is a timing chart showing waveforms of gate voltages supplied to the cell transistors shown in FIG. 11;

<Explanation of symbols for main parts of the drawings>

11: memory cell

12: sense amplifier

13A, 13B, 13C: Latch Circuit

16: encoder

17: syndrome calculator

18: syndrome decoder

19: correction circuit

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, similar components will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like elements for easier understanding of the present invention.

Referring to FIG. 8, a multilevel (in this case 4 level) read only memory device having an ECC circuit according to the first embodiment of the present invention is a block of memory arranged in a matrix and storing 2-bit data respectively. A plurality of read only memory cells 11 comprising cells 11 ₁ to 11 ₅ . The data to be stored is realized by a threshold voltage selected for the cell transistor, which may have a first level, a second level, a third level, or a higher level. Three read-only memory cells 11 ₁ to 11 ₃ arranged in rows form a group, with a pair of redundant memory cells 1 1 ₄ and 11 ₅ arranged in the same row attached thereto to Memory cells _{1 1 1} to 11 ₅ are formed. When a group of read-only memory cells ₁ 1-11 ₃ are programmed by specifying threshold voltages for the cell transistors, the pair of redundant cells 114 and 115 cause three read-only memory cells ₁ 1-11 ₃ . It is also programmed with the data specified by the data stored therein. Thus, each block stores 6 bits of read only data and 4 bits of parity data to achieve a 1 bit ECC function for correcting this 6 bits of read only data.

A sense amplifier 12 is arranged for each column of memory cells 11 to detect ON or OFF of the selected cell transistor via corresponding bit line 20. Three latch circuits 13A, 13B, and 13C are arranged for each sense amplifier! 2 and are subsequently activated to latch data that is continuously output from the sense amplifier 12. An encoder 16 is arranged to decode the respective outputs of the three latch circuits 13A, 13B, and 13C to output two bits of data to the correction circuits 19. The outputs of the encoders 16 arranged for each block of memory cells 11 ₁ to 11 ₅ are also supplied to a corresponding syndrome calculator 17, the output of which is decoded by the syndrome decoder 18. . The decoded outputs of the syndrome decoder 18 are supplied to correction circuits 19, which are corrected from encoder 16 with or without correction based on the corresponding output bits of syndrome decoder 18. The output read data a00, a01, a10, a11, a20, or a21 is supplied as output data D00, D01, D10, D11, D20, or D21 of the memory device, respectively.

2, each memory cell 11 is implemented by a cell transistor having a specified threshold voltage, and cell transistors in each column are connected between the corresponding bit line 20 and ground.

Referring to FIG. 9, each encoder 16 has an inverter INV0 for receiving the output Ln3 from the latch circuit 13C, a pair of outputs Ln1 and the latch circuits 13A and 13B. NAND gate NAND1 for receiving Ln2, output Ln1 from latch circuit 13A and NAND gate NAND2 for receiving output from inverter INV0, and an output from NAND1 encoded An inverter INV1 for outputting the output bit an0, and an inverter INV2 for receiving the output from NAND2 and outputting the encoded output bit an1. In this configuration, the decoder 16 outputs the designated output bits according to the following Table 2.

The syndrome calculator 17, the syndrome decoder 18, and the correction circuits 19 have a configuration similar to that in the description of the prior art with reference to FIGS. 4, 5, and 6, respectively. Therefore, detailed description of these circuits will be omitted.

The output pairs a00 and a01, a10 and a11, and a20 and a21 of the encoders 16 correspond to 2-bit data in the corresponding memory cells 11 ₁ , 11 ₂ , and 11 ₃ , respectively, and output pairs a30. and a31, and a40 and a41) are respectively corresponding to the stored 2-bit parity data in the redundant cells (11 ₄ and 11 _5).

Table 2, similar to Table 1, shows the relationship between the cell data realized by the level of the threshold voltage for the cell transistor and the outputs of the latch circuits 13A, 13B, and 13C and the encoder 16.

Threshold voltage Latch A Latch B Latch C Encoder Ln1 Ln2 Ln3 an0 an1 First level 0 0 0 0 0 Second level One 0 0 0 One 3rd level One One 0 One One High level One One One One 0

In this embodiment, the output pairs an0 and an1 of the encoder are at a first level, a second level, a third level, and a high level of the gate voltage supplied to the cell transistor due to the specified level of the threshold voltage for the cell transistor. Assume (0, 0), (0, 1), (1, 1) and (1, 0), respectively. That is, when the level of the threshold voltage transitions to an adjacent level due to a defect in the cell transistor, only one of the output bit pairs an0 and an1 of the encoder 16 is changed by any transition. Conversely, in the outputs of encoder 16 in a conventional memory, as shown in Table 1, when the threshold voltage transitions from the second level to the third level due to a defect in the cell transistor, both outputs an0 And an1) all transition from '0' to '1' and from '1' to '0', respectively. This means that conventional memory devices provide a wrong output.

In operation, the gate of the selected cell transistor is supplied with a voltage having the waveform shown in FIG. This waveform has a first level of the first stage, a second level of the second stage, and a third level of the third stage that rises with time. The outputs of the latch circuit are determined to follow Table 2. That is, the latch circuit A is activated in the first stage, the latch circuit B is activated in the second stage, and the latch circuit C is activated in the third stage for detecting the output voltage of the sense amplifier. For example, if the selected cell transistor is turned on to the second level, the outputs Ln1, Ln2, Ln3 of the three latch circuits A, B, and C in one group are n = 0, 1, Or (Ln1, Ln2, Ln3) = (1, 0, 0) for 2. The outputs of these latch circuits are supplied to an encoder 16 which outputs two bits of encoded data an0, an1 = (0, 1).

The 2-bit data output from the encoder 16, for example, a00 and a01 correspond to the 2-bit data stored in the selected memory cell _{1 1 1} and are supplied to the syndrome calculator 17. The syndrome calculator 17 calculates the syndrome parameter therefrom as 2-bit data and supplies it to the syndrome decoder 18. If one of the outputs from the syndrome decoder 18 has an error, the outputs of the syndrome decoder 18 will be '1'.

The outputs of the syndrome decoder 18 are supplied to correction circuits 19, each of which is implemented by an Ex-OR gate shown in FIG. 6 and outputs from the syndrome decoder 18 a corresponding bit. If is '1', one of the bits output from the encoders 16 is reversed, thereby correcting the error bit among the outputs from the encoders 16.

In one case, similar to the case described for a conventional memory device, three memory cells 11 ₁ , 11 ₂ , and 11 _{3 in} a block are configured to have a second level, a first level, and a third level of threshold voltage. Store data corresponding to each level. In this case, the three groups of latch circuits 13A, 13B, and 13C have outputs L01, L02, L03 = (1, 0, 0), (L11, L12, L13) = (0, 0 , 0), and (L21, L22, L23) = (1, 1, 0) and the outputs of encoder 16 are (a00, a01, a10, a11, a20, a21) as can be seen from Table 2. ) = (0, 1, 0, 0, 1, 1)

Stored in the redundant cells (11 ₄ and 11 ₅₎ parity bits by using a logic circuit such as that shown in Figure 10 the three read-only memory cells (11 _1, 11 _2, and 11 ₃₎ stored in the in the block It can be reproduced by a logic circuit having the same configuration as that shown in FIG. In this example, the parity data stored in the parity cells (11 ₄ and 11 ₅₎ is (a30, a31, a40, a41 ) = (1, 1, 0, 0). That is, if there are no errors in the outputs a00, a01, a11, a20, a21, a30, a31, a40, a41 of the encoder 16, the outputs of the syndrome decoder 18 are all '0'. , The outputs of the correction circuits 19 correspond to the outputs a00, a01, a11, a20, a21 of the encoder 16 (D00, D01, D10, D11, D20, D21) = (0, 1, 0, 0, 1, 1).

In the case listed above, if there is a fault in the cell transistor in the cell _{1 1 1} turned on to the first level of the applied voltage regardless of the predetermined second level of the threshold voltage, the outputs of the latch circuits are (L01, L02). , L03) = (0, 0, 0), and the outputs of encoder 16 are (a00, a01, a10, a11, a20, a21) = (0, 0, 0, 0, 1, 1) .

If the outputs of the syndrome decoder 18 are (a00 ', a01', a10 ', a11', a20 ', a21') = (0, 1, 0, 0, 0, 0), then the output a01 is stored reading '1' of the a01 'bit is set by the correction circuit 19 which outputs (D00, D01, D10, D11, D20, D21) = (0, 1, 0, 0, 1, 1) matching the dedicated data. Corrected on the basis of

On the other hand, if there is a defect in which the cell transistor is turned on to the third level irrespective of the predetermined second level in this case, the outputs of the latch circuits 13A, 13B, and 13C are (L01, L02, L03) = (1, 1, 0), and the outputs of the encoders 16 are (a00, a01, a10, a11, a20, a21) = (1, 1, 0, 0, 1, 1). In this case, the outputs of the syndrome decoder 18 are (a00 ', a01', a10 ', a11', a20 ', a21') = (1, 0, 0, 0, 0, 0), which is correct One of the circuits 19 causes the a00 bit to be corrected. Therefore, the ECC circuit matches (D00, D01, D10, D11, D20, D21) = (0, 1, 0, 0, 1, 1) that matches the stored data regardless of the defect in which the conventional ECC circuit caused an error. Provide correct outputs.

As described above, in the ECC circuit of the multi-level memory of the present embodiment, an error caused by a defect in which the cell transistor is turned on at a level adjacent to the predetermined level can be corrected intermittently, thereby obtaining reliable read data. .

In this embodiment, the threshold voltages of the cell transistors are detected by supplying gate voltages of different levels. While the gate voltage applied is kept constant, a plurality of reference amplifiers may be arranged instead of detecting different current levels of the cell transistors.

Referring to FIG. 11, a read-only multilevel (8 level) memory device having an ECC circuit according to the second embodiment includes a plurality of multilevel memory cells 10 (10 ₁ , 10 ₂ ) each storing three bits of data. , ...). Similar to the first embodiment, three memory cells storing read-only data form a group, and a pair of redundant memory cells are attached to form a block. In this configuration, one block of memory cells stores 15 bits of data including 9 bits of read-only data and 6 bits of parity data. This memory device comprises a group of seven latch circuits 13 for each memory cell 10, an encoder 16 arranged for each memory cell to encode the outputs of the group of latch circuits 13. ), Syndrome calculator 17, syndrome decoder 18, and correction circuits 19, which are similar to the first embodiment except for the number of bits of data.

Referring to FIG. 12, a gate voltage applied to the gate of each cell transistor is shown. The gate voltage includes the first to seventh levels of each of the first to seventh stages that rise with time. Based on gate voltages of different levels, data stored in cell transistors 10 may be read by latch circuits 13 through sense amplifier 12. Table 3 shows the relationship between the threshold voltage of the cell transistor and the outputs of the latch circuits 13 and the encoder.

Vth L.A L.B L.C L.D L.E L.F L.G Encoder Ln1 Ln2 Ln3 Ln4 Ln5 Ln6 Ln7 an0 An1 an2 1 L 0 0 0 0 0 0 0 0 0 0 2 L One 0 0 0 0 0 0 0 One 0 3 L One One 0 0 0 0 0 0 One One 4th L One One One 0 0 0 0 0 0 One 5th L One One One One 0 0 0 One 0 One 6th L One One One One One 0 0 One One One 7th L One One One One One One 0 One One 0 Hi One One One One One One One One 0 0

As shown in Table 3, when the level of the threshold voltage is shifted to an adjacent level by a defect in the cell transistor, three bits, an0, an1, and an2, which are the outputs of the encoder 16 due to any change in the case. Only one transitions from '1' to '0' or from '0' to '1', thereby effectively correcting the 1 bit error in the block, thereby preventing the correction circuits 19 from outputting an incorrect output value.

Since the above-described embodiments are only described as an example, the present invention is not limited to the above-described embodiments and those skilled in the art can easily make various modifications and adaptations without departing from the scope of the present invention. There will be.

According to the memory device of the present invention, when a memory cell has a defect in which a cell transistor is turned on at a level different from a desired level, the ECC circuit of the memory device has a valid 1-bit ECC function for correcting an error caused by the defect. Will have

Claims (8)

In a memory device, A plurality of multi-level memory cells 11 for storing multi-level data, respectively Read circuits 12, 13, and 16 for reading data from the memory cells 11 and outputting read data including a plurality of bits; A syndrome data generator (17, 18) for generating parity data having a number of bits corresponding to the number of bits of said read data, and Correction circuitry (19) for correcting one of the bits of the read data based on the corresponding bit of the parity data Including; The read circuits 12, 13, and 16 store two different read data in which two adjacent levels of the multi-level data stored in each of the memory cells 11 have common values in all bits except one bit. And generate the read data to provide. 2. The memory cells of claim 1, wherein the memory cells 11 comprise a plurality of first memory cells 11 ₁ , 11 ₂ , 11 ₃ and the first memory cells 11 ₁ , 11 _2, 11 for storing read-only data. ₃ ) one block including a plurality of second memory cells 1 1 ₄ and 11 ₅ for storing parity bits formed on the basis of the read-only data stored in ₃ ), wherein the read circuit 12, 13, 16) reads the parity bits and supplies them to the syndrome data generator (17, 18). 2. A memory device according to claim 1, wherein each of said memory cells (11) comprises a MOSFET having a threshold voltage selected from one of a plurality of levels. 4. The memory device of claim 3, wherein the plurality of levels comprises four levels. 4. The memory device of claim 3, wherein the plurality of levels comprises eight levels. 4. The memory device of claim 3, wherein a plurality of voltage levels corresponding to the levels of the threshold voltage is applied to the gate of the MOSFET. 4. The memory device of claim 3, wherein the readout circuit comprises a plurality of reference amplifiers for detecting different levels of current in the MOSFET. 2. The read circuit of claim 1, wherein the readout circuit comprises a plurality of latch circuits 13A, 13B, and 13C disposed for a corresponding one of the memory cells 11, and the plurality of latch circuits 13A, 13B, 13C. And a decoder (16) for decoding the data output from the.