JPH11339496A - Ecc circuit for multivalued cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ECC circuit capable of performing an error correction of multivalued data with a high correction capability while employing a circuit structure in the similar size with a conventional circuit. SOLUTION: There are provided a sense amplifier 2 connected to a multivalued cell section 1 having four values and a bit line, a plurality of latch circuits 3, 4, 5 connected to outputs of the sense amplifier 2, an encoder 6 connected to the latch circuits 3-5, a syndrome calculating circuit 7 for configuring an ECC circuit from outputs of the encoder 6, a syndrome decoder 8, and a correction circuit 9 for correcting the output of the encoder 6. An encode scheme of the encoder is set such that when states that can be realized by cells of the multivalued cell are arranged side by side, a difference in output bits from the adjacent any two states becomes only 1 bit. Every defect for the adjacent states of the cells can be corrected by the ECC circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-valued cell ECC.
(Error Checking and Correcting) The present invention relates to a semiconductor integrated circuit using a circuit method, and particularly to an ECC circuit suitable for use in a semiconductor memory.

[0002]

2. Description of the Related Art An outline of a conventional method for correcting an error in a multilevel cell will be described. As a storage system for performing error detection / correction of multi-valued data, for example, the description in Japanese Patent Application Laid-Open No. 7-234823 is also referred to.

Here, as an example, four memory cells are stored in one memory cell.
Consider a 6-bit output semiconductor memory that stores value (2 bits) information and uses a 1-bit error correction coding technique.
At this time, the parity bit is 4 bits.

FIG. 11 is a diagram showing an example of a conventional circuit configuration for performing error correction in a semiconductor integrated circuit that stores multi-value information in one memory cell.

Referring to FIG. 11, a multi-level cell unit 1 and a sense amplifier 2 connected to a bit line of the multi-level cell unit 1 are shown.
First, second, and third latch circuits 3, 4, and 5 connected to the output of the sense amplifier 2, an encoder 6 'connected to these latch circuits 3, 4, and 5, an encoder It comprises a syndrome calculation circuit 7 for forming an ECC circuit from the output of 6 ', a syndrome decoder 8, and a correction circuit 9 for correcting the output of the encoder 6'.

The circuit configurations of the multi-valued cell section 1, encoder 6 ', syndrome calculation circuit 7, syndrome decoder 8, and correction circuit 9 are shown in FIGS. 2, 12, 4, 5, and 6, respectively. Referring to FIG. 2, the multi-level cell unit 1 includes cell transistors MN1, MN2, and MN3 whose sources are grounded and whose drains are connected to bit lines.

As shown in FIG. 12, an encoder 6 'receives latch outputs Ln1, Ln2, and Ln3 as inputs and outputs encoder outputs an0,
an1 (n = 0, 1, 2) output circuit (NAND gates NAND1 to NAND5, inverters INV1 to IV1)
NV4).

The outputs a00 and a0 of the encoder 6 '
1, a10 and a11, a20 and a21 are 1
It is a set of 2-bit information that can be extracted from the memory cell,
A30 and a31 and a40 and a41 are sets of 2-bit information that can be extracted from one parity cell (redundant cell). This parity cell is also a multi-level cell, and stores 4-bit parity in two cells 1-4 and 1-5.

As shown in FIG. 4, a syndrome calculation circuit 7 constituting the ECC circuit outputs an encoder output (a00-
a41) to the 4-bit error correction code (ECC0-E
CC3) is generated.

For example, ECC0 is an exclusive OR (XOR) output of a00 and a01, a10 and a parity bit a3.
It is obtained as the exclusive OR of the exclusive OR outputs of 0.
As shown in FIG. 5, the syndrome decoder 8 receives and decodes the outputs (ECC0 to ECC3) of the syndrome calculation circuit 7 and decodes the outputs (a00 ', a01', a10 ', a
11 ', a20', a21 ').

As shown in FIG. 6, the correction circuit 9 takes an exclusive OR (XOR) of the output ani of the encoder 6 'and the output ani' of the syndrome decoder 6 'and outputs Dni (where n is 0). , 1, 2, i are 0, 1). (D0
6-bit data (0, D01, D10, D11, D20, D21) are the outputs of the six correction circuits 9.

In the circuit shown in FIG. 11, the outputs of the five encoders 6 are provided. (A00, a01, a10,
a11, a20, a21, a30, a31, a40, a
41) If one of the 10 bits is incorrect,
It has an ECC circuit configuration capable of error correction.

A voltage as shown in FIG. 13 is applied to the gate of the transistor of the cell of the multi-level cell section 1. The output of the three latch circuits connected to the sense amplifier 2 is set as shown in Table 2 depending on the state of the gate voltage in FIG. I do. For example, when a current flows (ON) to a cell in a state where the gate voltage is, the output (L) of three latch circuits to which the output of the connected sense amplifier is input is connected to the cell.
(n1, Ln2, Ln3) (n = 0, 1, 2) is (Ln
(1, Ln2, Ln3) = (1, 0, 0). The outputs of the three latch circuits are input to corresponding encoders,
The output is encoded as shown in Table 2 by the state of the latch circuit and the encoder 6 'having the circuit configuration shown in FIG. This means that two bits of information have been extracted from one cell.

Two-bit information (for example, a00 and a01) taken out from one memory cell is input to a syndrome calculation circuit 7 to calculate a syndrome, and the output is input to a syndrome decoder 8. As for the output (a00'-a21 ') of the syndrome decoder 8, an output corresponding to an erroneous bit becomes "1".

The output (a00 ') of the syndrome decoder 8
−a21 ′) is input to the correction circuit 9. Correction circuit 9
Consists of an exclusive-OR (XOR) circuit as shown in FIG. 6. If there is a bit of "1" in (a00'-a21 '), the data of (a00-a21) is inverted to correct the error. correct.

Here, as one example, (D00 and D01
Cell, cells D10 and D11, cells D20 and D21) = (ON at gate voltage, ON at gate voltage, ON at gate voltage).

At this time, the outputs of the latch circuits (three are a set) connected to each sense amplifier in FIG. 11 are (L01, L02, L03) = (1, 0, 0),
(L11, L12, L13) = (0, 0, 0), (L2
1, L22, L23) = (1, 1, 0), and the output of the encoder 6 ′ is (a00, a01, a1) from Table 2.
0, a11, a20, a21) = (0, 1, 0, 0,
1, 0).

In this case, the parity bits are as shown in FIG.
The data calculated by the circuit having the configuration shown in FIG. 3 is written, and (a30, a31, a40, a41) = (1, 1,.
1, 1).

The outputs of the encoder 6 '(a00, a01,
a10, a11, a20, a21, a30, a31, a
40, a41), there is no error in the output (a00'-a21 ') of the syndrome decoder 8 and the outputs (D00, D01, D0) of the correction circuit 9 are all "0".
10, D11, D20, D21) are (a00, a0
1, a10, a11, a20, a21), (0,
1, 0, 0, 1, 0).

Here, one of the memory cells is defective and D0
An error occurs in the multi-valued cells 0 and D01, and O
If N, the outputs of the latch circuits 3, 4, and 5 are (L0
1, L02, L03) = (0, 0, 0), and the output of the encoder 6 'is (a00, a01, a10, a1).
1, a20, a21) = (0, 0, 0, 0, 1, 0).

At this time, the output of the syndrome decoder 8 is (a00 ', a01', a10 ', a11', a2
0 ′, a21 ′) = (0, 1, 0, 0, 0, 0), a01 is corrected by the correction circuit 9, and its output (6
(Bit data) is (D00, D01, D10, D11,
D20, D21) = (0, 1, 0, 0, 1, 0).

As another example, if one of the memory cells is defective and an error occurs in the multi-valued cell 1 of D00 and D01 and the gate is turned on by the gate voltage, the outputs of the latches 3, 4, and 5 become:
(L01, L02, L03) = (1, 1, 0),
The output of the encoder 6 'is (a00, a01, a10,
a11, a20, a21) = (1, 0, 0, 0, 1,
0).

At this time, the output of the syndrome decoder 8 is (a00 ', a01', a10 ', a11', a2
0 ′, a21 ′) = (0, 0, 0, 1, 0, 0), a11 is erroneously corrected by the correction circuit 9, and its output is (D00, D01, D10, D11, D20, D2).
1) = (1, 0, 0, 1, 1, 0).

[0024]

As described above, in the conventional error correction of a multi-level cell, when the cell is defective and the gate voltage that is turned on is shifted by one, that is, when the cell transits to an adjacent state, In some cases, error correction cannot be performed.

In an actual multi-level cell, when a cell becomes defective, there are relatively many defects in which the gate voltage at which the cell is turned on is shifted by one. Therefore, it is desired to realize a system capable of correcting all of the defects of this type.

Accordingly, the present invention has been made based on the recognition of the above problems, and an object of the present invention is to provide a multi-valued cell ECC circuit capable of correcting more error patterns by devising an encoder. is there.

[0027]

In order to achieve the above object, the present invention provides a memory cell for storing multi-value information (referred to as a "multi-value cell") and a memory cell connected to a bit line of the multi-value cell. A plurality of latch circuits connected to the outputs of the sense amplifiers, an encoder that receives the outputs of the plurality of latch circuits as inputs, a syndrome calculation circuit that receives the output of the encoder as inputs, and enables 1-bit error correction, A multi-valued cell ECC circuit comprising: a syndrome decoder that receives an output of a syndrome calculation circuit as an input; and a correction circuit that receives an output of the encoder and the syndrome decoder as an input and corrects an error. A plurality of output data to be encoded according to the threshold voltage level of The difference of data in de plurality of output data, which are configured such that only one bit.

In the present invention, a cell for storing a parity bit is composed of a multi-level cell.

[0029]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, referring to FIG. 1, in a semiconductor integrated circuit having a memory cell (multi-level cell) for storing multi-level information, a sense amplifier is connected to a bit line of a multi-level cell (1). (2) is connected, a plurality of latch circuits (3, 4, 5) are connected to the output of the sense amplifier (2), and the output of each latch circuit is input to the encoder (6). The output of (6) is input to a syndrome calculation circuit (7) of an ECC circuit capable of correcting a 1-bit error and a correction circuit (9) for correcting an error. The output of the syndrome calculation circuit (7) is The syndrome decoder (8) is connected. The output of the syndrome decoder (8) is input to a correction circuit (9) and has a function of correcting the output of the encoder (6).
Corresponds to the level of the gate voltage applied to the multi-valued cell,
When the data sets of the encoder output are compared with the above data sets in ascending order of the gate voltage level, the encoding result is set so that the bit difference of the data sets is only one bit (for example, see Table 1 below). It is configured to output.

[0030]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[First Embodiment] FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a schematic configuration of a circuit. That is, four-level (two-bit) information is stored in one memorial, and six bits are output by using a one-bit error correction coding technique.

Referring to FIG. 1, a first embodiment of the present invention is a quaternary multi-level cell unit 1, a sense amplifier 2 connected to its bit line, and an output of the sense amplifier 2. First to third latch circuits 3, 4, and 5 (also referred to as latches 1, 2, and 3), an encoder 6 to which the outputs of these latches 3, 4, and 5 are input, and It comprises a syndrome calculation circuit 7 for constituting an ECC circuit, a syndrome decoder 8, and a correction circuit 9 for correcting the output of the encoder 6.

The multi-valued cell section 1, encoder 6, syndrome calculation circuit 7, syndrome decoder 8, and correction circuit 9 are circuits as shown in FIGS. 2, 3, 4, 5, and 6, respectively. Configuration. That is, the multi-level cell unit 1, the syndrome calculation circuit 7, the syndrome decoder 8, and the correction circuit 9 have the same circuit configuration as that described in the related art.

A00 and a0 output from the encoder 6
1, a10 and a11, a20 and a21 are 1
It is a set of 2-bit information that can be extracted from the memory cell,
a30 and a31 and a40 and a41 are sets of 2-bit information that can be extracted from one parity cell (redundant cell). The parity cell is a multi-valued cell, and stores 4-bit parity in two cells.

(A00 ', a01', a10 ', a1
1 ', a20', a21 ') are the outputs of the syndrome decoder 8.

(D00, D01, D10, D11, D2
The 6-bit data (0, D21) is the output of the correction circuit 9.

Hereinafter, points of the first embodiment of the present invention which are different from the conventional configuration shown in FIG. 11 will be described.

In the configuration shown in FIG. 11, the correspondence between the latch circuit output and the encoder output is as shown in the truth table of Table 2, whereas in the first embodiment of the present invention, , As shown in Table 1. This is because the encoder is set so that, when the states that the cells of the multilevel cell can take are arranged, the output bit difference between adjacent states is only one bit.

The operation of the first embodiment of the present invention will be described.

A voltage as shown in FIG. 7 is applied to the gate of the cell transistor in the multi-level cell section 1. Then, as shown in Table 1, the outputs of the three latch circuits are set according to the state of the gate voltage in FIG. 7 in which the current flows in the cell (the cell transistor is turned on). For example,
When a current flows through a cell (ON) while the gate voltage is high, the outputs of the three latch circuits that receive the output of the sense amplifier connected to the cell are (Ln1, Ln2, Ln).
3) = (1, 0, 0) (n = 0, 1, 2). The outputs (Ln1, Ln2, Ln3) of this latch circuit are input to the encoder 6, and the outputs are encoded as shown in Table 1 according to the states of the three latch circuits. This means that two bits of information have been extracted from one cell.

Two-bit information (for example, a00 and a01) extracted from one memory cell is input to the syndrome calculation circuit 7. The syndrome is calculated by the syndrome calculation circuit 7 and the output is input to the syndrome decoder 8. The output of the syndrome decoder 8 (a00'-
In a21 '), an output corresponding to an erroneous bit becomes "1".

The output (a00 ') of the syndrome decoder 8
−a21 ′) is input to the correction circuit 9. Correction circuit 9
Consists of an XOR circuit as shown in FIG.
-A21 '), if there is one bit, (a00-a
21) Invert the data to correct the error.

Next, as in the conventional circuit shown in FIG. 11, for example, (cells of D00 and D01, cells of D10 and D11, cells of D20 and D21) = (ON at gate voltage, gate voltage ON at gate voltage ON
Consider the case

At this time, the outputs of the latch circuits (three are set as a set) connected to each sense amplifier are (L
01, L02, L03) = (1, 0, 0), (L11,
L12, L13) = (0, 0, 0), (L21, L2
2, L23) = (1, 1, 0), and the output of the encoder 6 is (a00, a01, a10, a1) from Table 1.
1, a20, a21) = (0, 1, 0, 0, 1, 1).

In this case, the data calculated by the circuit shown in FIG. 8 is written in the parity bit, and (a3
0, a31, a40, a41) = (1, 1, 0, 0). The output of the encoder 6 (a00, a01, a10,
a11, a20, a21, a30, a31, a40, a
When there is no error in the data of 41), the outputs (a00'-a21 ') of the syndrome decoder 8 are all "0" and the outputs (D00, D01, D10, D1) of the correction circuit 9 are obtained.
1, D20, D21) are (a00, a01, a10,
a11, a20, a21) (0, 1, 0, 0,
1, 1).

Here, one of the memory cells is defective and (D
When an error occurs in the cell 1 storing (00 and D01) and it is turned on by the gate voltage, the outputs of the latch circuits 3, 4, and 5 are (L01, L02, L03) = (0, 0, 0). , The output of the encoder 6 is (a00, a01, a1
0, a11, a20, a21) = (0, 0, 0, 0,
1, 1).

At this time, the outputs of the syndrome decoder 8 are (a00 ', a01', a10 ', a11', a2
0 ', a21') = (0, 1, 0, 0, 0, 0), a01 is corrected by the correction circuit 9, and its output is (D00, D01, D10, D11, D20, D21).
= (0,1,0,0,1,1).

As another example, when one of the memory cells is defective and an error occurs in the cell 1 of D00 and D01 and the memory cell is turned on at the gate voltage 3, the outputs of the latch circuits 3, 4, and 5 become (L01 , L02, L03) = (1, 1, 0), and the output of the encoder 6 is (a00, a01, a1).
0, a11, a20, a21) = (1, 1, 0, 0,
1, 1).

At this time, the outputs of the syndrome decoder 8 are (a00 ', a01', a10 ', a11', a2
0 ′, a21 ′) = (1, 0, 0, 0, 0, 0,), which is corrected by the correction circuit 9, and its output is (D00,
D01, D10, D11, D20, D21) = (0,
1, 0, 0, 1, 1).

In the case of this error, the error cannot be corrected by the conventional ECC circuit shown in FIG. 11, but can be corrected by the first embodiment of the present invention.

That is, in the conventional error correction of a multi-level cell, when the cell is defective and the gate voltage which is turned on is shifted by one, that is, when the state shifts to an adjacent state, error correction cannot be performed. In the first embodiment of the present invention, any defect from a state that a cell can take to an adjacent state can be corrected.

In the first embodiment of the present invention, the method of performing reading by changing the gate voltage of the multi-valued cell has been described.
A method in which a plurality of reference amplifiers are provided and sensing is performed based on the amount of current can be applied.

[Second Embodiment] FIG. 9 is a diagram showing the configuration of a second embodiment of the present invention, and is an ECC for an 8-level multilevel cell.
FIG. 2 is a diagram illustrating a schematic configuration of a circuit. In the second embodiment of the present invention, an eight-valued multivalued memory cell 1, a sense amplifier 2 connected to its bit line, a plurality of latch circuits 3 connected to the output of the sense amplifier 2, An encoder 6 connected to the latch circuit 3 and a syndrome calculation circuit 7 for forming an ECC circuit from the output of the encoder 6
, A syndrome decoder 8, and a correction circuit 9 for correcting the output of the encoder 6.

The main differences between the second embodiment of the present invention and the first embodiment will be described below.

In the first embodiment shown in FIG. 1, the voltage shown in FIG. 7 is applied to the gates of the cells of the quaternary multi-level cell unit 1, whereas the second embodiment of the present invention In FIG. 10, seven different voltages shown in FIG. Thus, in the second embodiment of the present invention, the number of required latch circuits is seven for each sense amplifier. Therefore, the encoder 6
The circuit configuration is such that seven bits of the output (L01-L07) of the latch circuit are input and three bits (a00, a01, a02) are output.

Here, assuming that the encoding method of the encoding 6 is as shown in Table 3, when the possible states of the multi-valued cells are arranged, the output bit difference between the adjacent states is all 1 Even if there is only a bit, even if the state changes from an originally available state to an adjacent state due to a defective cell, it can be corrected by the 1-bit correction ECC circuit.

[0057]

[Table 1]

[0058]

[Table 2]

[0059]

[Table 3]

[0060]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that, in a semiconductor integrated circuit that stores multi-valued information in one memory cell, that is, in a semiconductor integrated circuit using a multi-valued cell, the possible states of the multi-valued cell are arranged. In this case, since the encoder sets the output bit difference from the adjacent state to only one bit, any defect in the cell to the adjacent state can be corrected by the 1-bit correction ECC circuit. That is, the capability of error correction of the value cell is improved.

As a second effect of the present invention, ECC
Parity bits (check bits) are required to form a circuit, but it is possible to suppress an increase in chip area by configuring the cells for storing the parity bits with multi-level cells. That is.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a configuration of a multi-level cell unit.

FIG. 3 is a diagram illustrating a circuit configuration of an encoder according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a circuit configuration of a syndrome calculation circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a syndrome decoder according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a circuit configuration of a correction circuit according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a voltage applied to the gate of the multi-level cell in the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a parity calculation circuit.

FIG. 9 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 10 is a diagram showing a voltage applied to the gate of the multi-level cell according to the second embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional multi-level cell ECC circuit.

FIG. 12 is a diagram showing a configuration of a conventional encoder.

FIG. 13 is a diagram showing a voltage applied to a gate of a multi-level cell in a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multi-valued cell part 2 Sense amplifier 3, 4, 5 Latch circuit 6 Encoder 7 Syndrome calculation circuit 8 Syndrome decoder 9 Correction circuit

Claims (4)

[Claims] 1. A memory cell for storing multi-value information (referred to as “multi-value cell”), a plurality of latch circuits connected to an output of a sense amplifier connected to a bit line of the multi-value cell, An encoder having inputs of outputs of a plurality of latch circuits, a syndrome calculation circuit having an output of the encoder as an input, and enabling 1-bit error correction; a syndrome decoder having an output of the syndrome calculation circuit as an input; A correction circuit that receives an output as an input and corrects an error based on an output of the syndrome decoder; and a multi-level cell ECC circuit, wherein the encoder encodes according to a threshold voltage level of the multi-level cell. A plurality of output data encoded for the multilevel cell between adjacent threshold voltage levels. The ECC circuit for multi-valued cells, characterized in that the difference in data is only one bit. 2. The ECC circuit for a multi-level cell according to claim 1, wherein the cell for storing the parity bit comprises a multi-level cell. 3. A multi-level cell for storing data in multi-level, a multi-level cell for storing parity bits of the data in multi-level, and an output of a sense amplifier connected to a bit line of the multi-level cell. A plurality of latch circuits obtained, an encoder receiving inputs of the outputs of the plurality of latch circuits, a syndrome calculation circuit receiving the output of the encoder as input, and enabling 1-bit error correction, and receiving an output of the syndrome calculation circuit. And a correction circuit that corrects an error of the output of the encoder based on the output of the syndrome decoder, wherein the encoder responds to a voltage or current level applied for reading the multi-level cell. When comparing sets of encoder output data in ascending order of the applied voltage or current level, Bit difference output data between Ukumi is configured to output the encoded results so that only one bit, ECC circuit multilevel cell, characterized in that. 4. A semiconductor integrated circuit in which a memory cell array includes a multi-valued cell, comprising the multi-valued cell ECC circuit according to claim 1.