KR100291663B1 - How to check data transmission between ATM layer and physical layer - Google Patents
How to check data transmission between ATM layer and physical layer Download PDFInfo
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- KR100291663B1 KR100291663B1 KR1019980043206A KR19980043206A KR100291663B1 KR 100291663 B1 KR100291663 B1 KR 100291663B1 KR 1019980043206 A KR1019980043206 A KR 1019980043206A KR 19980043206 A KR19980043206 A KR 19980043206A KR 100291663 B1 KR100291663 B1 KR 100291663B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
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Abstract
본 발명은 인터페이스에서 셀 송신시 발광소자 구동방법에 있어서, 특히 UTOPIA 레벨 2 인터페이스에서 셀 송신시 발광소자 구동방법에 관한 것으로,하나의 셀이 ATM Layer에서 PHY Layer로 전송될 때 이를 표시하는 LED를 구동하기 위해 PHY Layer Decoder부와 LED 제어부를 사용하고,The present invention relates to a method of driving a light emitting device when transmitting a cell at an interface, and more particularly, to a method of driving a light emitting device when transmitting a cell at a UTOPIA level 2 interface. PHY Layer Decoder and LED controller are used to drive
입력 신호로는 Transmit interface signal 중 TxSOC 신호와 TxAddr[4:0] 신호를 사용하며,As input signal, TxSOC signal and TxAddr [4: 0] signal of Transmit interface signal are used.
PHY Layer Decoder부는 TxAddr[4:0] 신호를 사용하여 현재 ATM Layer에서 선택된 Port를 해독하고, 그 결과(선택된 PHY Port)를 LED 제어부로 보내는 기능을 수행하고,The PHY Layer Decoder decodes the selected port in the current ATM Layer using the TxAddr [4: 0] signal, and sends the result (selected PHY port) to the LED controller.
LED 제어부에서는 해독된 결과와 TxSOC 신호를 사용하여 실제 하나의 셀이 전송되고 있음을 LED로 표시하기 위한 제어신호를 생성하는 것이 특징이다.The LED controller is characterized by generating a control signal to indicate that the actual cell is being transmitted using the LED using the decoded result and the TxSOC signal.
Description
본 발명은 인터페이스에서 셀 송신시 발광소자 구동방법에 관한 것으로, 특히 UTOPIA 레벨 2 인터페이스에서 셀 송신시 발광소자 구동방법에 관한 것인바, 여기서 UTOPIA(Universal Test & Operations PHY Interface for ATM) 레벨 2 인터페이스란 ATM Forum Technical Committee에서 정한 데이터 패스 인터페이스 스팩(data path interface spec.)으로써, 1개의 ATM Layer에 다수의 물리적 계층(Physical Layer)을 연결하여 데이터(ATM셀)를 전송하기 위한 시그널 인터페이스 스팩(signal interface spec)이다.The present invention relates to a method of driving a light emitting device when transmitting a cell in an interface, and more particularly, to a method of driving a light emitting device when transmitting a cell in a UTOPIA level 2 interface, wherein the UTOPIA (Universal Test & Operations PHY Interface for ATM) level 2 interface A data path interface specification defined by the ATM Forum Technical Committee. A signal interface specification for transmitting data (ATM cells) by connecting multiple physical layers to one ATM layer. spec).
본 발명은 UTOPIA Level 2 인터페이스에서 하나의 셀을 송신시, 셀의 송신 상태를 알려주는 송신 LED를 구동하는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of driving a transmission LED indicating a transmission state of a cell when transmitting one cell in a UTOPIA Level 2 interface.
도 1, 2는 본 발명의 구성 블록도.1 and 2 are block diagrams of the present invention.
도 3은 UTOPIA Level 2 transmit interface 타이밍도.3 is a UTOPIA Level 2 transmit interface timing diagram.
이하에서 도면을 참조로 상세히 설명하면 다음과 같다.Hereinafter, with reference to the drawings in detail as follows.
먼저, ATM Layer부와 PHY Layer부 사이를 연결하는 UTOPIA Level 2 interface signal은 다음과 같다.First, the UTOPIA Level 2 interface signal connecting the ATM layer unit and the PHY layer unit is as follows.
1. 송신 인터페이스 시그널(Transmit interface signal(ATM Layer＝＞ATM Layer로 셀 전송)1.Transmit interface signal (transmit cell to ATM Layer => ATM Layer)
-Txclk: ATM 셀 데이터를 PHY Layer로 쓰기 위한 reference Clock 신호.Txclk: A reference clock signal for writing ATM cell data to the PHY Layer.
-TxAddr[4:0]: 특정 PHY Layer를 선택 및 폴링(polling) 하기 위한 5비트 어드레스 버스 신호.TxAddr [4: 0]: 5-bit address bus signal for selecting and polling a specific PHY Layer.
-Txclav: PHY Layer에서 하나의 ATM셀을 수신할 수 있는 상태임을 나타내는 available 신호.-Txclav: available signal indicating that one ATM cell can be received by the PHY Layer.
-TxEnb: PHY Layer로 셀 전송시 transmit enable을 나타내는 신호.TxEnb: A signal indicating transmit enable when transmitting a cell to a PHY layer.
-TxData: 전송되는 셀 데이터 신호.TxData: Cell data signal to be transmitted.
-TxSOC: 전송되는 셀의 시작을 나타내는 신호.TxSOC: signal indicating the start of a cell to be transmitted.
2. 수신 인터페이스 시그널(Receive Interface signal(PHY Layer＝＞ATM Layer로 셀 전송)2. Receive Interface signal (cell transmission to PHY Layer => ATM Layer)
-Rxclk: ATM 셀 데이터를 PHY Layer에서 읽기 위한 reference Clock 신호.Rxclk: A reference clock signal for reading ATM cell data at the PHY layer.
-RxAddr[4:0]: 특정 PHY Layer를 선택 및 폴링(polling) 하기 위한 5비트 어드레스 버스 신호.RxAddr [4: 0]: 5-bit address bus signal for selecting and polling a specific PHY Layer.
-Rxclav: PHY Layer에서 하나의 ATM셀을 보낼수 있는 상태임을 나타내는 available 신호.Rxclav: available signal indicating that one ATM cell can be sent in the PHY Layer.
-RxEnb: PHY Layer로 셀 수신시 receive enable을 나타내는 신호.-RxEnb: Signal indicating receive enable when receiving cell with PHY Layer.
-RxData: 수신되는 셀 데이터 신호.RxData: Received cell data signal.
-RxSOC: 수신되는 셀의 시작을 나타내는 신호.RxSOC: Signal indicating the start of a cell to be received.
* 이때 TxAddr[4:0] = 0X1F 및 RxAddr[4:0]=0X1F는 PHY Layer address로 할당하지 않으며 따라서 최대 연결 가능 PHY Layer는 31개이다.* At this time, TxAddr [4: 0] = 0X1F and RxAddr [4: 0] = 0X1F are not assigned as PHY Layer addresses, so the maximum connectable PHY Layer is 31.
1개의 ATM Layer에 다수의 PHY Layer가 공통의 데이터 라인을 사용하므로 셀이 전송될 경우 어느 PHY Layer로 셀이 전송되는지를 찾아내어 특정 포트의 LED를 구동시켜야 한다.Since multiple PHY Layers use a common data line in one ATM Layer, when a cell is transmitted, it is necessary to find out which PHY Layer the cell is transmitted to drive LEDs of a specific port.
이를 위해 본 발명에서는 UTOPIA 레벨 2에 정의된 신호인 TxSOC 신호와 TxAddr[4:0] 신호를 사용하여 그 기능을 구현하였다.To this end, the present invention uses the TxSOC signal and the TxAddr [4: 0] signal defined in the UTOPIA level 2 to implement the function.
도 1, 2는 본 발명에 대한 구성도이다.1 and 2 is a configuration diagram for the present invention.
본 발명에서는 하나의 셀이 ATM Layer에서 PHY Layer로 전송될 때 이를 표시하는 LED를 구동하기 위해 PHY Layer Decoder부와 LED 제어부를 사용하고, 입력 신호로는 Transmit interface signal 중 TxSOC 신호와 TxAddr[4:0] 신호를 사용한다.In the present invention, a PHY Layer Decoder unit and an LED control unit are used to drive an LED indicating when a cell is transmitted from an ATM layer to a PHY layer. As an input signal, a TxSOC signal and a TxAddr [4: 0] signal.
PHY Layer Decoder부는 TxAddr[4:0] 신호를 사용하여 현재 ATM Layer에서 선택된 Port를 해독하고, 그 결과(선택된 PHY Port)를 LED 제어부로 보내는 기능을 수행한다.The PHY Layer Decoder decodes the currently selected port in the ATM layer using the TxAddr [4: 0] signal, and sends the result (the selected PHY port) to the LED controller.
LED 제어부에서는 해독된 결과와 TxSOC 신호를 사용하여 실제 하나의 셀이 전송되고 있음을 LED로 표시하기 위한 제어신호를 생성한다.The LED controller generates a control signal for displaying the LED indicating that the actual cell is being transmitted using the decoded result and the TxSOC signal.
ATM Layer에서 TxAddr[4:0]신호를 사용하여 특정 PHY Layer로 셀을 전송한다.In the ATM layer, a cell is transmitted to a specific PHY layer using a TxAddr [4: 0] signal.
TxAddr[4:0] 신호는 address bus 신호로써 각 PHY Layer당 고유의 address 번지를 사용한다.TxAddr [4: 0] is an address bus signal that uses a unique address for each PHY layer.
도 3의 UTOPIA Level 2 transmit interface timing도를 이용하여 작동을 설명한다.The operation will be described using the UTOPIA Level 2 transmit interface timing diagram of FIG. 3.
먼저 ATM Layer에서 PHY Layer(0)으로 전송할 셀이 있으면 도 3과 같이 TxClk(1)에서 PHY Layer(0)에 해당하는 주소인 TxAddr[4:0]='0000'을 내보내고 TxClk(2)에서 PHY Layer(0)이 셀을 받을 수 있는 상태인지를 TxClav 신호로 확인한다.First, if there is a cell to be transmitted from the ATM layer to the PHY Layer (0), TxClk (1) exports TxAddr [4: 0] = '0000', which is the address corresponding to the PHY Layer (0), as shown in FIG. Whether the PHY Layer (0) can receive the cell is confirmed by the TxClav signal.
만약 Txclav 신호가 하이이면 PHY Layer(0)이 셀을 받을 수 있음을 나타내므로 TxClk(3)에서 한 번 더 TxAddr[4:0]'0000'를 내보내고 TxClk(4)부터 셀 전송을 시작한다.If the Txclav signal is high, it indicates that the PHY Layer (0) can receive the cell. Therefore, TxClk (3) sends TxAddr [4: 0] '0000' once more and starts transmitting the cell from TxClk (4).
TxClk의 (1) 및 (3)에서 TxAddr[4:0]='0000'(즉 PHY(0)으로 셀을 전송)이면 PHY Layer Decoder부에서는 TxAddr[4:0]신호를 사용하여 Select-port(0) 신호를 생성한다.In TxClk (1) and (3), if TxAddr [4: 0] = '0000' (i.e., cell is transmitted to PHY (0)), the PHY Layer Decoder uses the TxAddr [4: 0] signal to select-port. (0) Generate a signal.
LED 제어부에서는 생성된 select-port(0) 신호와 TxSOC 신호를 사용하여 공통으로 하이(high)인 부분을 추출하여 LED-Trigger(0) 신호를 생성한다.The LED controller generates a LED-Trigger (0) signal by extracting a part that is commonly high by using the generated select-port (0) signal and the TxSOC signal.
생성된 LED-Trigger 신호를 이용하여 LED-ON(0) 신호를 만들어 내며, 이 신호는 하나의 ATM 셀이 전송될 동안 TxLED(0)를 구동한다.The generated LED-Trigger signal is used to generate the LED-ON (0) signal, which drives TxLED (0) while one ATM cell is being transmitted.
상술한 바와같이 본 발명은 UTOPIA Level 2 인터페이스에서 하나의 셀을 송신시, 셀의 송신 상태를 알려주는 송신 LED를 구동할 수 있는 효과가 있다.As described above, according to the present invention, when one cell is transmitted in the UTOPIA Level 2 interface, a transmission LED indicating a transmission state of the cell can be driven.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980043206A KR100291663B1 (en) | 1998-10-15 | 1998-10-15 | How to check data transmission between ATM layer and physical layer |
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| KR1019980043206A KR100291663B1 (en) | 1998-10-15 | 1998-10-15 | How to check data transmission between ATM layer and physical layer |
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| KR20000025909A KR20000025909A (en) | 2000-05-06 |
| KR100291663B1 true KR100291663B1 (en) | 2001-07-12 |
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