KR100286748B1 - Channel tester between lower control system and device in exchange system - Google Patents

Abstract

The present invention provides a channel test apparatus between a lower control system and a device provided in an exchange system. The apparatus according to the present invention includes a lower control system including a loopback test apparatus in each of channel distributors existing between the lower control system and the device. It is configured to test channels on the bus to be installed between devices. This allows testing of the channel on the bus between the lower control system and the device even when the device is not connected.

Description

Channel tester between lower control system and device in exchange system

The present invention relates to a channel test apparatus between a lower control system and a device in an exchange system, and more particularly, to a channel test apparatus capable of testing a channel state on a bus to be installed between a lower control system and a device without a device being connected. .

1 is a diagram illustrating a connection configuration between a lower control system and a device in an exchange system using a heat bus (HIT_BUS (HDLC protocol Interface Telephony Device Bus)) consisting of 64 HDLC (High Data Link Control (HDLC) channels). The Telephony Processor (hereinafter, referred to as TP) 110 as a control system allows PCM (Pulse Code Modulation) data to be transmitted / received in units of 16 HDLC channels continuously through the heat bus interface 111 provided therein. The first to fourth channel distributors 121, 122, 123, and 124 are connected to the first and fourth channel dividers 121, 122, 123, and 124, respectively, and the channel distributors 121, 122, 123, and 124 connect 16 consecutive channels to corresponding device groups 130, 140, 150, and 160. Distribute considering the conditions of the device provided in the). For example, if the devices included in the device groups 130, 140, 150, and 160 are all operated by 2 byte units, the device groups 130, 140, 150, and 160 are provided with 16 devices, and channel distributors. Reference numerals 121, 122, 123, and 124 divide 16 consecutive channels by 1 channel and allocate them to the device.

The existing test method for all or arbitrary channels on the bus installed between the lower control system and the device having such a connection structure is loopback through the corresponding channel distributors 121, 122, 123, and 124 in the TP 110. As it is implemented in a loopback method, in order to test all or arbitrary channels on the bus, as shown in FIG. 1, only a device is connected to all or corresponding channels.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned limitations. The present invention provides a channel test apparatus between a lower control system and a device in which a channel on a bus installed between the lower control system and the device can be tested in a state where the device is not connected. The purpose is to provide.

In order to achieve the above object, an apparatus according to the present invention performs a channel test on a bus installed and operated between a lower control system provided in an exchange system and a device by comparing a loopback signal corresponding to a signal transmitted from the lower control system. An apparatus comprising: a channel detector for detecting a channel to be tested by analyzing frame synchronization signals and transmission data provided from a lower control system; A storage unit storing transmission data carried in the detected channel when a channel desired for testing is detected by the channel detector; The loopback signal is provided as a loopback signal by loading the data stored in the storage unit into the same channel as the detected channel after a predetermined multiple frame period elapses by using a signal delaying the frame synchronization signal for a predetermined multiple frame period and the detected channel information. It characterized in that it comprises a signal providing unit.

1 is a diagram illustrating a general connection between a lower control system and a device in an exchange system;

2 is a schematic block diagram of an exchange system having a channel test apparatus between a lower control system and a device according to the present invention;

3 is a detailed view of the loopback test apparatus shown in FIG. 2.

<Explanation of symbols for main parts of drawing>

210: Telephony processor (TP) 211: Heat bus interface unit (HIT_BUS I / F)

220, 230, 230, 250: first to fourth channel distributor

221, 231, 241, 251: loopback tester

310: channel detector 311, 332: counter

312: frame start information (SOF) detector 313: channel detector

320: data register 330: loopback signal provider

331: Delay 333: Channel information insertion controller

334 loopback signal generator

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic block diagram of an exchange system including a channel test apparatus between a lower control system and a device according to the present invention, wherein a lower control system and a device include a heat bus (HIT_BUS (HDLC protocol Interface Telephony Device Bus) (HIT_BUS)). It is connected to HIT_BUS).

Accordingly, the apparatus shown in FIG. 2 is a 16 HDLC (Telephony Processor, hereinafter abbreviated as TP) 210 which is a lower control system having the HIT_BUS interface unit 211 and TP 210 which are continuous from 16 High Data Link Control. (Hereinafter abbreviated as HDLC) has a function of distributing channel information transmitted in units of channels in consideration of a device to be connected in the same manner as before, and loopback test apparatuses 221, 231, respectively, for testing a channel on a bus according to the present invention. And first through fourth channel distributors 220 through 250 with 241 and 251.

FIG. 3 is a detailed view of each loopback test apparatus 221, 231, 241, and 251 illustrated in FIG. 2, wherein one channel for testing among 16 HDLC channels transmitted from the TP 210 through the HIT_BUS interface 211 is illustrated. A loop detection signal corresponding to a signal provided from the TP 210 for the channel detector 310 for detecting a signal, a data register 320 storing data transmitted on a channel to be tested, and data stored in the data register 320. The loopback signal providing unit 330 is provided.

In particular, the channel detector 310 is reset by a frame synchronization signal (also referred to as Frame SYNC, FS) provided from the TP 210 through a transmission path (not shown) provided separately from the HIT_BUS and is different from the existing HIT_BUS. A counter 311 that counts the transmission clock signal TX_Clock output from the TP 210 through a transmission path (not shown) of the HDLC protocol, and the transmission data TX_Data provided from the TP 210 through HIT_BUS. The SOF detector 312 and the SOF detector 312 that detect frame start information (hereinafter, referred to as SOF) detect the count value of the counter 311 at the point of time when the SOF is detected as a desired channel. And a channel detector 313 for controlling the input enable state IE of the data register 320 at the time of channel detection.

The loopback signal providing unit 330 delays the frame synchronization signal provided from the TP 210 for one frame period through a separate transmission path (not shown) from the HIT_BUS for one frame period and the delayer 331. A counter 332 and a channel detector 313 which are reset by a frame synchronization signal provided with a delay at a count and count the received clock signal RX_Clock provided from the TP 210 through a transmission path (not shown) separate from the HIT_BUS. The channel information insertion controller 333 for controlling the insertion of the channel information stored in the data register 320 according to whether the channel information detected by the reference information matches the count value provided by the counter 332, and the channel information. As controlled by the insertion controller 333 to control the output enable state (OE) of the data register 320, the channel information transmitted from the data register 320 is inserted into the corresponding channel for the test from the TP 210. Generating a loop-back signal corresponding to the transmitted data was sent consists of a loop-back signal generator 334. The generated loopback signal is provided to the received data RX_Data of the TP 210 via the HIT_BUS.

The apparatus according to the present invention thus configured is operated as follows.

The information of 16 channels which is continuous through the HIT_BUS interface unit 211 of the TP 210 is respectively divided into a first channel divider 220, a second channel divider 230, a third channel divider 240, and a fourth channel divider. When distributed and transmitted to 250, the loop test apparatus 221, 231, 241, and 251 provided in the first to fourth channel distributors 220 to 250 are provided to perform a channel test.

For example, when the first 16 channel information is sent to the first channel distributor 220, the first 16 channel information is applied to the channel detector 310 in the loopback test apparatus 221. Since the channel detector 310 corresponds to the data TX_Data transmitted through the HIT_BUS, the channel detector 310 transmits the transmitted channel information to the SOF detector 312 and provides a frame provided from the TP 210 through a separate transmission path (not shown). The synchronization signal and the sending clock signal are applied to the counter 311.

The counter 311 is reset by the applied frame synchronizing signal to count the transmission clock signal, and transmits the count value to the channel detector 313 whenever the count value is updated. The SOF detector 312 detects the presence of the SOF regardless of the channel when channel information consisting of 16-bit HDLC serial data is received. Since the SOF is generally provided as a low level signal, the SOF detector 312 checks whether a low level signal exists among the received channel information, and if the low level signal is detected, determines that the SOF signal has been detected and thus detects the channel detector 313. ) To notify the detection of the SOF signal.

The channel detector 313 detects the count value provided from the counter 311 at the time when the SOF detection is notified from the SOF detector 312 as the channel information desired for the test. At the same time as the channel information is detected, the data register 320 is set to the input enable state, and the detected channel information is transmitted to the loopback signal providing unit 330.

The data register 320 is set to a state capable of storing an input signal by an input enable signal provided from the channel detector 313 and sequentially stores the data TX_Data transmitted from the TP 210 through the HIT-BUS. . The storage capacity of the data register 320 is set to 16 bits to store data corresponding to one channel. Therefore, if 16-bit data is stored after the input enable state is set, the save operation for the input data is stopped.

Meanwhile, when the same frame synchronizing signal as that provided to the channel detector 310 is applied, the loopback signal providing unit 330 provides the delay unit 331. The delay unit 331 is operated by setting a delay time so as to delay an applied frame synchronizing signal for one frame period. In this case, the delay time may be set in multiples of one frame period (for example, 2 × 1 frame period). The frame synchronization signal delayed for one frame period by the delayer 331 is provided to the counter 332 to reset the counter 332.

Accordingly, the counter 332 counts the received clock signal RX_Clock provided from the TP 210 through a separate transmission path (not shown). The counted result is provided to the channel information insertion controller 333 whenever the count value is updated, similar to the counter 311 described above.

The channel information insertion controller 333 compares the detected channel information provided from the channel detector 313 with the count value provided from the counter 332. As a result of the comparison, the loopback signal generator 334 is requested to insert channel information if there is a match.

When the loopback signal generator 334 is required to insert the channel information, the loopback signal generator 334 sets the data register 320 to the output enable state, and simultaneously transmits data output serially from the data register 320 at the TP 210 side. Occurs as a loopback signal on the same channel. Therefore, the data stored in the data register 320 is provided as the received data RX_Data of the TP 210 on the same HIT_BUS channel as at the time of transmission.

The TP 210 compares the data (RX-Data) received through the HIT_BUS interface unit 211 with previously transmitted data and checks whether the corresponding channel is normal.

The HIT-BUS channel data applied to the second to fourth channel distributors 230 to 250 is also processed in the same way as the first channel distributor 220 described above.

As described above, the present invention implements a sub-control system provided in the exchange system and a channel on the bus installed between the devices so that the channel divider includes a loopback test apparatus to test the sub-control system and the lower control system even when the device is not connected. All or desired channels on the bus installed between the devices can be tested, which makes the test easier.

Claims (5)

An apparatus for performing a channel test on a bus installed and operated between a lower control system provided in an exchange system and a device by comparing a loopback signal corresponding to a signal transmitted from the lower control system. A channel detector for detecting a channel to be tested by analyzing frame synchronization signals and transmission data provided from the lower control system; A storage unit storing transmission data carried in the detected channel when the channel desired for the test is detected by the channel detector; The data stored in the storage unit is loaded on the same channel as the detected channel after the predetermined multiple frame period has elapsed by using the signal delaying the frame synchronization signal for a predetermined multiple of the frame period and the detected channel information. An apparatus for testing a channel between a lower control system and a device in a switching system comprising a loopback signal providing unit for providing a loopback signal. The apparatus of claim 1, wherein the channel detector detects a channel carrying frame start information (SOF) in the transmission data as a desired channel for the test. 3. The apparatus of claim 1 or 2, wherein the channel detector comprises: a counter reset by the frame synchronization signal and counting a transmission clock signal provided from the lower control system; A first detector for detecting frame start information of the transmission data; And a second detector configured to detect the count value of the counter as a desired channel and notify the storage unit of the channel detection status when the first detector detects the frame start information. Channel tester between lower control system and device in system. The apparatus of claim 3, wherein the loopback signal providing unit comprises: a delayer delaying the frame synchronization signal for the predetermined multiple frame periods; a reset provided by a delayed frame synchronization signal output from the delayer and received from the lower control system A counter for counting a clock signal; A controller for controlling whether to insert the channel information by comparing the channel information detected by the second detector with a counter value of the counter; And a loopback generator which is controlled by the controller and reads data stored in the storage to generate the loopback signal. 2. The system of claim 1, wherein the bus comprises a first predetermined number of channels and is operated by separating the first predetermined number of channels into a second predetermined number of consecutive channels. When the channel distributor is provided, the channel test apparatus is provided in the channel distributor, respectively, and the first predetermined number is equal to or smaller than a predetermined multiple of the second predetermined number. Channel tester between devices.