KR100284402B1 - Arithmetic Unit of AC-3 Audio Decoder - Google Patents

Abstract

The present invention relates to an AC-3 audio decoder. In particular, the present invention simplifies circuit implementation and chip size by sharing a plurality of multipliers, adders, subtractors, and muxes used for arithmetic operations in existing IMDCT algorithms. The present invention relates to an arithmetic arithmetic apparatus of an AC-3 audio decoder which can be reduced in size. A first multiplier multiplying a signal selected by the first multiplexer and a fixed input signal; A second multiplier multiplying a signal selected by the second multiplexer with a fixed input signal; An adder for adding an output signal of the first multiplier and an output signal of the second multiplier; A subtractor for subtracting the output signal of the second multiplier from the output signal of the first multiplier; A third multiplexer for selecting and outputting one of signals output from the adder and the subtractor, respectively; The arithmetic operation unit required for the IMDCT calculation can be reduced by providing a round-off unit that removes the lower bits of data output from the third multiplexer.

Description

Arithmetic Unit of AC-3 Audio Decoder

The present invention relates to an AC-3 audio decoder. In particular, the present invention simplifies circuit implementation and chip size by sharing a plurality of multipliers, adders, subtractors, and muxes used for arithmetic operations in existing IMDCT algorithms. An arithmetic operation unit of an AC-3 audio decoder which has been reduced.

In the above, IMDCT refers to an algorithm for converting a frequency signal into a time signal.

In general, the AC-3 audio decoder is one of the audio compression technologies developed to effectively compress vast amounts of digital audio data.

Use of TDAC-based filter banks to eliminate aliasing that occurs during time-frequency conversion of signals, channel coupling to code amplified signal components between audio channels, and inaudible signal components in human auditory systems Principal compression and psychoacoustic modeling to remove noise caused by the error of the quantized mantissa is a main compression technique of the AC-3 audio decoder.

The various theories used for the compression of audio data are complicated in their mathematical background and therefore require a large number of operations in their implementation.

Therefore, when the AC-3 audio decoding algorithm is configured in hardware, a design structure capable of real-time decoding is essential.

1 is a circuit diagram of a calculation operation unit for IMDCT embedded in a conventional AC-3 audio decoder.

As shown therein, the first arithmetic operation unit 10 comprising two multipliers 11 and 12, a subtractor 13, and a round-off unit 14 for removing the lower bits, and two multipliers 21 ), A second arithmetic operation unit 20 comprising an adder 23 and a round-off unit 24 for removing the lower bits, two multipliers 31, 32, a subtractor 33, and a lower part. A third arithmetic operation unit 30 comprising a round-off unit 34 for removing bits, two multipliers 41 and 42, an adder 43, and a round-off unit 44 for removing the lower bits. It consists of a fourth arithmetic operation unit 40 made.

The IMDCT algorithm using the arithmetic operation device configured as described above is as follows.

First, the IMDCT algorithm is represented by a formula.

N-1

x [n] =-2∑X _D [k] cos ((2∏ / 4N) (2n + 1) (2k + 1) + ∏ / 4 (2k + 1) (1 + α)) [Equation 1]

n = 0

0≤k <N / 2 above

In order to implement IMDCT according to the above equation, Pre-IFFT calculation, comple-IFFT calculation, and Post-IFFT calculation should be performed.

In order to implement the above IMDCT, three IFFT calculations must be performed, and each IFFT calculation includes an arithmetic operation of the following [Equation 2].

Z1 [K] = ((ar * cr)-(ai * ci)) + j ((ai * cr) + (ar * ci))

Z2 [K] = ((ar-1 * cr)-(ai-1 * ci) + j ((ai-1 * cr) + (ar-1 * ci) [Equation 2]

That is, in this equation for separately calculating the imaginary part and the real part, two multipliers, an adder and a subtractor for each part are required as shown in FIG.

Therefore, the IMDCT calculation takes up most of the multiplication, addition, and subtraction operations, so that the unit also increases correspondingly.

In particular, as the number of bits of data increases, the hardware for this also increases exponentially.

Therefore, in the related art, a lot of hardware is required as described above, which causes a problem in that the chip size is increased when designing an ASIC. Furthermore, since many arithmetic operation units are required as described above, there is a problem that the device implementation is complicated.

Accordingly, the present invention has been proposed to solve various problems of the arithmetic operation circuit embedded in the conventional AC-3 audio decoder.

The present invention uses a plurality of multipliers, adders, subtractors, and muxes to be used for arithmetic operations in the implementation of existing IMDCT algorithms, thereby simplifying circuit implementation and reducing chip size. The purpose is to provide a computing device.

The apparatus of the present invention proposed to achieve the above object,

First and second multiplexers for selecting one of four input signals and outputting the selected one;

A first multiplier multiplying an input signal different from the signal selected by the first multiplexer;

A second multiplier for multiplying an input signal different from the signal selected by the second multiplexer;

An adder for adding the output signal of the first multiplier and the output signal of the second multiplier;

A subtractor for subtracting the output signal of the second multiplier from the output signal of the first multiplier;

A third multiplexer for selecting and outputting one of the signals output from the adder and the subtractor, respectively;

And a round-off unit which removes a lower bit of data output from the third multiplexer.

1 is a circuit diagram of an arithmetic operation unit built in a conventional AC-3 audio decoder;

2 is a block diagram of an arithmetic operation unit of the AC-3 audio decoder according to the present invention;

3 is an explanatory diagram for explaining a round-off scheme in the present invention.

<Explanation of symbols for main parts of drawing>

100,110,160: first to third multiplexers

120,130: first and second multipliers

140: The adder

150: subtractor

170: round-off part

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2 is a block diagram of an arithmetic operation unit of an AC-3 audio decoder according to the present invention.

As shown therein, the first and second multiplexers 100 and 110 select one of four input signals ar, ai, ar-1 and ai-1 and output the selected ones; A first multiplier (120) multiplying the signal (A1) selected by the first multiplexer (100) with another input signal (A2); A second multiplier (130) multiplying the signal (A3) selected by the second multiplexer (110) with another input signal (A4); An adder 140 for adding an output signal Temp1 of the first multiplier 120 and an output signal Temp2 of the second multiplier 130; A subtractor (150) for subtracting the output signal (Temp2) of the second multiplier (130) from the output signal (Temp1) of the first multiplier (120); A third multiplexer 160 for selecting and outputting one of the signals ADD1 and SUB1 output from the adder 140 and the subtractor 150, respectively; The round-off unit 170 removes the lower bits of the data output from the third multiplexer 160.

The arithmetic operation unit of the AC-3 audio decoder according to the present invention configured as described above first selects one of four signals (ar, ai, ar-1, ai-1) input from the first multiplexer (100). Selection is made according to s1 and s2, and the second multiplexer 110 also selects one of the four input signals ar, ai, ar-1 and ai-1 according to the selection signals s3 and s4. Done.

The signals A1 and A3 selected as described above are input to the first and second multipliers 120 and 130, respectively, and the fixed signals ci and cr are respectively applied to the first and second multipliers 120 and 130. ) Are input respectively.

Accordingly, the first and second multipliers 120 and 130 may select one of the signals A1 and A3 and the fixed signals A2 and A4 selected by the first and second multiplexers 100 and 110, respectively. Each output will be multiplied.

Herein, the signals input to the first and second multipliers 120 and 130 become 22 bits of fixed fixed point data less than 1, and after the multiplication is performed, the data output from each multiplier is 43 bits of signed data. do.

The data Temp1 and Temp2 respectively output from the two multipliers 120 and 130 are input to the third multiplexer 160 after addition and subtraction are performed in the adder 140 and the subtractor 150, respectively.

Then, the third multiplexer 160 selects and outputs one of the data output from the adder 140 and the subtractor 160 according to the selection signal s5, and the 43-bit data thus selected is round off. It is input to the unit 170.

As shown in FIG. 3, the round off unit 170 removes the lower 21 bits of the 43-bit data (S-bit and 42-bit data) input, and the remaining upper 22 bits (S-bit and 21-bit). Only data) is output as decoded audio data.

As described above, according to the present invention, a plurality of multipliers, subtractors, and adders for IMDCT calculation can be shared with each other to reduce arithmetic units required for arithmetic operations, thereby reducing overall chip size and arithmetic. The reduction in the unit has the advantage that the circuit configuration is also easy.

Claims (1)

An AC-3 audio decoder for decoding coded audio data, First and second multiplexers for selecting one of four input signals and outputting the selected one; A first multiplier multiplying a signal selected by the first multiplexer with a fixed input signal; A second multiplier multiplying a signal selected by the second multiplexer with a fixed input signal; An adder for adding the output signal of the first multiplier and the output signal of the second multiplier; A subtractor for subtracting the output signal of the second multiplier from the output signal of the first multiplier; A third multiplexer for selecting and outputting one of the signals output from the adder and the subtractor, respectively; And a round off unit for removing the lower bits of the data output from the third multiplexer.

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