JPH1198023A - Signal coding and decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by performing a product-sum operation of M and N sample data which are acquired in 1st and 2nd modes respectively and a coefficient data group that shows an impulse response characteristic. SOLUTION: A 1st band dividing filter 101 performs coefficient multiplication and addition of with a signal for a filter degree 48 and 24 a past digital audio signal as one unit and produces subband signals of 22.05 to 11.025 kHz high area and 11.025 to 0 kHz intermediate and low areas. Further, a high area subband which is sampled in 1/2 rate and thinned and an intermediate and low area subband signal are outputted in 22.05 kHz sampling frequency. A 2nd band split filter 102 can switch an effective filter degree to 48 or 24, performs coefficient multiplication and addition with a previous intermediate and low area subband signal of a filter 101 as one unit and generates 11.05 to 5.5125 kHz intermediate area subband signal and 5.5125 to 0 kHz low area subband signal. An output signal S1 of a filter degree switching part 103 acquires a cutoff characteristic that is sharper than a 2nd mode of 24 in a mode of a filter degree 48.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal encoding and decoding apparatus for performing a filtering process.

[0002]

2. Description of the Related Art In recent years, the digitization of audio has progressed rapidly, and digital signal processing technology has been increasingly important. In particular, digital signal processing technology used in a mini-disc reproducing and recording apparatus (hereinafter, abbreviated as a mini-disc) has attracted attention as a new method for recording digital audio data on a magneto-optical disc by a unique signal compression technique.

[0003] A signal encoding device for a mini-disc will be described. Mini discs use ATRAC (Adaptive Transform) to compress digital audio signals to about 1/5.
m Acoustic Coding) system. In a signal encoding device, a digital audio signal input in a time series is divided into three frequency bands to become sub-band signals. By first dividing the digital audio signal into three bands in this way, higher accuracy and shorter processing time are achieved.

[0004] The sub-band signal of each band is cut out by a variable time window, and the MDCT (Modefied Discrete Cosine Tra-
(nsform) transformation to decompose into frequency components to generate frequency spectrum data. The frequency spectrum data generated here is grouped into groups of 52 bands, and signals are thinned out for each group based on human auditory characteristics. This hearing characteristic specifically refers to the minimum audible characteristic and the masking effect. The minimum audible characteristic is a characteristic in which the limit of the sound intensity that can be heard by a human differs depending on the frequency. The masking effect is an effect that when a loud sound is generated at a certain frequency, a small sound at a close frequency becomes inaudible to human ears.

After unnecessary signals are thinned out using these auditory characteristics, the signals are encoded for each group and recorded on a magneto-optical disk. At the time of reproduction, the processing up to now is performed in the reverse order. FIG. 9 is a block diagram showing a configuration of a conventional signal encoding device. A conventional signal encoding apparatus includes a first band division filter 801, a second band division filter 802, block size determination units 803 to 805, MD
CT processing units 806 to 808, adaptive bit allocation unit 80
9, a quantization / encoding bit string generation unit 810.

[0006] The first band division filter 801 converts a digital audio signal transmitted at a sampling frequency of 44.1 kHz and a resolution of 16 bits into a high band sub-band signal of 22.05-11.025 kHz and a mid-low band sub-band signal of 11.025-0 kHz. And output. Further, the mid-low sub-band signal is
The band division filter 802 divides the signal into a 11.025-5.5125 kHz middle band sub-band signal and a 5.5125-0 kHz low band sub-band signal, and outputs the divided signals.

[0007] When the high band sub-band signal, the middle band sub-band signal, and the low band sub-band signal are input to the block size determining units 803 to 805, the block size determining units 803 to 805 respond to the signals. Determine MDCT block size and MDCT processing units 806 to 808
Notify. Here, the MDCT block size is MD
In the processing unit when performing the MDCT conversion in the CT processing units 806 to 808, the subband signal for about 11.6 ms is usually set to one block size. The block size is made variable according to a change in the signal.

[0008] MDCT processing units 806 to 808 convert signals into frequency spectrum data representing frequency components and output the signals in accordance with the MDCT block sizes determined by block size determination units 803 to 805. These frequency spectrum data are divided into groups of 52 bands, and the data is thinned out based on auditory characteristics for each group. After thinning out, the adaptive bit allocation unit 809 allocates the number of bits for each group according to the state of the signal. That is, a larger number of bits is assigned to a group having a large change in signal, and a smaller number of bits is assigned to a group having a small change.

[0009] The quantization / encoding bit string generation unit 810
Quantization is performed in accordance with the number of bits allocated by the adaptive bit allocation unit 809 to generate an encoded bit sequence. An ACIRC (advanced crossinterleaveReed) error correction code is added to the coded bit string generated as described above.
-Solomoncode) and EFM modulation (eight to fourt)
een modulation) and record it on the disc.

[0010] In the case of a minidisk signal decoding device,
A digital audio signal may be generated based on the coded bit sequence recorded on the magneto-optical disk by a procedure reverse to that of the signal coding apparatus described above.

[0011]

However, the signal encoding / decoding device according to the prior art described above has a problem that the power consumption is large. In particular, when the signal encoding / decoding device is used for a portable mini-disc, how to extend the duration of the battery is an important issue in addition to securing the reproduction time.

It is therefore an object of the present invention to provide a signal encoding / decoding device that reduces power consumption.

[0013]

In order to solve the above-mentioned problems, a signal encoding apparatus according to the present invention comprises: a designating unit for designating one of a first mode and a second mode; , M in the first mode
Acquisition means for sequentially acquiring N sample data less than M in the second mode, and M acquired sample data and coefficient data indicating impulse response characteristics in the first mode It is characterized by comprising a calculating means for performing a product-sum operation on a group and performing a product-sum operation on the obtained N sample data and the coefficient data group in the second mode.

Further, the arithmetic means includes: coefficient storage means for storing M coefficient data and N coefficient data respectively indicating the impulse response characteristics;
A product-sum operation is performed from the M sample data and the M coefficient data read from the coefficient storage means, and in the second mode, the N sample data and the coefficient data are read from the coefficient storage means. And an operation unit for performing a product-sum operation from the N pieces of coefficient data.

The calculating means includes coefficient storing means for storing M coefficient data indicating the impulse response characteristic, and in the first mode, the M sample data and M coefficient data are stored.
The apparatus may further include a calculation unit that performs a product-sum operation from the plurality of coefficient data and performs a product-sum operation from the N sample data and the N coefficient data among the M sample data in the second mode. A calculating unit configured to perform a sum-of-products operation on the odd-numbered data of the sample data obtained by the obtaining unit to calculate first intermediate data; The second intermediate data is calculated by performing a multiply-accumulate operation on the even-numbered data of the sampled data thus obtained.
It may include a product-sum operation unit, an addition unit that adds the first intermediate data and the second intermediate data, and a subtraction unit that subtracts the first intermediate data and the second intermediate data.

Further, the signal decoding apparatus according to the present invention comprises:
Specifying means for specifying one of the first mode and the second mode in accordance with a user operation; and adding the time-series digital audio signal of the first band and the time-series digital audio signal of the second band to generate the first time-series digital audio signal. Adding means for calculating intermediate data; subtracting means for calculating time-series second intermediate data by subtracting the time-series digital audio signal of the first band from the time-series digital audio signal of the second band; In the first mode, M pieces of sample data are obtained. In the second mode, N pieces of sample data less than M are sequentially obtained. Means for sequentially acquiring N pieces of sample data in the second mode, and impulse data obtained by the first acquiring means. Sum-of-products operation for performing a product-sum operation with a first coefficient data group indicating a response characteristic, and a product sum of the sample data obtained by the second obtaining unit and a second coefficient data group indicating the impulse response characteristic A second product-sum unit for performing the calculation, and an output unit for alternately outputting the calculation result of the first product-sum unit and the calculation result of the second product-sum unit are provided.

Further, the signal encoding method according to the present invention comprises:
A designation step of designating one of a first mode and a second mode in accordance with a user operation; a step of sequentially acquiring M sample data from a time-series digital audio signal in the first mode; In this case, the method includes a step of sequentially acquiring N sample data less than M from the time-series digital audio signal, and an operation step of performing a product-sum operation of the acquired sample data and a filter coefficient.

[0018]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a signal encoding device according to a first embodiment of the present invention.
In the figure, the signal encoding apparatus includes a first band division filter 101, a second band division filter 102, a filter order switching unit 103, and block size determination units 803 to 80.
5, MDCT processing units 806 to 808, an adaptive bit allocation unit 809, and a quantization / encoding bit string generation unit 810. When a digital audio signal is input, this signal encoding device outputs an encoded bit sequence that is a signal obtained by compressing the original digital audio signal to about 1/5 through processing of each component. It is this encoded bit string that is actually recorded on the recording magneto-optical disk. The processing of each component will be described below.

The first band division filter 101 can switch the effective filter order between 48 and 24, and converts the digital audio signal AD (m) to a high band (22.05-11.025 kHz).
z) and a QMF (quadratu) that divides into two frequency bands of middle and low frequency (11.025-0kHz) and outputs two subband signals
re mirror filter) is an analysis filter bank. Here, the digital audio signal AD (m) is a signal sampled at a sampling frequency of 44.1 kHz and a resolution of 16 bits, where m is an integer representing a discrete time.

For example, if the signal at time m is AD (m),
The previous signal is AD (m-1), and the previous signal is AD (m-2). Digital audio signal AD
When (m) is input, the first band division filter 101
Performs an operation such as coefficient multiplication or addition using a signal of the past filter order (48 or 24) before the digital audio signal AD (m) as one unit, and has a bandwidth of 22.05k.
Hz-11.025kHz high band sub-band signal ADh (m) and bandwidth 11.025-0kHz middle low band sub-band signal ADml
(M). Further, sampling is performed by a down-sampler having a rate of 1/2 times, and the thinned high-frequency sub-band signal ADh (n) and middle-low frequency sub-band signal ADml (n) are sampled at a sampling frequency of 22.0.
Output at 5kHz.

The second band division filter 102 is capable of switching the effective filter order between 48 and 24.
Sampling frequency 22.05k from band division filter 101
Hz, resolution 16-bit middle and low frequency sub-band signal ADml
When (n) is input, calculations such as coefficient multiplication and addition are performed using the signal of the filter order (48 or 24) before ADml (n) as one unit, and the bandwidth becomes 11.05-5.5125.
kHz middle band sub-band signal ADm (n) and bandwidth 5.512
5-0 kHz low band sub-band signal AD1 (n) is generated. Further, sampling is performed by a downsampler having a rate of 1/2 times, and a middle frequency sub-band signal ADm (l) and a low frequency sub-band signal ADl (l) are sampled at a sampling frequency of 11.0.
Output at 25kHz.

Filter order switching section 103 includes first band division filter 101 and second band division filter 10
A filter order switching signal S1 for switching the filter order to 2 (48 or 24) is output. That is, when the filter order is set to 48 (first mode), S1 = 0 is output, and the filter order is set to 24 (second mode).
Is output, S1 = 1 is output. The switching of the switching signal S1 is specifically realized by a switch for user operation.

The switching of the filter order affects sound quality and power consumption. That is, in the first mode having the filter order of 48, a sharper cut-off characteristic is obtained than in the case of the filter order of 24, so that the sound quality is further improved. On the other hand, in the second mode in which the filter order is 24, the load on the product-sum operation described later is reduced, so that the power consumption is lower than in the case of the filter order 48.

The block size determination units 803 to 805
Based on each sub-band signal divided by the first band division filter 101 or the second band division filter 102, M
Block size (MDCT block size) as a processing unit for performing MDCT conversion in DCT processing units 806 to 808
To determine. Normally, about 11.6 ms of the subband signal is 1
Process as block size. However, in the case of a signal having a sudden rise and fall, if 11.6 ms is set as one block size, the change cannot be dealt with. For this reason, the block size was changed according to the input signal of 1/8 for the high-frequency sub-band signal and 1/4 for the mid-range and low-frequency sub-band signals, and a rapidly changing signal such as an impact sound was input. In some cases, the block size is instantaneously switched to a small size so as to cope with a change in signal.

The MDCT processing units 806 to 808 include a first band division filter 101 and a second band division filter 10
2 is extracted from the sub-band signal input from block 2 using the block size determined by the block size determination units 803 to 805 as one unit, and is subjected to MDCT transform to generate frequency spectrum data. The generated frequency spectrum data is grouped into 52 frequency band groups,
Data thinning based on auditory characteristics is performed.

The adaptive bit allocation section 809 adaptively calculates the number of bits to be allocated to each group,
Notify the coded bit string generation unit 810. As a result, the number of bits required for recording a signal is greatly reduced. The quantization / coding bit sequence generation unit 810 quantizes the frequency spectrum data for each group according to the number of bits calculated by the adaptive bit allocation unit 809, adds coding information to this, and generates a coding bit sequence. Generate. This encoded bit string is recorded on the recording minidisc.

Next, the first band division filter 101
The processing inside the second band division filter 102 will be described in detail. In general, a QMF filter bank includes a low-pass filter having a filter coefficient hl (i) (i = 0, 1, 2,...) And a high-pass filter having a filter coefficient hh (i). Here, the filter coefficient is a coefficient representing the impulse response of the filter in a finite time, and is determined at the time of designing the filter so as to obtain a desired frequency characteristic. The digital audio signal AD (m) is divided by these two filters into a low sub-band signal ADL (m) and a high sub-band signal ADH (m). These ADL (m) and ADH (m) are obtained by the following equations.

[0028]

(Equation 1)

[0029]

(Equation 2)

Here, M in Equations 1 and 2 is the filter order of the low-pass filter and the high-pass filter, and matches the number of filter coefficients. Hl (i), hh in Equations 1 and 2
The following relationship is established between (i).

[0031]

(Equation 3)

In order to use Equation 3, X1 (m), X2
(M) is defined as in Equations 4 and 5.

[0033]

(Equation 4)

[0034]

(Equation 5)

ADL (m) and ADH (m) can be expressed as Equations 6 and 7 using Equations 1 and 2.

[0036]

(Equation 6)

[0037]

(Equation 7)

The first band division filter 101 and the second band division filter 102 in the present embodiment are expressed by the following equations (4) to (7).
Is realized. Details will be described with reference to FIG. FIG. 2 is a block diagram showing a more detailed configuration of the first band division filter 101. In the figure, a first band division filter 101 includes a shift register 201, selectors 202 and 203, a filter coefficient memory 204,
05, 206, an adder 207, and a subtractor 208, which divide an input digital audio signal into two frequency bands. The operation of each component will be described below.

The shift register 201 has 16 bits, 4 bits,
This is an eight-stage shift register. In the figure, when a 16-bit digital audio signal AD (m) is input at a frequency of 44.1 kHz from the left, the shift register 201 discards the oldest digital audio signal at the right end, and shifts the remaining M-1 pieces of digital audio signals. The digital audio signal is sequentially shifted rightward.

The selector 202 receives the filter order switching signal S1 from the filter order switching unit 103.
, The digital audio signal AD (m−2i) input from the shift register 201 (where 12 <= i
<= 23) or 24 0s (16 bits) are sent to the arithmetic unit 205. That is, when S1 = 0, the selector 202 sends the digital audio signal AD (m−2i) input from the shift register 201 to the arithmetic unit 205. When S1 = 1, the selector 202 outputs the digital audio signal A (m−2i).
0 is sent to the arithmetic unit 205 instead of D (m−2i).

The selector 203 receives the filter order switching signal S1 from the filter order switching unit 103.
, The digital audio signal AD (m− (2i + 1)) input from the shift register 201 (where 1
2 <= i <= 23) or 24 0s (16 bits) are sent to the arithmetic unit 206. That is, when S1 = 0, the digital audio signal AD (m− (2i +
1)) is sent to the arithmetic unit 206, and when S1 = 1, 0 is sent to the arithmetic unit 206 instead of the digital audio signal AD (m- (2i + 1)).

The filter coefficient memory 204 stores the arithmetic unit 20
5 and filter coefficients h0 (x) and h1 (x) (0 <= x <= 47) used for multiplication in the arithmetic unit 206 are held. When the filter order switching signal S1 input from the filter order switching unit 103 is 0, h0
When (x) is equal to 1, h1 (x) is supplied to the computing units 205 and 206 as h (x).

When the filter order switching signal S1 = 0, the arithmetic unit 205 sends AD (m−2i) (where 0 <= i <= 11) sent from the shift register 201 and sends it through the selector 202. AD (m−2i) (where 12 <= i <= 23) and h (2i) (where 1 <= i <= 23) in the filter coefficient memory 204 are used to calculate the intermediate data X1 (m) Is output.

When the filter order switching signal S1 = 1, the arithmetic unit 205 outputs AD (m−2i) (where 0 <= i <= 11) sent from the shift register 201 and 0 sent from the selector 202. , Filter coefficient memory 2
04 from h (2i) (1 <= i <= 23)
And outputs intermediate data X1 (m). That is, when S1 = 1, the multiplication after i = 12 in Equation 4 becomes 0, so that the load on the arithmetic processing is reduced.

When filter order switching signal S1 = 0, arithmetic unit 206 outputs AD (m- (2i + 1)) (where 0 <= i <= 1) from shift register 201.
1), AD (m-
(2i + 1)) (where 1 <= i <= 23), h (2i + 1) in the filter coefficient memory 204 (where 0 <= i <
= 23) to calculate the intermediate data X2 (m)
Is output.

When filter order switching signal S1 = 1, arithmetic unit 206 outputs AD (m- (2i + 1) (where 0 <= i <= 1) sent from shift register 201.
1), 0 sent from the selector 203, h (2i + 1) of the filter coefficient memory 204 (where 1 <= i <= 2
3) The arithmetic operation of Expression 5 is performed to output intermediate data X2 (m). That is, similarly to the arithmetic unit 205, when S1 = 1, the multiplication after i = 12 in Equation 5 becomes 0.

The adder 207 obtains ADL (m) by performing addition shown in Expression 6 from the intermediate data X1 and X2 obtained by the multiplication and addition of the arithmetic units 205 and 206, and further obtains ADL (m). Down-sampler
ler), and outputs a mid-low sub-band signal ADml (m) having a bandwidth of 11.025-0 kHz. The subtracter 208 obtains ADH (m) by performing subtraction shown in Expression 7 from the intermediate data X1 and X2 obtained by the multiplication and addition of the arithmetic units 205 and 206, and further obtains a downsampler having a rate of 1/2 times. Sampling at
22.5-11.025kHz high band sub-band signal ADh (m) is output.

As described above, the first band division filter 101
Is shown using a shift register and various arithmetic units, but this is equivalent to that realized by software as follows. (Second Embodiment) The schematic configuration of a signal encoding device according to a second embodiment is the same as that of FIG. 1 of the first embodiment, but the first band division filter 101 and the second band division filter 102 The internal configuration is different. The same points are not described, and the first band division filter 101 and the second band division filter
The internal configuration of the band division filter 102 will be described.

In this embodiment, the first band division filter 1
01 and the second band splitting filter 102
gital Signal Processor). This DSP has a built-in memory, and realizes the functions of the first band division filter 101 and the second band division filter 102 by executing a program in the memory.

FIG. 3 is a flowchart showing a processing procedure of the DSP for realizing the function of the first band division filter 101 in this embodiment. In step 301, the first band division filter 101 determines the filter order switching signal S1 output from the filter order switching unit 103. That is, when S1 = 0, the first band division filter 101 sets the filter coefficient h0 (x) (0 <= x <=
47) and the 48 continuous digital audio signals to calculate intermediate data X1 and X2 (steps 302 and 30).
3) When S1 = 1, the filter coefficient h1 (x) (0
<= X <= 23) and the intermediate data X1 and X2 are calculated from the continuous 24 digital audio signals (steps 305 and 306). Here, M = 48 and N = 24.

The high band sub-band signal ADH (m) and the middle low band sub-band signal ADL (m) are calculated from the intermediate data X1 and X2 calculated in steps 302 and 303 or steps 305 and 306. The DSP processing of the first band division filter 101 has been described above, but the description of the second band division filter 102 is omitted because it is almost the same.

In the second embodiment, the filter coefficient is set to h0 (x) according to the filter order switching signal S1.
Alternatively, h1 (x) is switched, but the same coefficient may be used without switching. The processing procedure of the DSP in this case will be described below. In FIG. 4, steps having the same step numbers as those in FIG.
Hereinafter, different steps will be mainly described.

In step 301, when the filter order switching signal S1 = 1, the following arithmetic operations shown in equations 8 and 9 are performed to calculate intermediate data X1 (m) and X2 (m).

[0054]

(Equation 8)

[0055]

(Equation 9)

Here, M = 48 and N = 24. Steps 405 and 406 differ from FIG. 3 in the range of i and the filter coefficient used. In FIG. 3, the filter coefficient is a filter order switching signal S.
The state is switched to h0 or h1 according to 1. In the third embodiment, the filter coefficient uses h0 regardless of whether the filter order switching signal S1 is 0 or 1. (Third Embodiment) FIG. 5 is a block diagram showing a configuration of a signal decoding device according to a third embodiment of the present invention.

The signal decoding apparatus according to the present embodiment includes a coded bit stream decomposition / inverse quantization section 111, inverse MDCT processing sections 112 to 114, a first band synthesis filter section 501, a second band synthesis filter section 502, a filter order This device is constituted by a switching unit 503, and expands an encoded bit sequence recorded on a magneto-optical disk to decode digital audio data having a frequency of 44.1 kHz and a resolution of 16 bits.

Encoded Bit String Decomposition / Dequantization Unit 111
Extracts encoded information and quantized frequency spectrum data from an encoded bit string, and performs inverse quantization to restore the frequency spectrum data. The inverse MDCT processing units 112 to 114 perform inverse MDCT conversion on the frequency spectrum data according to the MDCT block length of each band, and perform high-frequency (bandwidth 22.05-11.025 kHz) expressed in discrete time.
z), midrange (bandwidth 11.025-5.5125kHz), low range (bandwidth
5.5125-0kHz).

The filter order switching unit 503 outputs a filter order switching signal S2 for switching the filter order of the first band combining filter unit 501 and the second band combining filter unit 502 (to 24 or 12).
S2 when the filter order is set to 24 (first mode)
S2 to output = 0 and set it to 12 (second mode)
= 1 is output. The switching of the switching signal S2 is as follows.
Specifically, it is realized by a switch for user operation.

The switching of the filter order affects sound quality and power consumption. That is, in the first mode in which the filter order is 24, the sound quality is further improved because the desired frequency characteristic is closer to that in the case where the filter order is 12. On the other hand, in the second mode in which the filter order is 24, the load on the product-sum operation described later is reduced, so that the power consumption is lower than in the case of the filter order 48.

The first band synthesizing filter 501 is a QMF filter bank for synthesizing a middle band sub-band signal and a low band sub-band signal by arithmetic processing to generate a middle-low band (bandwidth 11.025-0 kHz) sub-band signal. is there. The second band synthesis filter unit 502 combines the high band subband signal from the inverse MDCT processing unit 112 and the middle and low band subband signal from the first band synthesis filter unit 501 by arithmetic processing,
It outputs digital audio data with a frequency of 44.1 kHz and a resolution of 16 bits.

The first band combining filter section 501 and the second band combining filter section
The band synthesis filter unit 502 can switch the filter order effective for the arithmetic processing by the filter order switching unit 503. Details will be described later with reference to FIG. Next, the processing inside the first band synthesis filter unit 501 and the second band synthesis filter unit 502 will be described in detail.

The digital audio data AD (m) obtained by synthesizing the high-frequency sub-band signal ADH (n) and the low-frequency sub-band signal ADL (n) is expressed as , 11 and Equations 12 and 13
It is represented by

[0064]

(Equation 10)

[0065]

[Equation 11]

[0066]

(Equation 12)

[0067]

(Equation 13)

Here, h is a filter coefficient of a synthesis filter for synthesizing signals of two bands. The internal configurations of the first band combining filter unit 501 and the second band combining filter unit 502 in the present embodiment realize the equations 10 to 13. The configuration will be described below with reference to FIG. FIG. 6 is a block diagram showing a more detailed configuration of the second band synthesis filter 502.

In FIG. 6, the second band synthesis filter unit 5
02 denotes an adder 602, a subtractor 603, a shift register 604, a shift register 605, a computing unit 606, a computing unit 607, a selector 608, a selector 609, and a delay circuit 6.
10 and the input high-frequency sub-band signal AD
The digital audio data AD2 (m) is output based on h (n) and the middle / low band sub-band signal ADml (n). Here, m and n are sampling frequencies of 22.05k, respectively.
Expresses discrete time of Hz and 44.1kHz.

The adder 602 generates the sub-band signal ADh
When (n) and ADml (n) are input, the addition shown in Expression 10 is performed, and the intermediate data Y1 (n) is output to the shift register 604. When ADh (n) and ADml (n) are input, the subtracter 603 performs the subtraction shown in Expression 11, and stores the intermediate data Y2 (n) in the shift register 605.
Output to

The shift register 604 has 16 bits, 4 bits,
This is an eight-stage shift register. Shift register 604
Is, when the intermediate data Y1 (n) is input from the left of the figure,
The oldest intermediate data Y1 (n- (M-1)) at the right end is discarded, and the other intermediate data Y1 is sequentially shifted rightward. The shift register 605 is a shift register 60
4 is the same shift register. However, Y2 is input instead of the intermediate data Y1.

The selector 608 outputs a filter order switching signal S 2 notified from the filter order switching unit 503.
, The intermediate data Y1 (ni) input from the shift register 604 (where 12 <= i <= 23) or
Alternatively, twelve 0s (16 bits) are sent to the arithmetic unit 606. That is, when S2 = 0, the intermediate data Y1
(Ni), and when S2 = 1, Y1 (n-
0 is sent to the arithmetic unit 606 instead of i).

The selector 609 is similar to the selector 608. However, the input intermediate data is not Y1, but Y2. When the filter order switching signal S2 = 0, the arithmetic unit 606 sends Y1 (n−i) (0 <= i <= 11) sent from the shift register 604 and Y1 (n) sent via the selector 608. −i) (where 1
2 <= i <= 23), h2 of the filter coefficient memory 601
(I) The arithmetic operation of Expression 12 is performed from (where 0 <= i <= 23), and digital audio data AD2 (m) (where m = 2n) is output.

When the filter order switching signal S 2 = 1, the arithmetic unit 606 outputs Y 1 (n−i) (0 <= i <= 11) sent from the shift register 604, and outputs 0, Filter coefficient memory 60
From h5 (i) of 1 (where 0 <= i <= 23), Equation 12
And the digital audio data AD2 (m)
(Where m = 2n) is output.

When the filter order switching signal S 2 = 0, the arithmetic unit 607 sends out Y 2 (n−i) (where 0 <= i <= 11) sent from the shift register 604 and sends it out via the selector 609. Y2 (mi) (however, 1
2 <= i <= 23), h2 of the filter coefficient memory 601
(I) The arithmetic operation of Expression 13 is performed from (where 0 <= i <= 23), and digital audio data AD2 (m) (where m = 2n + 1) is output.

When the filter order switching signal S 2 = 1, the arithmetic unit 607 outputs Y 2 (n−i) (where 0 <= i <= 11) sent from the shift register 604, and outputs 0, Filter coefficient memory 60
From h5 (i) of 1 (where 0 <= i <= 23), Equation 13
And the digital audio data AD2 (m)
(Where m = 2n + 1) is output.

The filter coefficient memory 601 includes a computing unit 60
6 and filter coefficients h2 (i) and h5 (i) used for multiplication in the arithmetic unit 607. When the filter order switching signal S2 input from the filter order switching unit 503 is 0, h2 (i) is supplied to the computing units 606 and 607 when h2 (i) is 1 and when h2 (1) is 1, respectively.

The delay circuit 610 delays AD2 (m) output from the arithmetic unit 606 by 44.1 kHz and outputs the result. As a result, AD2 from the arithmetic unit 607 and AD2 from the arithmetic unit 606 are alternately transmitted, and as a result, digital audio data AD2 (m) (m = 0, 1, 2,...) Having a sampling frequency of 44.1 kHz. …) Is output. (Fourth Embodiment) The schematic configuration of a signal decoding device according to a fourth embodiment is the same as that of FIG. 5 of the third embodiment, except that a first band synthesis filter unit 501 and a second band synthesis filter unit are used. The internal configuration of 502 is different. The description of the same points will be omitted, and the internal configurations of the first band combining filter unit 501 and the second band combining filter unit 502 will be described below.

In the present embodiment, the first band synthesis filter unit 501 and the second band synthesis filter unit 502
Performs band synthesis processing. This DSP has a built-in memory, and realizes the functions of the first band division filter 101 and the second band division filter 102 by executing a program in the memory. FIG. 7 is a flowchart illustrating a processing procedure of the DSP that realizes the function of the second band synthesis filter unit 502 according to the fourth embodiment.

The second band synthesizing filter unit 502
When l (n) and ADh (n) are input, subtraction is performed and intermediate data Y1 (n) is added and intermediate data Y1 (n) is added.
(N) is calculated (steps 701 and 702). Next, the second band synthesis filter unit 502 determines whether the filter order switching signal S2 is 0 or 1 (Step 703).

As a result, in the case of S2 = 0, that is, in the case of the first mode, in steps 704 and 705, the digital audio signal AD2 (m) is calculated with the filter order 24. The filter coefficient used at this time is h2. S
Steps 706 and 7 when 2 = 1, that is, in the second mode
At 07, the digital audio signal AD2 (m) is calculated using the filter order 12. The filter coefficient used at this time is h5.

In the fourth embodiment, the filter coefficient is switched between h2 and h5 according to the filter order switching signal S2, but the same coefficient may be used without switching. The processing procedure of the DSP in this case will be described below. FIG. 8 is a flowchart showing the processing of the second band synthesis filter 502. In this figure, the steps denoted by the same step numbers as those in FIG. 7 perform the same processing, and thus description thereof will be omitted, and the following description will focus on different steps.

In step 703, when the filter order switching signal S2 = 1, the operations shown in steps 806 and 807 are performed to obtain the digital audio signal AD2 (m).
Is calculated. Here, M = 24 and N = 12.
In FIG. 7, the filter coefficient is also switched between h2 and h5 in accordance with the value of the filter order switching signal S2. In FIG. 8, however, the filter coefficient h6 in steps 806 and 807 is This is equivalent to the filter coefficient h2.

The first band synthesizing filter section 501 is almost the same as the above, and a description thereof will be omitted. In the first and second embodiments, the filter order is 48 or 24. However, the filter order is not limited to this value, and a different value may be set according to the application. In the present embodiment, the second mode with a filter order of 24 is designed to be suitable for recording for a long time such as a conference or an interview and does not require sound quality comparable to music. A filter design may be performed in consideration of a trade-off with the recording time, and the filter order may be set based on the design. The same applies to the third and fourth embodiments.

The switching between the first mode and the second mode is a user operation, but the present apparatus may automatically switch the mode when the remaining battery level is low. Specifically, the configuration of FIG. 1 further includes a monitoring unit that monitors the remaining amount of the battery, and when the remaining amount of the battery becomes lower than a certain value, the monitoring unit notifies the filter order switching unit 103 of the fact. , The filter order switching signal S1 is changed from 0 in the first mode to the second signal indicating low power consumption.
The mode may be switched to mode 1.

[0086]

According to the signal encoding apparatus of the present invention, when the first mode is selected from the time series digital audio signal and the specifying means for specifying one of the first mode and the second mode in accordance with a user operation, M sample data
An acquisition unit for sequentially acquiring N sample data less than M in the second mode, and a product-sum operation of the acquired M sample data and a coefficient data group showing an impulse response characteristic in the first mode And in the second mode,
Since there is provided an operation unit for performing a product-sum operation of the obtained N sample data and the coefficient data group, the second mode is designated as compared with the case where the first mode is designated. The number of times of the product-sum operation is reduced to about N / M, so that the load on the operation means is reduced, so that the power consumption of the signal encoding device can be reduced. This is effective, for example, when a user wants to record for a long time in a battery-driven mini-disc device equipped with the present device. When the sound is recorded in the second mode, the sound quality is slightly deteriorated. However, a practical effect is great in a recording such as an interview or a conference that does not require sound quality comparable to music.

Further, since the designating means for designating the mode follows the operation of the user, there is an effect that the user can switch the mode as needed. Further, the arithmetic means includes: coefficient storage means for storing M coefficient data and N coefficient data respectively indicating the impulse response characteristics; and in the first mode, the M sample data and the coefficient storage. A product-sum operation is performed from the M coefficient data read out from the means, and in the second mode, the N sample data and the N data read out from the coefficient storage means are read.
Since there is provided an operation unit for performing a product-sum operation from the pieces of coefficient data, there is an effect that two types of coefficient data can be used.

The calculating means includes coefficient storing means for storing M coefficient data indicating the impulse response characteristic, and in the first mode, the M sample data and M coefficient data are stored.
And a calculation unit for performing a product-sum operation from the N sample data and the N coefficient data among the M sample data in the second mode. The mode can be switched only by storing the M coefficient data in the means, and there is an effect that the storage capacity of the coefficient storage means can be saved.

The calculating means may perform a product-sum operation on the odd-numbered data of the sample data obtained by the obtaining means to calculate first intermediate data. A second operation of calculating a second intermediate data by performing a product-sum operation on even-numbered data of the data
Since the digital audio signal includes a product-sum operation unit, an addition unit that adds the first intermediate data and the second intermediate data, and a subtraction unit that subtracts the first intermediate data and the second intermediate data, the digital audio signal is high. In a band division filter that divides a band into a band and a low band, the same effect as described above is obtained.

A signal decoding apparatus for performing a filtering process, comprising: a designating means for designating one of a first mode and a second mode in accordance with a user operation; a time-series digital audio signal of a first band; Adding means for calculating time-series first intermediate data by adding the two-band time-series digital audio signal; and subtracting the first-band time-series digital audio signal from the second-band time-series digital audio signal. Subtracting means for calculating the second intermediate data of the series, and sequentially obtaining M sample data in the first mode and N sample data less than M in the second mode from the first intermediate data. M sample data in the first mode and N sample data in the second mode are sequentially obtained from the first obtaining means and the second intermediate data. A second acquisition unit, a first sum-of-products operation for performing a product-sum operation of the sample data acquired by the first acquisition unit and a first coefficient data group indicating an impulse response characteristic, and a sample acquired by the second acquisition unit. Second sum-of-products means for performing a sum-of-products operation of data and a second coefficient data group indicating the impulse response characteristic, and an output for alternately outputting the calculation results of the first sum-of-products means and the calculation results of the second sum-of-products means Means, the number of sample data used in the operation is reduced in the second mode, and the number of product-sum operations is reduced to about N / M in the second mode as compared with the first mode. Therefore, the signal decoding device that combines the two band signals also has the effect of reducing power consumption as described above. This is effective when a recording such as an interview or a conference is reproduced for a long time in a battery-driven mini-disc device equipped with the present device. In the second mode, the sound quality is slightly degraded,
Practical effects are great for recordings that do not require sound quality comparable to music, such as interviews and conferences.

A signal encoding method for performing a filtering process, comprising: a designation step of designating one of a first mode and a second mode in accordance with a user operation;
In the mode, the time-series digital audio signal
Sequentially obtaining a number of sample data, a step of sequentially obtaining N sample data less than M from the time-series digital audio signal in the second mode, a step of obtaining the sample data and a filter coefficient. Since it has an operation step of performing a product-sum operation, the same effect as described above can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a signal encoding device according to a first embodiment.

FIG. 2 is a block diagram illustrating a more detailed configuration of a first band division filter 101 according to the first embodiment.

FIG. 3 is a flowchart illustrating processing of a first band division filter 101 in software according to the second embodiment.

FIG. 4 is a flowchart illustrating processing of a first band division filter 101 according to a second embodiment in software.

FIG. 5 is a block diagram illustrating a configuration of a signal decoding device according to a third embodiment.

FIG. 6 is a block diagram illustrating a more detailed configuration of a second band synthesis filter 502 according to the third embodiment.

FIG. 7 is a flowchart illustrating processing of a second band synthesis filter unit 502 according to a fourth embodiment in terms of software.

FIG. 8 is a flowchart illustrating processing of a second band synthesis filter 502 according to a fourth embodiment in terms of software.

FIG. 9 is a block diagram illustrating a configuration of a conventional signal encoding device.

[Explanation of symbols]

 Reference Signs List 101 first band division filter 102 second band division filter 103 filter order switching unit 201 shift register 202, 203 selector 204 filter coefficient memory 205, 206 arithmetic unit 207 adder 208 subtractor 803-805 block size determination unit 806-808 MDCT Processing unit 809 Adaptive bit allocation unit 810 Quantization / encoding bit string generation unit

Claims (6)

[Claims] 1. A signal encoding apparatus for performing a filtering process, comprising: a designation unit for designating one of a first mode and a second mode in accordance with a user operation; Acquisition means for sequentially acquiring M sample data in the second mode and N sample data less than M in the second mode; and acquiring the M sample data and the impulse response characteristics in the first mode. And a calculating means for performing a product-sum operation with the coefficient data group shown in the second mode and performing a product-sum operation between the acquired N sample data and the coefficient data group in the second mode. apparatus. 2. The arithmetic means comprises: coefficient storage means for storing M coefficient data and N coefficient data respectively representing the impulse response characteristics; and in the first mode, the M sample data. A product-sum operation is performed from the M coefficient data read from the coefficient storage means, and in the second mode, a product is calculated from the N sample data and the N coefficient data read from the coefficient storage means. The signal encoding device according to claim 1, further comprising: an operation unit that performs a sum operation. 3. The arithmetic means comprises: coefficient storage means for storing M coefficient data indicating the impulse response characteristic; and in a first mode, a product from the M sample data and the M coefficient data. Performs a sum operation, and in the second mode,
The signal encoding apparatus according to claim 1, further comprising: a calculation unit configured to perform a product-sum operation from the N sample data and N coefficient data in the M sample data. 4. The first sum-of-products calculation unit that performs a sum-of-products calculation on the odd-numbered data of the sample data obtained by the obtaining unit to calculate first intermediate data, A second sum-of-products operation unit for performing a sum-of-products operation on the even-numbered data of the sample data obtained by the means to calculate second intermediate data; and adding the first intermediate data and the second intermediate data. The signal encoding device according to claim 1, further comprising: an adding unit; and a subtracting unit that subtracts the first intermediate data and the second intermediate data. 5. A signal decoding apparatus for performing a filtering process, comprising: a designation unit for designating one of a first mode and a second mode in accordance with a user operation; Adding means for calculating time-series first intermediate data by adding the two-band time-series digital audio signal; and subtracting the first-band time-series digital audio signal and the second-band time-series digital audio signal. Subtraction means for calculating second intermediate data of a series; and M sample data in the first mode and N sample data less than M in the second mode are sequentially obtained from the first intermediate data. M sample data in the first mode and N sample data in the second mode are sequentially obtained from the first obtaining means and the second intermediate data. 2 acquisition means, 1st sum-of-products means for performing a product-sum operation of the sample data acquired by the 1st acquisition means and the first coefficient data group showing the impulse response characteristic, and sample data acquired by the 2nd acquisition means And a second coefficient data group indicating the impulse response characteristic, a second sum-of-products means, and an output means for alternately outputting a calculation result of the first sum-of-products means and a calculation result of the second sum-of-products means A signal decoding device comprising: 6. A signal encoding method for performing filter processing, comprising: a designation step of designating one of a first mode and a second mode in accordance with a user operation; Sequentially acquiring M sample data from the signal; in the second mode, sequentially acquiring N sample data less than M from the time-series digital audio signal; acquiring the sample data; An operation step of performing a product-sum operation with a coefficient.