KR100284072B1 - Self Refresh Test Circuit - Google Patents

Abstract

The self-refresh test circuit of the present invention reduces the amount of charge stored in the memory cell by narrowing the width and period of the row address strobe signal in the form of a pulse, thereby reducing the self refresh test time and the width of the row address strobe signal as usual. This provides the advantage that the self refresh mode can also be performed.

Description

Self Refresh Test Circuit

1 is a block diagram of a conventional self refresh circuit.

2 is a timing diagram of a signal related to FIG.

3 is a block diagram of a self refresh test circuit in accordance with an embodiment of the present invention.

4 is a timing diagram of a signal related to FIG.

* Explanation of symbols for main parts of the drawings

10: test pad 20: cell fresh test detector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self refresh test circuit, and more particularly, to a self refresh test circuit which reduces a test time by adjusting a row address strobe cycle to reduce the amount of charge stored in a memory cell. It is about.

FIG. 1 is a normal self refresh circuit, and FIG. 2 is a timing diagram of signals related to the first diagram, and detailed description thereof will be omitted.

The operation of the self-refresh circuit of FIG. 1 will be briefly described with reference to FIG. Is enabled, and the memory device enters CBR mode. After the memory device enters the CBR mode and the state transition does not occur in the ras bar for a predetermined time (for example, 64us), the refresh cycle (e.g., section E of the ras signal, which is the row address strobe signal of FIG. For example, a burst mode is performed in which all memory cells are refreshed for a predetermined time (for example, 512us) in accordance with 512 cycles. After the burst mode is performed, a distributed mode is performed in which word lines are refreshed at regular intervals (for example, 128us), such as the F section of the lath signal. After the refresh operation is completed, the self refresh test mode is completed by reading data of the refreshed memory cell again.

However, testing the normal self refresh circuit takes more than four times as long as the time required for performing the normal normal refresh mode.

Accordingly, an object of the present invention is to make the generation cycle of the row address strobe signal equal to the burst mode in the self refresh test mode, and supply the memory cell with the minimum charge necessary to refresh the row address strobe signal in the form of a pulse. The present invention provides a self-refresh test circuit that operates only while being driven to perform fast test operation. In the normal self-refresh mode, the period and width of pulse generation are as usual. That is, it also provides an advantage of entering the cell refresh test mode or the cell refresh mode by adjusting the generation period and width of the pulse.

In order to achieve the above object, the self-refresh test circuit of the present invention detects the cell refresh mode by using a test pad and adjusts the width of the row address strobe signal by using a fuse to store the pre-stored memory cell. Minimize white.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail. 3 is a block diagram showing a self-refresh (S / R) test circuit of the present invention, which is a normal self-refresh circuit 40 and a test pad for adjusting the period of the row address strobe signal (hereinafter, las). (10), the S / R test detector 20 for detecting the entry into the self-refresh test mode according to the signals from the test pad 10 and the S / R detector 4, and the 4 and 20 And a burst mode detector 6 that detects whether or not to enter the burst mode in accordance with a signal from the burst mode control circuit 5, and adjusts a pulse width according to the signal from the S / R test detector 20. And a cell refresh command 8 for generating a cell refresh command signal in accordance with the signals from the 30, 4, 6, and burst mode period generators 7, respectively.

FIG. 4 is a timing diagram showing signals related to the self-refresh test circuit of the present invention of FIG. 3, and the operation of FIG. 3 will be described with reference to FIG. In the self refresh test mode, the self refresh test circuit uses the pad 10 to perform a rapid cycle of refresh in burst mode during the cycle before the self refresh test. In addition, the pulse width required for sensing data is narrowed to minimize the amount of charge stored in the memory cell. In the self-refresh test mode, even if the pulse width is reduced, the circuit can be tested for normal operation to the minimum required by the refresh.

The self-refresh test circuit adjusts the pulse width tras to the test pad 10 to supply a full amount of charge to the memory cell, thereby performing a mode of self-refreshing one word line every 128 us after the burst mode.

In detail, the test completion time of the conventional self refresh test circuit is 128ms at 4 mega DRAM. However, the test can be completed within 1 ms using the self refresh test circuit of the present invention.

As described above, the self-refresh test circuit of the present invention reduces the amount of charge stored in the memory cell by narrowing the pulse width (tras) and period of the lath signal, thereby reducing the self-refresh test time and in the normal self test mode. Self-test mode is performed with sufficient spacing between pulses.

Claims (3)

Cell refresh test detection means for determining the entry of the self refresh mode or the self refresh test mode by a signal from the outside, and burst mode for generating a row address strobe signal continuously in accordance with the signal from the cell refresh test detection means. A sensing time control means for adjusting a sensing time of a row address strobe signal according to a sensing means, a signal from the cell refresh test sensing means, and a self refresh by a signal from the burst mode sensing means and sensing time control means And a self-refresh command signal generating means for generating a command signal. The cell refresh test circuit according to claim 1, wherein the sensing time control means comprises a fuse. 2. The self-refresh test circuit as claimed in claim 1, wherein the cell refresh test sensing means comprises a pad.