KR100283449B1 - Aspect ratio inverter of tv screen - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an aspect ratio convertor (ARC) of a television receiver, and more particularly, to an aspect ratio converting apparatus for a television screen, which can prevent a deterioration in image quality occurring when the screen is expanded in a vertical direction.

In the aspect ratio converting apparatus of the conventional television screen, when the transition of the video signal occurs in the vertical direction between the V3 and V5 lines as shown in (b) and (c) of FIG. 2, the V5 line is input at 0 IRE level. 50 IRE is output in the extended CV5 line, and 25 IRE is output in the CV7 line, resulting in deterioration of image quality and deterioration of vertical resolution.

The present invention suppresses signal damage in the transition region by extending the image signal line in the vertical direction by performing linear operation after compensating for the vertical transition region through MIDEAN processing of the input image signal. It is an aspect ratio converting device for TV screens to improve image quality and express high definition images.

Description

Aspect ratio inverter of tv screen

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an aspect ratio convertor (ARC) of a television receiver, and more particularly to an aspect ratio converting apparatus of a television screen, which can prevent a deterioration in image quality occurring when the screen is expanded in a vertical direction.

Referring to FIG. 1, a conventional aspect ratio conversion apparatus for a television screen includes an analog digital converter 1 for converting an input video signal into a digital video signal, and a digital video signal output from the analog digital converter 1 in units of fields. The field memory 2 to be stored, the vertical expansion operation unit 3 which reads the image signals stored in the field memory 2 and expands them in the vertical direction, and the digital image signals output from the vertical expansion operation unit 3 are analog images. A digital analog converter 4 for converting and outputting a signal, a clock generator 5 for generating a clock using a synchronization signal of the input video signal, and a clock generated by the clock generator 5 Timing pulse generator 6 for supplying timing control pulses of analog digital converter 1, field memory 2, vertical expansion computing section 3, and digital analog converter 4; It consists of.

The vertical expansion operation by the aspect ratio converting apparatus of the conventional television screen configured as described above will be described with reference to FIGS. 1 to 4.

The clock generator 5 generates a clock by multiplying the horizontal synchronizing signal and the vertical synchronizing signal of the input video signal, and the clock is input to the timing pulse generator 6, and the timing pulse generator 6 is an input clock. Using this function, pulses of appropriate timing necessary for digital conversion, storage and output of video signal, vertical expansion operation, and analog conversion are generated and supplied to each block. The analog digital converter 1 receives the plunging clock of the timing pulse generator 6 and converts the input video signal into a digital video signal, and the field memory 2 stores and outputs the digital video signal in units of fields. The vertical expansion calculating section 3 reads the digital video signal output from the field memory 2 and performs the expansion processing in the vertical direction.

FIG. 2 shows a control signal supplied to the field memory 2, in which (a) shows a vertical synchronization pulse, (b) shows a write reset pulse, and (c) shows a read reset pulse.

That is, the position for performing expansion in the vertical direction is changed according to the positional relationship between the vertical synchronization pulse of (a) and the write reset pulse of (b), and the read reset signal of (c) is the vertical synchronization of (a). At the same timing as the pulse.

3 illustrates an example in which the vertical expansion operation unit 3 extends the aspect ratio in the vertical direction by 33%. The video signals V1, V3, V5, and V7 (or V0, respectively) of the lines of the odd field (or even field) are shown. Constant operations are performed on V2, V4, V6, and V8 respectively to obtain extended video signals CV1, CV3, CV5, CV7 (or CV0, CV2, CV4, CV6, CV8).

As an example, in the Radix field, CV1 = V1, CV3 = 2/8 * V1 + 6/8 * V3, CV5 = 4/8 * V3 + 4/8 * V5, CV7 = 6/8 * V5 + 2/8 * From V7 and V7, an extension operation that repeats the same operation as in V1 is executed again so that 3 lines (V1) (V3) (V5) are converted to 4 lines (CV1) (CV3) (CV5) (CV7), thereby expanding by 33%. Done.

Fig. 4 (a) shows the V1 and CV1 lines of the input image signal waveform and the output waveform in this case, (b) shows the V3 and CV3 lines, and (c) shows the V5 and CV5 lines, and (d ) Shows V7 and CV7 lines, respectively.

And in even field, CV2 = 1/8 * V0 + 7/8 * V2, CV4 = 3/8 * V2 + 5/8 * V4, CV6 = 5/8 * V4 + 3/8 * V6, CV8 = 7 / 8 * V5 + 1/8 * V8 and the same operation as in V2 is repeated from line V8, so the video signal of three lines (V2) (V4) (V6) is four lines (CV2) (CV4) Converted to (CV6) (CV8), a 33% expansion is achieved.

As described above, in the vertical extension association section 3, the above operation is performed according to the eight sequence control signals supplied from the timing pulse generator 6 in the 33% extension mode, thereby expanding the video signal screen in the vertical direction. The extended video signal is converted into an analog signal by the digital analog converter 4 and output.

However, in the aspect ratio converting apparatus of the conventional television screen, when the transition of the video signal occurs in the vertical direction between the V3 and V5 lines as shown in FIGS. 2B and 2C, the V5 line is at 0 IRE level. Even when inputted as, the output of 50 IRE is shown in the extended CV5 line and 25 IRE is shown in the CV7 line, resulting in deterioration of image quality and deterioration of vertical resolution.

The present invention suppresses signal damage in the transition region by extending the image signal line in the vertical direction by performing linear operation after compensating for the vertical transition region through MIDEAN processing of the input image signal. Accordingly, an object of the present invention is to provide an aspect ratio converting apparatus for a television screen capable of improving image quality and expressing high definition images. Hereinafter, the configuration of the present invention and its effects will be described with reference to the accompanying drawings.

1 is a block diagram of a conventional television screen vertical expansion apparatus.

2A-C are waveform diagrams of field memory control signals of a conventional vertical expansion device.

3 is a view showing the operation principle of the vertical expansion operation unit in the conventional vertical expansion device.

4A-D are waveform diagrams of input and output signals of a conventional vertical expansion apparatus.

5 is a block diagram of an aspect ratio converter of a television screen of the present invention.

6 is a view showing the operation principle of the vertical expansion processing unit of the present invention.

7a and b are block diagrams of the median processing unit in the present invention.

8A-D are waveform diagrams of input and output signals of the present invention.

Referring to FIG. 5, the aspect ratio converting apparatus for a television screen according to the present invention includes an analog digital converter 11 for converting an input analog video signal into a digital signal, and a digital video signal output from the analog digital converter 11. Field memory 12 for outputting the video signal delayed by the position to be vertically expanded and the video signal delayed by one field, and the video signal output from the field memory 12, and obtaining an intermediate value. A vertical expansion processing unit 13 that performs vertical expansion operation using the intermediate value and the delayed video signal, and converts the digital video signal output from the vertical expansion processing unit 13 into an analog video signal and outputs the extended video signal. Generating a clock required for system operation by using a digital analog converter 14 and a synchronization signal of the input video signal. The analog digital converter 11, the field memory 12, the vertical expansion processor 13, and the digital analog converter 14 by receiving the clock generator 15 and the clock output from the clock generator 15. And a timing pulse generator 16 for generating and supplying control pulses of the control pulses. The vertical expansion processor 13 delays a video signal delayed by one line by a vertical expansion position output from the field memory 12. A median processor 18 for calculating and outputting an intermediate value between a memory 17 and a video signal delayed in the line memory 17, a video signal delayed by the vertically extended position in the field memory 12, and a video signal delayed by one field. ) And an arithmetic unit 19 which performs expansion operation in the vertical direction by inputting the output of the median processor 18, the output of the line memory 17, and the signal delayed by the vertical expansion position of the field memory 12.It is sex.

The vertical expansion operation of the screen by the aspect ratio converting apparatus of the television screen of the present invention configured as described above will be described with reference to FIGS. 5 to 8.

The clock generator 15 separates the horizontal synchronizing signal of the input video signal and logically combines the separated horizontal synchronizing signal to generate a clock pulse, which is input to the timing pulse generator 16.

The timing pulse generator 16 uses the input clock to provide a sampling clock for digital conversion of the analog digital converter 11, a clock for data storage and delayed output of the field memory 12, and a vertical expansion processor 13. The control clock for the expansion processing of the ()) and the sampling clock for the analog conversion of the digital analog converter 14 are generated and supplied to each circuit.

The analog digital converter 11 converts the input analog video signal into a digital video signal in accordance with a sampling clock supplied from the timing pulse generator 16 and outputs the digital video signal. The digital video signal is input to the field memory 12.

The field memory 12 stores the digital image signal in units of fields in accordance with the storage control clock supplied from the timing pulse generator 16, and the stored image signal is controlled in the vertical direction under the control of the timing pulse generator 16. A video signal delayed by an extended position and a video signal delayed by one field are output.

As illustrated in FIG. 6, the vertical expansion processor 13 performs one line delay processing of the video signal delayed by the position extended in the vertical direction by inputting the video signal delayed in the field memory 12, and the delayed video signal. And an intermediate value of the video signal delayed by one field delayed in the field memory 12 and the video signal delayed by the position extending in the vertical direction, and the intermediate value and the one-line and vertical delayed video signal are expanded and processed to expand the digital image. Output the signal.

That is, the video signal delayed by the position extending in the vertical direction output from the field memory 12 is input to the line memory 17 and is delayed by one line under the control of the timing pulse generator 16, and the delayed signal is The video signal delayed in the vertical direction and the one-field delayed video signal supplied to the input terminal X1 of the median processing unit 18 are output from the input terminal X2 of the median processing unit 18, respectively. X3) is supplied.

The median processor 18 obtains the median value of the video signal supplied to the input terminals X1, X2, and X3, and outputs the median value to the output terminal Y. The output intermediate value is output to the input terminal D1 of the calculation unit 19. Supplied.

FIG. 7A illustrates a configuration of the first embodiment of the median processing unit 18. The input video signal is a pair of adjacent video signals inputted to the minimum value calculating units 20, 21 and 22, respectively. As a result of comparing the adjacent video signals, a small value is output, and this video signal is input to the maximum value calculating section 23 (24) to output a large value, and this video signal is input to the maximum value calculating section 25 so that a large value is output. In the video signal supplied to the input terminals X1, X2 and X3, an intermediate value is output.

FIG. 7B is a configuration showing a second embodiment of the median processor 18, and input video signals are inputted to the maximum value calculator 26, 27, 28 by pairs of adjacent video signals, respectively. As a result of the comparison of adjacent video signals, a large value is output, and the video signal is input to the minimum value calculator 29 and 30 to output a small value. The video signal is input to the minimum value calculator 31 to output a small value. In the video signal supplied to the input terminals X1, X2 and X3, an intermediate value is output.

On the other hand, the video signal delayed by one line from the line memory 17 is input to the other input terminal D2 of the calculator 19, and the video signal delayed vertically from the field memory 12 to the other input terminal D3. Is input.

The calculation unit 19 performs the expansion operation of the video signal input to the input terminals D1, D2, and D3 by receiving the sequence control signal of the timing pulse generator 16 to receive the digital video signal extended in the vertical direction. Output

FIG. 6 shows an example of an extended operation executed by the calculating unit 19. The calculation given from the first line to the last line of the radix field is performed by the following equation.

In other words, the operation of CV1 = V1, CV3 = 1/2 * MV3 + 1/2 * V3, CV5 + MV5, CV7 = 1/2 * MV7 + 1/2 * V5 is repeated to make three lines of V1, V3, V5. This expands 33% to four lines: CV1, CV3, CV5, and CV7.

In the above formula, MV3, MV5 and MV7 are intermediate values.

In addition, the calculating unit 19 performs an operation given by the following equation from the first line to the last line of the even field.

That is, CV2 = 1/4 * MV2 + 3/4 * V2, CV4 = 3/4 * MV4 + 1/4 * V4, CV6 = 3/4 * MV6 + 1/6 * V4, CV8 = 1/4 * By repeating the operation of MV8 + 3/4 * V6, three lines of V2, V4, and V6 are expanded 33% to four lines of CV2, CV4, CV6, and CV8.

The extended video signal is supplied to the digital analog converter 14, and the digital analog converter 14 receives the sampling clock of the timing pulse generator 16 to convert the digital input signal into an analog video signal and output the analog video signal. .

When the vertical expansion is performed, the median processing unit 18 preserves the vertical transition in an area where the rapid transition of the input video signal occurs in the vertical direction. Therefore, even when the vertical expansion is performed, the transition portion of the video signal can be reproduced without damage. Will be.

8A to 8D show waveforms of the lines V0, V2, V4, and V6 of the video signal extending in the vertical direction according to the present invention. The image signal lines V1, V3, V5, and V7 are obtained, the median value is obtained using these two signal values, and the signal waveform finally extended and output is shown using the intermediate value and the delay signal.

Observing FIG. 8, in particular, when an image signal including a transition is input as shown in (b), one field delayed signal is output from the field memory 12, and therefore, the three signals input from the median processor 18. The intermediate value of, i.e., a signal having similarity among three signals is obtained and output. When the intermediate value outputted from the median processor 18 and the current video signal are calculated, the output video signal has a transition of 0 IRE. Since a signal appears, it is possible to prevent the degradation of image quality in the transition region.

As described above, according to the present invention, in the case of extending in the vertical direction to convert the aspect ratio of the television receiver screen, the vertical expansion is performed without damaging the vertical transition section of the video signal, thereby improving image quality and expressing high definition images. In wide-screen television receivers, even when zoom mode (33% vertical expansion) is performed, clear images can be obtained, thus improving the quality of video equipment.

Claims (4)

An analog digital converter for converting an input analog video signal into a digital signal, a digital video signal output from the analog digital converter in field units, and a video signal delayed by a vertically extended position and a video signal delayed by one field And a vertical expansion processor which performs line delay processing on the video signal output from the field memory, obtains an intermediate value, and performs a vertical expansion operation using the intermediate value and the delayed video signal. A digital analog converter for converting a digital video signal into an analog video signal and outputting an extended video signal, a clock generator for generating a clock required for system operation by using a synchronization signal of the input video signal, and the clock generator The analog signal received from the clock An aspect ratio converter of a television screen comprising a digital converter, a field memory, a vertical expansion processor, and a timing pulse generator for generating and supplying control pulses of a digital analog converter. The display apparatus of claim 1, wherein the vertical expansion processor is configured to delay one line of a video signal delayed by the vertical expansion position output from the field memory, a video signal delayed by the line memory, and a vertical expansion position by the vertical expansion position. A median processor which calculates and outputs a median value of the video signal and the one-field delayed video signal, and extends in the vertical direction by inputting a signal delayed by the output of the median processor, the output of the line memory, and the vertical expansion position of the field memory An aspect ratio converting apparatus for a television screen composed of a computing unit that performs arithmetic. 3. The apparatus of claim 2, wherein the median processor is configured to output a large value by comparing a minimum value calculator that outputs a small value by comparing the magnitude of an input video signal with a magnitude of the value output by the minimum value calculator; An aspect ratio converting apparatus for a television screen, comprising a maximum value calculating section that outputs large values by comparing the magnitudes of the values output from the maximum value calculating section. 3. The apparatus of claim 2, wherein the median processor comprises: a maximum value calculator for comparing a magnitude of an input video signal and outputting a large value; a minimum value calculator for comparing a magnitude of a value output from the maximum value calculator; An aspect ratio converting apparatus for a television screen comprising a minimum value calculating section for outputting a small value by comparing the magnitudes of the values output from the minimum value calculating section.