KR100282396B1 - Video Format Converter - Google Patents

Abstract

The present invention relates to an image format converting apparatus adapted to simplify the structure of a hardware, comprising: a first format that adds a format conversion ratio IN of an input image and a weight value alpha (n-1) of a previous image according to format conversion; By using the alpha (n-1) + IN output from the addition block and the format conversion ratio (OUT) of the output video, the format conversion weight of the current video (alpha), lead address increment (shift (n)), and A look-up table storage unit for outputting a weighted real value alpha_real used for extraction, a read address generator for outputting a read address value by an integer value shift (n) indicating the read address increase, and the read The FIFO memory sequentially outputs the input image data Data In corresponding to the address output value, and the delayed current image data I (n) from the next image data I (n + 1) output to the FIFO memory. 2nd padding to output A multiplication block for multiplying an output value I (n + 1) -I (n) and a weighted real value alpha_real (n) in the second addition block, and an output value of the multiplication block alpha_real (n) * (I (n + 1) −I (n) and a third addition block for outputting the final format-converted image data O (k) by summing up the current image data I (n). It is configured by.

Description

Video Format Converter

The present invention relates to an image format conversion apparatus, and more particularly, to an image format conversion apparatus adapted to simplify the structure of hardware.

Currently, one of the leading technologies in the video display device is digital TV.

In the case of digital TV, input video of various formats must be processed regardless of HDTV or SDTV, and output video must also be able to display images of various formats.

This requires a format converter for converting each input format into a desired output format.

Hereinafter, a conventional video format conversion apparatus will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a video format conversion apparatus of the related art.

FIG. 1 illustrates one of video format conversion apparatuses that are commonly used. The configuration is as follows.

A plurality of vertical N: M interpolators 11 connected in parallel, a plurality of horizontal N: M interpolators 12, and a MUX 13 connected in parallel are placed to convert various input formats into desired output formats.

For example, if the format of the input image is 720 x 1280, the vertical 2: 3 interpolator in the plurality of vertical N: M interpolators 11 and the horizontal 2: 3 interpolator in the multiple horizontal N: M interpolators 12 After performing interpolation at, the MUX 13 outputs an image of the 1080 × 1920 output format.

If the format of the input image is 480 × 720, interpolation is performed at a vertical 2: 3 interpolation part among several vertical N: M interpolators 11 and at a horizontal 3: 8 interpolation part among several horizontal N: M interpolators 12. After performing the conversion, the MUX 13 outputs a 1080 × 1920 output format image.

That is, interpolation blocks necessary for the plurality of vertical N: M interpolators 11 and the plurality of horizontal N: M interpolators 12 are added according to the format of the input image, and the image is converted and output in a desired format.

The conventional image format conversion apparatus has a problem in that additional hardware must be configured whenever a format of an input image is newly added.

To solve this problem, a format conversion method using some specific division has been proposed. However, since the complicated control logic is required and many gates are used, the hardware structure of the format conversion device is complicated.

The present invention has been made to solve such a problem of the conventional image format conversion apparatus, and the structure of hardware is obtained by using a lookup table without obtaining values necessary for the conversion of the image format using a divider. The object is to provide a simplified image format conversion apparatus.

1 is a block diagram of a conventional video format conversion device

2 is a block diagram of an apparatus for converting a format of a video signal according to the present invention;

Explanation of symbols for main parts of the drawings

21.26.28. First, second, and third addition blocks 22. Lookup table storage unit

23. Read address generator 24. FIFO memory

25. Delay block 27. Multiplication block

The video format conversion apparatus of the present invention simplifies the structure of the hardware by obtaining values required for the conversion of the image format using a look-up table. n-1)) using the alpha (n-1) + IN output from the first addition block and the format conversion ratio (OUT) of the output video, the format conversion weight (alpha) and read address increment (shift) of the current video. (n)), a lookup table storage unit for outputting a weighted real value (alpha_real) used for extraction of the next image output, and a read address value by an integer value (shift (n)) indicating the read address increase. A read address generation unit, a FIFO memory sequentially outputting input image data Data In corresponding to the read address output value, and a current image delayed from the next image data I (n + 1) output to the FIFO memoryA second addition block for subtracting and outputting data I (n), and multiplying the output value I (n + 1) -I (n) by the weighted real value alpha_real (n) in the second addition block The output data of the multiplication block and the output value alpha_real (n) * (I (n + 1) -I (n) and the current image data I (n)) of the multiplication block to be finalized and converted into final image data O and a third addition block for outputting (k)).

Hereinafter, an image format conversion apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an apparatus for converting a format of a video signal according to the present invention.

According to an embodiment of the present invention, when the ratio (format conversion ratio of the input image; IN) (format conversion ratio of the output image; OUT) between the size of the input image and the size of the output image is input, the format conversion weight of the next image is input. Image format conversion is implemented using a lookup table 22 that outputs (alpha (n)), lead address increment (shift (n)), and a real value (alpha_real (n)) used to extract the next output image. It is.

The configuration is a first that adds the format conversion ratio IN of the input image calculated by calculating the ratio between the size of the input image and the size of the output image and the weight value alpha (n-1) of the previous image according to the format conversion. The format conversion ratio of the output image calculated by calculating an addition block 21, alpha (n-1) + IN output from the first addition block 21, and a ratio between the size of the input image and the size of the output image. The lookup table storage unit 22 outputs the format conversion weight value alpha, the lead address increment shift (n), and the weighted real value alpha_real used to extract the next image output using (OUT). ), A read address generator 23 for generating a read address by an integer value shift (n) indicating an increase in read address output from the lookup table storage 22, and the read address generator ( Input image data Da corresponding to the address output value of 23) a current delayed by the processing unit of the video signal by the delay block 25 in the FIFO memory 24 sequentially outputting ta In) and the next video data I (n + 1) output to the FIFO memory 24; A second addition block 26 which subtracts and outputs image data I (n), an output value I (n + 1) -I (n) in the second addition block 26 and a lookup table storage unit A multiplication block 27 for multiplying and outputting a weighted real value alpha_real (n) used for extraction of the next output image output from (32), and an output value of the multiplication block 27 (alpha_real (n) * (I) A third addition block for outputting the final format-converted image data O (k) by summing the (n + 1) -I (n) and the current image data I (n) output from the delay block 25. And including 28.

The format conversion operation of the video format conversion device according to the present invention configured as described above is as follows.

First, when the ratio (format conversion ratio of the input image; IN) (format conversion ratio of the output image; OUT) between the size of the input image and the size of the output image is input, the lookup table storage unit 22 formats the next image. Outputs the transform weight (alpha), lead address shift (shift), and real value (alpha_real) used to extract the next output image.

That is, alpha (n + 1) = (alpha (n) + IN)% OUT,

shift (n + 1) = (alpha (n) + IN) / OUT,

The lookup table storage unit 22 outputs alpha_real (n + 1) = ((alpha (n) + IN)% OUT) / OUT = alpha (n + 1) / OUT.

Here, shift (n + 1) represents an increase in the read address from the current input image and has an integer value.

Alpha (n + 1) is an integer value that becomes an alpha value of the next input image.

alpha_real (n + 1) is the real value used to extract the next output image.

The image format conversion apparatus according to the present invention extracts the output image by the following equation.

The final output video data O (k) is

O (k) = alpha_real (n) * I (shift (n)) + (1-alpha_real (n)) * I (shift (n) +1))

It can be obtained as = I (shift (n)) + alpha_real (n) * (I (shift (n) + 1-I (shift (n))).

Here, alpha_real has a value in the range of 0 ≦ alpha_real <1.

For example, when the ratio of the input image size to the output image size is 2: 3, the output image is obtained as follows.

alpha (n + 1) = (alpha (n) + IN)% OUT,

shift (n + 1) = (alpha (n) + IN) / OUT,

alpha_real (n + 1) = ((alpha (n) + IN)% OUT) / OUT = alpha (n + 1) / OUT

O (k) = alpha_real (n) * I (shift (n)) + (1-alpha_real (n)) * I (shift (n) +1))

= I (shift (n)) + alpha_real (n) * (I (shift (n) + 1-I (shift (n)))

In this equation, alpha (0) = alpha_real (0) = shift (0) = 0, 0≤n <IN, 0≤k≤OUT, n, k, alpha (n), shift (n) are integers, alpha (n) is a real number.

Where O (0) = I (0),

alpha (1) = (alpha (0) + IN)% OUT = (0 + 2)% 3 = 2,

shift (1) = (alpha (0) + IN) / OUT = (0 + 2) / 3 = 0,

alpha_real (1) = alpha (1) / OUT = 2/3

O (1) = I (0) + 2/3 * (I (1) -I (0)).

And alpha (2) = (alpha (1) + IN)% OUT = (2 + 2)% 3 = 1,

shift (2) = (alpha (1) + IN) / OUT = (2 + 2) / 3 = 1,

alpha_real (2) = alpha (2) / OUT = 1/3,

O (2) = I (1) + alpha_real (2) * ((2) -I (1)).

And alpha (3) = (alpha (2) + IN)% OUT = (1 + 2)% 3 = 0,

shift (3) = (alpha (2) + IN) / OUT = (1 + 2) / 3 = 1,

O (3) = I (2).

O (4) = I (2) + 2/3 * (I (3) -I (2)), and O (5), O (6), ... (k) can be obtained.

The video format conversion device according to the present invention has the following effects.

The format conversion weights (alpha (n)), lead address increments (shift (n)), and real values (alpha_real (n)) used to extract the next output image, which are required for image format conversion, are not used by the divider. Using lookup tables has the effect of simplifying the configuration of the hardware.

In addition, while efficiently implementing the input image and the output image size conversion, there is an effect that no additional hardware configuration.

Claims (4)

Alpha (n-1) + IN output from the first addition block that adds the format conversion ratio IN of the input image and the weight value alpha (n-1) of the previous image according to the format conversion, and the format conversion ratio of the output image A lookup table storage unit for outputting a format conversion weight value (alpha), a lead address increment (shift (n)), and a weighted real value (alpha_real) used for extracting the next image output using (OUT); A read address generator for outputting a read address value by an integer value shift (n) indicating the read address increase; A FIFO memory sequentially outputting input image data Data In corresponding to the read address output value; A second addition block for subtracting and outputting the delayed current image data I (n) from the next image data I (n + 1) output to the FIFO memory; A multiplication block for multiplying and outputting an output value I (n + 1) -I (n) and a weighted real value alpha_real (n) in the second addition block; The output value alpha_real (n) * (I (n + 1) -I (n) and the current image data I (n)) of the multiplication block are summed to output the final format-converted image data O (k). And a third addition block. The method of claim 1, wherein the final output image data O (k) is O (k) = alpha_real (n) * I (shift (n)) + (1-alpha_real (n)) * I (shift (n) +1)) = I (shift (n)) + alpha_real (n) * (I (shift (n) + 1-I (shift (n))). The apparatus of claim 1, wherein alpha_real has a value in a range of 0 ≦ alpha_real <1. The apparatus of claim 1, wherein the delay block is configured between the FIFO memory and the second addition block to delay and output the image signal by a processing unit for format conversion.