KR100281904B1 - Forming method of a capacitor improving node slope - Google Patents
Forming method of a capacitor improving node slope Download PDFInfo
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- KR100281904B1 KR100281904B1 KR1019990001282A KR19990001282A KR100281904B1 KR 100281904 B1 KR100281904 B1 KR 100281904B1 KR 1019990001282 A KR1019990001282 A KR 1019990001282A KR 19990001282 A KR19990001282 A KR 19990001282A KR 100281904 B1 KR100281904 B1 KR 100281904B1
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- hole
- lower electrode
- noble metal
- layer
- capacitor
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 25
- 229910000510 noble metal Inorganic materials 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000009713 electroplating Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910002367 SrTiO Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052707 ruthenium Inorganic materials 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- 229910015801 BaSrTiO Inorganic materials 0.000 claims description 3
- 229910004491 TaAlN Inorganic materials 0.000 claims description 3
- 229910004166 TaN Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 3
- 229910010037 TiAlN Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 239000010970 precious metal Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910013641 LiNbO 3 Inorganic materials 0.000 claims description 2
- 229910004541 SiN Inorganic materials 0.000 claims description 2
- 229910004121 SrRuO Inorganic materials 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 229910052762 osmium Inorganic materials 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 150000003839 salts Chemical class 0.000 claims description 2
- 229910019899 RuO Inorganic materials 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000007772 electrode material Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Abstract
본 발명은 커패시터의 귀금속 전극을 형성하는 방법에 관한 것으로, 특히 귀금속 하부전극을 형성하기 위한 틀인 절연층 홀의 식각시 그 경사가 완전한 수직이 되지 못함에 따라 하부전극의 형상이 위로 갈수록 넓어지는 경사를 개선하기 위한 것이다. 본 발명은 하부전극을 형성하기 위한 절연층 홀에 단차 도포성이 나쁜 물질을 증착하고 홀 바닥에 증착된 경사개선층 물질을 제거하여 하부전극의 틀을 형성하는 것을 특징으로 한다.The present invention relates to a method of forming a noble metal electrode of a capacitor, and in particular, the inclination of the lower electrode becomes wider upward as the inclination of the insulating layer hole, which is a frame for forming the noble metal lower electrode, is not completely vertical. It is to improve. The present invention is characterized in that the frame of the lower electrode is formed by depositing a material having poor step coverage in the insulating layer hole for forming the lower electrode and removing the inclined improvement layer material deposited on the bottom of the hole.
본 발명에 따르면, 경사진 홀의 양 측벽에 단차 도포성이 나쁜 물질로 경사개선층을 형성함으로써, 기판 면에 대하여 수직 또는 아래로 갈수록 넓어지는 모양의 하부전극을 형성할 수 있고, 따라서 후속하는 유전체막 및 상부전극의 형성이 용이하게 된다.According to the present invention, by forming an inclined improvement layer with a material having poor step coverage on both sidewalls of the inclined hole, it is possible to form a lower electrode having a shape that extends vertically or downwardly with respect to the substrate surface, and thus a subsequent dielectric. It is easy to form the film and the upper electrode.
Description
본 발명은 커패시터를 형성하는 방법에 관한 것으로, 특히 높은 유전율을 가지는 물질을 유전체막으로 사용하고, 귀금속을 전극물질로 사용하는 커패시터의 전극 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming an electrode of a capacitor using a material having a high dielectric constant as the dielectric film and using a noble metal as the electrode material.
반도체 메모리 소자의 고집적화에 따라 커패시터가 차지하는 면적이 축소되면서 커패시터의 정전용량을 증가시키기 위해, 유전체막의 두께를 줄이는 방법, 하부전극을 원통(cylinder)형, 핀(fin)형, HSG(Hemispherical Grain)형 등의 3차원 구조로 형성하여 하부전극의 면적을 확대하는 방법, 유전체 물질로서 Ta2O5, BST((Ba,Sr)TiO3), PZT((Pb,Zr)TiO3), PLZT(Pb(La,Zr)TiO3) 등과 같은 높은 유전율을 갖는 물질을 사용하는 방법 등이 제시되었다.In order to increase the capacitance of the capacitor as the area occupied by the capacitor becomes smaller due to the higher integration of semiconductor memory devices, a method of reducing the thickness of the dielectric film, a cylinder type, a fin type, and a HSG (Hemispherical Grain) To expand the area of the lower electrode by forming a three-dimensional structure, such as a die, Ta 2 O 5 , BST ((Ba, Sr) TiO 3 ), PZT ((Pb, Zr) TiO 3 ), PLZT ( A method of using a material having a high dielectric constant such as Pb (La, Zr) TiO 3 ) and the like has been proposed.
이중 특히 BST, PZT, PLZT와 같은 물질을 유전체막으로 사용하는 경우, 그 전극은 Pt, Ru 등의 귀금속으로 형성하고 있는데, 이러한 귀금속 전극은 종래의 다결정 실리콘 전극에 비해 가격이 비싸고 원하는 패턴으로의 식각이 어렵기 때문에, 비교적 비용이 저렴하고 식각이 필요없는 전기도금법을 이용하여 전극을 형성하는 방법이 제안되었다.In particular, when a material such as BST, PZT, or PLZT is used as the dielectric film, the electrode is formed of a noble metal such as Pt or Ru, which is more expensive than a conventional polycrystalline silicon electrode and has a desired pattern. Since etching is difficult, a method of forming an electrode using an electroplating method which is relatively inexpensive and does not require etching has been proposed.
종래의 전기도금법을 이용하여 귀금속 전극을 형성하는 방법을 첨부도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of forming a noble metal electrode using a conventional electroplating method is as follows.
도 1에 도시된 바와 같이, 기판(10) 상에 전기도금시 시드층(Seed Layer)이 되는 도전층(12)을 형성하고, 그 위에 식각이 용이한 SiO2등의 절연층(14)을 적층한 후, 하부전극을 형성할 부분을 식각하여 홀(16)을 형성한다. 이어서, 도전층(12)을 음극으로 하고, 하부전극을 형성할 귀금속 물질을 양극으로 하여 귀금속염이 용해된 도금액에 담가 전기도금을 하여 시드층인 도전층(12) 상의 홀(16)에 귀금속을 채운다. 원하는 높이까지 귀금속을 채운 다음, 절연층(14)을 제거하면 도 2에 도시된 바와 같이, 도 1의 홀(16) 모양과 같은 귀금속 하부전극(18)이 완성된다.As shown in FIG. 1, a conductive layer 12, which becomes a seed layer during electroplating, is formed on the substrate 10, and an insulating layer 14 such as SiO 2 , which is easily etched, is formed thereon. After stacking, the hole 16 is formed by etching a portion to form the lower electrode. Subsequently, the conductive layer 12 is used as a cathode, the noble metal material for forming the lower electrode is used as an anode, and is immersed in a plating solution in which the noble metal salt is dissolved, followed by electroplating to form a precious metal in the hole 16 on the conductive layer 12 as a seed layer. Fills. After filling the noble metal to a desired height, and removing the insulating layer 14, as shown in FIG. 2, the noble metal lower electrode 18 like the shape of the hole 16 of FIG. 1 is completed.
이러한 전기도금법을 이용하여 귀금속 전극을 형성하는 방법은, 그 패턴 형성이 용이하고 높이도 임의로 조정이 가능하다는 장점이 있다. 그러나, 도 1과 같이 절연층(14)에 홀(16)을 형성하는 절연층 식각시, 홀의 경사(θ)가 정확히 90°가 되지 못하고 대략 85°이하로 형성되어, 그에 따라 하부전극(18)도 위로 갈수록 더 넓어지는 경사를 갖게 된다. 그러면, 이렇게 위로 갈수록 넓어지는 모양의 하부전극(18) 상에 계속하여 유전체막(20) 및 상부전극(22)을 형성하여 커패시터를 완성할 때, 도 3에 도시된 바와 같이, 하부전극의 측면과 아래쪽에 유전체나 상부전극 물질이 제대로 증착되지 않아 전극의 접촉면적이 감소하거나, 상하부전극이 단락되는 등의 문제가 있다. 특히, 이러한 문제는 하부전극(18)의 높이가 높거나 전극간 간격이 좁아지면 더욱 심각해진다.The method of forming the noble metal electrode using such an electroplating method has an advantage that the pattern formation is easy and the height can be arbitrarily adjusted. However, as shown in FIG. 1, when the insulating layer is etched to form the hole 16 in the insulating layer 14, the inclination θ of the hole is not formed to be exactly 90 ° but is formed to be approximately 85 ° or less, thereby lower electrode 18. ) Also has a slope that is wider as you go up. Then, when the dielectric film 20 and the upper electrode 22 are continuously formed on the lower electrode 18 having a shape that expands upward, the side of the lower electrode, as shown in FIG. 3, is completed. There is a problem that the contact area of the electrode is reduced or the upper and lower electrodes are shorted because the dielectric material and the upper electrode material are not properly deposited on and below. In particular, this problem becomes more serious when the height of the lower electrode 18 is high or the spacing between electrodes is narrow.
본 발명이 이루고자 하는 기술적 과제는, 기판 면에 대하여 수직 또는 아래로 갈수록 넓어지는 귀금속 전극을 형성할 수 있는 커패시터의 형성방법을 제공하는 것이다.The technical problem to be achieved by the present invention is to provide a method of forming a capacitor capable of forming a noble metal electrode that is wider toward the substrate surface or vertically downward.
도 1 내지 도 3은 종래의 방법에 따라 귀금속 커패시터를 형성하는 과정을 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a process of forming a noble metal capacitor according to a conventional method.
도 4a 내지 도 8b는 본 발명의 방법에 따라 귀금속 커패시터를 형성하는 과정을 도시한 단면도들이다.4A through 8B are cross-sectional views illustrating a process of forming a noble metal capacitor according to the method of the present invention.
상기의 기술적 과제를 달성하기 위하여 본 발명에 따른 커패시터의 형성방법은 다음과 같다.In order to achieve the above technical problem, a method of forming a capacitor according to the present invention is as follows.
먼저, 시드층인 도전층 상에 절연층을 적층하고, 식각하여 하부전극이 형성될 영역의 도전층을 노출하는 홀을 형성한다. 상기 홀에 단차 도포성이 나쁜 물질을 증착하여 상기 물질이 홀 측벽에 위로 갈수록 두껍게 증착된 경사개선층을 형성하고, 홀 바닥에 증착된 경사개선층 물질을 제거하여 하부전극의 틀을 형성한다. 이어서, 양 측벽에 경사개선층이 형성된 홀 내부에 귀금속을 채우고, 절연층과 경사개선층을 제거하여 커패시터의 하부전극을 완성한다.First, an insulating layer is stacked on the conductive layer, which is a seed layer, and is etched to form holes for exposing the conductive layer in the region where the lower electrode is to be formed. By depositing a material having poor step coatability in the hole, the material is formed on the sidewall of the hole to form an inclined improvement layer that is thicker, and removes the inclined improvement layer material deposited on the bottom of the hole to form a frame of the lower electrode. Subsequently, the noble metal is filled in the hole in which the slope improvement layers are formed on both sidewalls, and the insulating layer and the slope improvement layer are removed to complete the lower electrode of the capacitor.
여기서, 상기 경사개선층 물질로는, SiO2, SiN, SiON, BPSG, TiO2, AlN, SrTiO3, BaSrTiO3, Ti, TiN, TiSiN, TiAlN, TaN, TaAlN 또는 TaSiN이 바람직하다.Here, in the inclined-improvement layer material, SiO 2, a SiN, SiON, BPSG, TiO 2, AlN, SrTiO 3, BaSrTiO 3, Ti, TiN, TiSiN, TiAlN, TaN, TaAlN, or TaSiN is preferred.
이와 같이, 본 발명의 방법에 따르면, 절연층의 식각에 의해 형성된 하부전극의 틀인 홀의 양 측벽에 단차 도포성이 나쁜 물질로 경사개선층을 형성함으로써, 기판 면에 대하여 수직이거나 또는 아래로 갈수록 넓어지는 하부전극을 형성할 수 있다.As described above, according to the method of the present invention, an inclination improvement layer is formed on the both sidewalls of the hole, which is a frame of the lower electrode formed by the etching of the insulating layer, to form an inclined improvement layer made of a material having poor step coverage. It can form a lower electrode.
이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도 4a 및 도 4b에 도시된 바와 같이, 기판(40) 상에 시드층으로서 도전층(42)을 적층하고, 그 위에 절연층(44, 44')을 적층한다. 사진식각공정을 통하여 하부전극이 형성될 영역의 도전층(42)을 노출하도록 절연층(44, 44')을 식각하여 홀을 형성한다. 이때, 홀의 경사는 도 1과 마찬가지로 완전한 수직이 되지 못하고 대략 85°내외의 경사를 갖게 된다. 도 4a는 홀이 좀더 완만한 경사를 갖는 경우를 도시한 것이고, 도 4b는 홀이 좀더 수직에 가깝게 가파른 경사를 갖는 경우를 도시한 것이다.First, as shown in FIGS. 4A and 4B, the conductive layer 42 is laminated as a seed layer on the substrate 40, and the insulating layers 44 and 44 ′ are stacked thereon. Through the photolithography process, holes are formed by etching the insulating layers 44 and 44 'to expose the conductive layer 42 in the region where the lower electrode is to be formed. At this time, the inclination of the hole does not become completely vertical as in FIG. 1 and has an inclination of about 85 °. FIG. 4A illustrates the case where the hole has a more gentle slope, and FIG. 4B illustrates the case where the hole has a steeper slope closer to the vertical.
이어서, 전면에 단차 도포성이 나쁜 물질을 증착한다. 단차 도포성이 나쁜 물질로는 SiO2, SiN, SiON, BPSG, TiO2, AlN, SrTiO3또는 BaSrTiO3등의 절연물질, 또는 Ti, TiN, TiSiN, TiAlN, TaN, TaAlN 또는 TaSiN 등의 도전물질을 들 수 있다. 그러면, 단차 도포성이 나쁜 물질은 절연층 홀의 상부 모서리에서 더 두텁게 증착되어 경사개선층(46)을 형성하고, 도 5a에 도시된 바와 같이, 전체적으로 경사가 수직인 홀을 얻을 수 있다. 이 때, 상기 단차 도포성이 나쁜 물질의 증착시간을 늘리거나, 단차 도포성이 더욱 나쁜 물질을 사용하는 경우, 또는 홀의 경사가 도 4b와 같이 더 가파른 경우에는, 도 5b에 도시된 바와 같이, 절연층 홀의 상부 모서리에 더욱 두텁게 증착되어(46'), 전체적인 홀의 모양은 아래로 갈수록 넓어지는 형태가 된다.Subsequently, a material having poor step coatability is deposited on the entire surface. Conductive material, such as a step coating property is bad materials include SiO 2, SiN, SiON, BPSG, TiO 2, AlN, SrTiO 3 or BaSrTiO 3, etc. of the insulating material, or Ti, TiN, TiSiN, TiAlN, TaN, TaAlN, or TaSiN Can be mentioned. Then, the material having poor step coverage is deposited thicker at the upper edge of the insulating layer hole to form the slope improvement layer 46, and as shown in FIG. 5A, a hole having a vertical slope as a whole can be obtained. In this case, when the deposition time of the material having poor step coverage is increased, or when a material having poor step coverage is used, or when the slope of the hole is steeper as shown in FIG. 4B, as shown in FIG. 5B, The thicker the deposition of 46 'at the top edge of the insulating layer hole, the overall shape of the hole becomes wider downwards.
이어서, 도전층(42)을 식각정지층으로 하여 경사개선층 물질을 전면 에치백하여 홀의 바닥에 증착된 경사개선층 물질을 제거하면, 도 6a 또는 도 6b와 같이 절연층 홀의 양 측벽에만 경사개선층이 스페이서(48, 48')의 형태로 남게 된다. 이때, 절연층(44, 44')의 상면에도 경사개선층이 약간 남을 수 있다.Subsequently, when the inclination improvement layer material is etched back to remove the inclination improvement layer material deposited on the bottom of the hole by using the conductive layer 42 as an etch stop layer, the inclination improvement is performed only on both sidewalls of the insulation layer holes as shown in FIG. 6A or 6B. The layer remains in the form of spacers 48, 48 ′. At this time, the inclination improvement layer may remain slightly on the upper surfaces of the insulating layers 44 and 44 '.
이어서, 도 7a 또는 도 7b에 도시된 바와 같이, 양 측벽에 경사개선층 스페이서(48, 48')가 형성된 홀에, 노출된 도전층(42)을 시드층으로 하고 전기도금법으로 하부전극 물질을 도금하여 채운다. 이때 하부전극 물질로는, 특히 유전체막으로서 높은 유전율을 가지는 물질을 사용하는 경우에, Pt, Rh, Ru, Ir, Os 또는 Pd 등의 귀금속으로 하는 것이 바람직하다. 전기도금은 상기 귀금속을 포함하는 금속염, 예컨대 RuNOCl3가 용해된 도금액에 상기 귀금속(Ru)을 양극으로 하고, 도전층(42)을 음극으로 하여 도금되는 하부전극 패턴(50 또는 50')이 원하는 높이로 될 때까지 행한다.Subsequently, as shown in FIG. 7A or 7B, the exposed conductive layer 42 is used as a seed layer in the hole in which the slope improvement spacers 48 and 48 'are formed on both sidewalls, and the lower electrode material is electroplated. Plated and filled. The lower electrode material is preferably a precious metal such as Pt, Rh, Ru, Ir, Os, or Pd, especially when a material having a high dielectric constant is used as the dielectric film. Electroplating is desired by the lower electrode pattern 50 or 50 'which is plated by using the noble metal (Ru) as an anode and the conductive layer 42 as a cathode in a plating solution in which the noble metal is contained, for example, RuNOCl 3. Until it reaches a height.
이어서, 경사개선층(48, 48') 및 절연층(44, 44')을 습식식각 등으로 제거하면 도 8a 또는 도 8b와 같이, 기판 면에 대하여 수직인 또는 아래로 갈수록 넓어지는 하부전극(50, 50')이 얻어진다.Subsequently, when the inclination improvement layers 48 and 48 'and the insulating layers 44 and 44' are removed by wet etching, the lower electrode (which is wider or perpendicular to the substrate surface as shown in FIG. 8A or FIG. 8B) is removed. 50, 50 ') is obtained.
이어서, 도시하지는 않았지만, 하부전극(50, 50') 상에 통상적인 방법으로 유전체막 및 상부전극을 형성함으로써 커패시터를 완성한다. 이때 유전체로서는 Ta2O5, Al2O3, SrTiO3, BaTiO3, (Ba,Sr)TiO3, PbTiO3, (Pb,Zr)TiO3, Pb(La,Zr)TiO3, Sr2Bi2NbO9, Sr2Bi2TaO9, LiNbO3또는 Pb(Mg,Nb)NbO3등의 높은 유전율을 가지는 물질을 사용하는 것이 바람직하고, 상부전극으로서는 Pt, Ru, Ir, Os, Pd 등의 귀금속이나, RuO2, IrO2, SrRuO3, BaSrRuO3, CaSrRuO3등의 귀금속 산화물을 사용하는 것이 바람직하다.Subsequently, although not shown, a capacitor is completed by forming a dielectric film and an upper electrode on the lower electrodes 50 and 50 'in a conventional manner. In this case, Ta 2 O 5 , Al 2 O 3 , SrTiO 3 , BaTiO 3 , (Ba, Sr) TiO 3 , PbTiO 3 , (Pb, Zr) TiO 3 , Pb (La, Zr) TiO 3 , Sr 2 Bi It is preferable to use a material having a high dielectric constant such as 2 NbO 9 , Sr 2 Bi 2 TaO 9 , LiNbO 3, or Pb (Mg, Nb) NbO 3 , and Pt, Ru, Ir, Os, Pd or the like as the upper electrode. to use a noble metal oxide, such as noble metal or, RuO 2, IrO 2, SrRuO 3, BaSrRuO 3, CaSrRuO 3 are preferred.
이상 상술한 바와 같이, 본 발명에 따르면, 경사진 홀의 양 측벽에 단차 도포성이 나쁜 물질로 경사개선층을 형성함으로써, 기판 면에 대하여 수직 또는 아래로 갈수록 넓어지는 모양의 하부전극을 형성할 수 있고, 따라서 후속하는 유전체막 및 상부전극의 형성이 용이하게 된다.As described above, according to the present invention, the inclined improvement layer is formed of a material having poor step applicability on both sidewalls of the inclined hole, thereby forming a lower electrode having a shape that becomes wider or vertically downward with respect to the substrate surface. Therefore, subsequent formation of the dielectric film and the upper electrode becomes easy.
Claims (6)
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