KR100279259B1 - Array structure of LCD - Google Patents

Abstract

The present invention discloses an array structure of a liquid crystal display device in which a liquid crystal display device can maintain [Delta] Vp for determining an image quality when misalignment occurs.

In the disclosed invention, a unit pixel in the form of an active matrix is defined in which a pair of gate bus lines and a pair of data bus lines are arranged crosswise. The pixel electrodes are disposed in unit pixels, respectively. The thin film transistors are provided at intersections of the gate bus lines and the data bus lines, respectively, to operate the pixel electrodes. A pair of gate bus lines defining unit pixels are branched from the same source and receive the same scan selection signal. A pair of gate bus lines defining a unit pixel and a pair of thin film transistors formed at an intersection with the data bus line simultaneously operate the corresponding pixel electrode in the unit pixel. When the misalignment occurs, the area where the individual thin film transistors and the gate bus lines overlap is changed, but the overall overlap area is maintained based on the pair of thin film transistors.

Description

Array structure of liquid crystal display

The present invention relates to an array structure of a liquid crystal display device, and more particularly, to an array structure of a liquid crystal display device capable of preventing the parasitic capacitance value from being changed due to misalignment during manufacturing of the liquid crystal display device.

In general, ΔVp, which determines the image quality of the liquid crystal display, is a value at which the voltage applied to the pixel electrode drops when the gate voltage Vg applied to the liquid crystal display is changed from high to low. . If the ΔVp deviates from a predetermined reference value, flicker or afterimages occur on the screen.

ΔVp is represented as a function of capacitances formed in the liquid crystal display, as shown in Equation 1 below.

ΔVp = VgCgs / (Cst + C _LC + Cgs) -------- (Equation 1)

Vg: gate voltage

Cgs: capacitance of the parasitic capacitor formed at the portion overlapping the gate bus line and the source electrode

C _LC : Liquid Crystal Capacitance

Cst: subcapacitance capacitance

Here, ΔVp has a close influence on the size of the parasitic capacitance C _gs , and when the parasitic capacitance C _gs is increased, ΔVp is also increased to affect the image quality.

In general, several lithography processes are performed in the process of forming the liquid crystal display. In this process, misalignment is likely to occur.

In particular, if a slight misalignment occurs in the process of patterning the source electrode, the overlapping area between the source electrode and the gate bus line is changed, so that the parasitic capacitance Cgs is changed. For this reason, (DELTA) Vp value changes and the image quality of a liquid crystal display device falls.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to keep the ΔVp value constant so that the parasitic capacitance value does not change even when misalignment occurs.

1 is a plan view of a liquid crystal display device according to the present invention;

FIG. 2 is an enlarged plan view of one pixel of FIG. 1; FIG.

(Explanation of symbols for the main parts of the drawing)

10: lower panel 11a, 11b: Mo gate bus line

11a-1, 11a-2, 11b-1, 11b-2: zagate bus lines

12a, 12b: data bus line 13: pixel electrode

14 storage electrode 15 thin film transistor

15a: drain electrode 15b: source electrode

In order to achieve the above object of the present invention, according to an embodiment of the present invention, a unit pixel in the form of an active matrix is defined by a pair of gate bus lines and a pair of data bus lines arranged crosswise. The pixel electrodes are disposed in unit pixels, respectively. The thin film transistors are provided at intersections of the gate bus lines and the data bus lines, respectively, to operate the pixel electrodes. A pair of gate bus lines defining unit pixels are branched from the same source and receive the same scan selection signal. A pair of gate bus lines defining a unit pixel and a pair of thin film transistors formed at an intersection with the data bus line simultaneously operate the corresponding pixel electrode in the unit pixel. When the misalignment occurs, the area where the individual thin film transistors and the gate bus lines overlap is changed, but the overall overlap area is maintained based on the pair of thin film transistors.

In the present invention, the gate bus line is branched into a pair of child gate bus lines, and the child gate bus lines branched from the one gate bus line are arranged in parallel at a first interval. Child gate bus lines having different sources are arranged in parallel at a second interval. The data bus lines are arranged crosswise with the gate bus lines. The unit pixels are limited to the child gate bus lines branched from one gate bus line and a pair of data bus lines having different origins, and each unit pixel is spaced apart at the second interval in the column direction. The pixel electrodes are disposed in respective unit pixels, and the thin film transistors are provided at intersections of the gate bus lines and the data bus lines, respectively, and are provided in pairs per unit pixel to operate one pixel electrode. When the misalignment occurs, the area where the individual thin film transistors and the gate bus lines overlap is changed, but the overall overlap area is maintained based on the pair of thin film transistors.

According to the present invention, the pixel electrode is controlled as a pair of thin film transistors, and the thin film transistors are provided at positions symmetric with each other. Here, when misalignment occurs, since the thin film transistors are formed symmetrically with each other, even if the overlap area of the source electrode and the gate bus line of one thin film transistor is reduced, the overlap area is relatively increased in the other thin film transistor, so that the overall overlap is achieved. The area does not change.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an enlarged view of one pixel of FIG. 1.

Referring to FIG. 1, the lower panel 10 is defined as a cell array area CA and a peripheral area P. Referring to FIG. For example, in this embodiment, two gate bus lines 11a and 11b and two data bus lines 12a and 12b are alternately arranged on the lower panel 10. Here, the gate bus lines 11a and 11b are branched into two bus lines 11a-1, 11a-2 and 11b-1 and 11b-2, respectively, in the vicinity of the outside of the cell array region CA. Here, the gate bus lines 11a and 11b in the peripheral region are referred to as mother gate bus lines, and the gate buses branching from the mother gate bus lines 11a and 11b into two at the edges of the cell region CA. Lines 11a-1, 11a-2 and 11b-1, 11b-2 are called child gate bus lines. A pair of self gate bus lines 11a-1, 11a-2 and 11b-1, 11b-2 branched from one mother gate bus line 11a, 11b are spaced apart by a first interval d1, Extends in parallel. Subsequently, the sub gate bus lines 11a-2 and 11 b-1 which are branched from different parent gate bus lines 11 a and 11 b and arranged adjacent to each other have a second interval d 2 less than the first interval d 1. It extends in parallel. Here, the first interval d1 is about the long width of the unit cell, and the second interval d2 is the minimum distance that can insulate the gate bus lines. Accordingly, the subpixel p is adjacent to the sub gate bus lines 11a-1, 11a-2 and 11b-1, 11b-2 branched from one mother gate bus line 11a, 11b. It is a space surrounded by a pair of data bus lines 12a and 12b.

The pixel electrodes 13 are disposed in the unit pixels P, respectively. In this case, the pixel electrode 13 is insulated from the gate bus lines 11a-1, 11a-2 and 11b-1 and 11b-2 and the data bus lines 12a and 12b that define the unit pixel P. Characters are placed a minimum distance that can be secured.

Storage electrodes 14 forming the storage capacitors of the liquid crystal display are respectively formed in the unit pixels P to overlap with the pixel electrodes 13, and the storage electrodes 14 on one row are all formed. It is connected, taking the form of a line. Preferably, the gate gate lines 11a-1, which are parallel to the gate gate lines 11a-1, 11a-2 and 11b-1, 11b-2 and branched to the same gate gate lines 11a, 11b, 11a-2 and 11b-1, 11b-2).

In the thin film transistor 15 which selectively turns on / off the pixel electrode 13, the gate gate lines 11a-1, 11a-2 and 11b-1, 11b-2 intersect with the data bus lines 12a and 12b. It is formed at each point. Therefore, two thin film transistors 15 for operating one pixel electrode 13 are paired. The thin film transistor 15 is drained from one side of the data bus lines 12a and 12b and overlaps the gate gate lines 11a-1, 11a-2 and 11b-1, 11b-2 with a predetermined portion. 15a). The drain electrode 15a is formed at a portion corresponding to the second gap d2 and overlaps with one side surfaces of the gate gate lines 11a-2 and 11b-1 parallel to each other at the second gap d2. . Here, the drain electrode 15a is a "T" shaped rotated about 270 degrees. Also, the thin film transistor 15 includes a source electrode 15b overlapping the gate bus lines 11a-1, 11a-2 and 11b-1, 11b-2 and contacting the pixel electrode 13. The source electrode 15b overlaps the gate bus lines 11a-1, 11a-2 and 11b-1, 11b-2, and is formed to face the drain electrode 15a at a predetermined distance. Although not described in detail in the drawings, each of the gate bus lines 11a-1, 11a-2 and 11b-1, 11b-2 where the thin film transistors 15 are formed is provided with a channel layer and an etch stopper layer, respectively. The drain electrode 15a and the source electrode 15b overlap with each other.

Hereinafter, the operation according to the embodiment of the present invention having the above-described configuration will be described.

The scan selection signal is applied to one of the selected gate bus lines 11a. The scan selection signals are also applied to the pair of gate gate lines 11a-1 and 11a-2 branched from the parent gate bus line 11a to which the scan signal is applied. Then, all of the thin film transistors 15X1 and 15X2 having the gate gate lines 11a-1 and 11a-2 as the gate electrodes are turned on. Accordingly, the pixel electrode 13 is controlled on / off by a pair of thin film transistors 15X1 and 15X2 provided in the unit pixel P portion thereof.

At this time, in the process of forming the data bus lines 12a and 12b, the overlapping area between the source electrode 15b and the gate bus line 12 determining the ΔVp value is changed due to a predetermined misalignment. As mentioned in

However, with the same configuration as in the embodiment of the present invention, even if misalignment occurs, the area where the source electrodes 15b and the gate gate lines 11a-1 and 11a-2 overlap in the pair of thin film transistors It is virtually unchanged. That is, even when misalignment occurs, the pair of thin film transistors 15X1 and 15X2 controlling one pixel electrode 13 are simultaneously moved in a predetermined direction, so that the source electrode 15a of one thin film transistor 15X1 is moved due to misalignment. Even if the overlap area is reduced, the overlap area is increased in the other thin film transistor 15X2, and the relatively reduced area is compensated.

In more detail, with reference to FIG. 2, a portion indicated by a solid line is an array of a liquid crystal display device when no misalignment has occurred, and a portion indicated by a dotted line shows an array of the liquid crystal display device when a misalignment occurs. Let's look at the source electrode 15b (the source electrode when the misalignment occurs) indicated by the dotted line. When misalignment occurs, in the thin film transistor 15X1 of the upper portion of the pixel electrode 13, the source electrode 15b has an area that overlaps with the gate bus line 11a-1 more than when misalignment does not occur. Increment by y ". On the other hand, the source electrode 15b in the thin film transistor 15X2 in the lower portion of the pixel electrode 13 is relatively reduced in area of overlap with the gate bus line 11a-2 by "y". Accordingly, even if misalignment occurs, the area of the source electrode 15b overlapping with the gate bus lines 11a-1 and 11a-2 remains unchanged.

Therefore, the parasitic capacitance Cgs does not change, so that a constant ΔVp can be maintained.

The present invention is not limited only to the above embodiment. In the present exemplary embodiment, the pixel electrode is formed to be spaced apart from the gate bus line and the data bus line constituting the unit cell by a predetermined distance, but the present invention is not limited thereto. The same applies.

As described in detail above, according to the present invention, the pixel electrode is controlled as a pair of thin film transistors, and the thin film transistors are provided at positions symmetric with each other. Here, when misalignment occurs, since the thin film transistors are formed symmetrically with each other, even if the overlap area of the source electrode and the gate bus line of one thin film transistor is reduced, the overlap area is relatively increased in the other thin film transistor, so that the overall overlap is achieved. The area does not change.

Accordingly, since the parasitic capacitance determined by the overlap area is kept constant even when misaligned, ΔVp can be kept constant.

Therefore, the image quality of the liquid crystal display device is improved.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (7)

A unit pixel in the form of an active matrix in which a pair of gate bus lines and a pair of data bus lines are alternately arranged and defined; Pixel electrodes disposed on the unit pixels, respectively; A thin film transistor disposed at an intersection of the gate bus line and the data bus line, and configured to operate the pixel electrode; The pair of gate bus lines defining the unit pixel branch from the same source to receive the same scan selection signal, A pair of gate bus lines defining the unit pixel and a pair of thin film transistors formed at an intersection with the data bus line simultaneously operate the corresponding pixel electrode in the unit pixel. The overlapping area of the thin film transistor and the gate bus line is changed when misalignment occurs, but the overall overlap area is maintained based on a pair of thin film transistors. The method of claim 1, wherein the unit pixels are branched with one source and arranged perpendicularly to the pair of gate bus lines that are scanned and selected by the same signal, and to the pair of gate bus lines. And a data bus line extending in parallel, wherein the data bus lines have different sources. 3. The gate bus line of claim 2, wherein the gate matrix lines of the active matrix unit pixels are spaced apart by a predetermined distance from each other at different sources and branched from different sources to define different unit pixels. An array structure of a liquid crystal display device, characterized in that there is a distance by a predetermined distance. The thin film transistor of claim 1, wherein the thin film transistor is positioned at an interval between unit pixels in the column direction, and is overlapped with the gate bus line, the drain electrode being drawn from the data bus line and overlapping the gate bus line. An array structure of a liquid crystal display device, wherein the source electrode and the gate bus line are in contact with a pixel electrode and opposed to the drain electrode at a predetermined distance. A plurality of gate bus lines, each gate bus line branched into a pair of child gate bus lines, the child gate bus lines branching from the one gate bus line at a first interval The gate gate lines arranged in parallel and having different sources include: gate bus lines arranged in parallel at a second interval; A data bus line intersecting with the gate bus line; A unit pixel defined by a child gate bus line branched from the one gate bus line and a pair of data bus lines of different origins, wherein each unit pixel is spaced apart from the second interval in a column direction pixel; A pixel electrode disposed in each of the unit pixels; A thin film transistor disposed at an intersection of the gate bus line and the data bus line, and provided in pairs per unit pixel to operate one pixel electrode; The overlapping area of the thin film transistor and the gate bus line is changed when misalignment occurs, but the overall overlap area is maintained based on a pair of thin film transistors. 6. The thin film transistor of claim 5, wherein the thin film transistor is disposed in the second gap portion and is drained from the data bus line to overlap the self gate bus line, the thin film transistor overlaps the gate bus line, and contacts the pixel electrode. And the source electrode and the gate bus line, which are opposed to the drain electrode at a predetermined distance, as the gate electrode. The array of liquid crystal display of claim 6, wherein the drain electrode is overlapped with two self gate bus lines adjacent to each other in the column direction and adjacent to each other and having different sources. rescue.