KR100276650B1 - Failure inspection and analysis method of semiconductor device - Google Patents

Abstract

The present invention discloses a defect inspection and analysis method for semiconductor devices. The inspection method can be continued by checking if the failure of each vector affects the failure of the next vector and if it is a continuous vector, it is divided into a restart vector and a continuing vector. If the restart vector is a restart vector, Masking this bad vector and performing the check again from the beginning. The failure analysis method for the continuous vector is performed by discriminating whether or not the vector is defective. If it is a bad vector and it is not a continuous vector, it is determined whether or not the vector is necessary for analysis. Continue the scan from the inserted analysis vector, and if it is bad and restart vector, mask the bad vector and continue to scan from the next vector. The failure analysis method for the restart vector is performed by discriminating whether or not the vector is defective analysis. If it is defective and the restart vector is the judgment of whether or not the analysis is necessary, if analysis is necessary, Performs inspection from 1 vector to analysis vector and masks the bad vector and the analysis vector. And, if it is not bad and it is still a vector and it is not a vector that needs analysis, continue the inspection from the next vector. Therefore, defect inspection and analysis can be performed at the same time, and defects due to defects in the previous vector can be eliminated.

Description

Failure inspection and analysis method of semiconductor device

The present invention relates to a defect inspection and analysis method for a semiconductor device, and more particularly, to a defect inspection and analysis method for a semiconductor device having a sequential circuit.

Testing of semiconductor devices involves connecting the pins of a semiconductor device to be tested to a test equipment, applying a given signal to the input pins, and measuring whether the desired signal is output at the output pins. As a result of the measurement, if the desired signal is output, it is determined to be a normal device, otherwise it is judged to be a defective device. If the desired output of the semiconductor device determined to be defective is compared with the measured output, the cause and position of the defect can be found.

1 is a schematic block diagram for explaining a method of inspecting a semiconductor device, which comprises an inspection equipment 10, a semiconductor device 20, and a tester 30.

The tester 30 is a device for storing an inspection pattern of the semiconductor device 20 and measuring whether an output pattern is accurately output by applying an input pattern of each vector to a semiconductor device. The semiconductor device 20 is placed on the inspection equipment 10.

A conventional inspection method of a semiconductor device will be described below.

First, let the input and output characteristics of a semiconductor device having six input pins and three output pins be as shown in the following table.

(Table 1)

IN1 IN2 IN3 IN4 IN5 IN6 OUT1 OUT2 OUT3 One 0 One 0 One 0 0 One 0 The first vector One 0 0 One 0 One One One 0 The second vector One 0 0 One One One One One 0 Third vector One 0 0 One 0 0 One 0 One Fourth vector ... ... ... ... ... ... ... ... ... ... One One One One One One One One One N-th vector

The above table defines the test pattern, the input signal from IN1 to IN6, the output signal from OUT1 to OUT3, and the first to the n-th vectors are defined as vectors.

The tester applies input signals 1, 0, 1, 0, 1, 0 to the input pins of the first vector and measures whether the output signals 0, 1, 0 from the output pins of the semiconductor device are correctly output, If it is not the same, it is judged to be defective. In this way, the second to n-th vectors are examined.

In the case of the combinational circuit, since each vector is independent, the vector may be applied regardless of the order. Also, since the defects of the respective vectors are independent, it is easy to find the cause and location of defects. However, in the case of an order circuit, the first vector to the n-th vector must be applied in order, and the failure of the preceding vector may cause the failure of the next vector. Therefore, , It is not possible to accurately determine whether or not the defect is caused by the defect of the preceding vector, and it is not easy to find the cause and location of the defect.

SUMMARY OF THE INVENTION An object of the present invention is to provide a defect inspection method for a semiconductor device which can accurately determine a defect caused by an actual circuit of a semiconductor device.

It is another object of the present invention to provide a method for analyzing failure of a semiconductor device capable of analyzing a cause and position of a defect in the semiconductor device.

According to another aspect of the present invention, there is provided a defect inspection method for a semiconductor device, the defect inspection method using a semiconductor device having a predetermined number of input pins and output pins, and an inspection pattern from a first to an n-th vector of the semiconductor device, A method for inspecting a semiconductor device having a tester for identifying a semiconductor device, the method comprising: a measurement step of applying an input signal of the first vector to the predetermined number of input pins and measuring an output signal from the output pins; And if the vector is a bad vector and a restart vector, masking the bad vector and proceeding to the first measurement step, and if the measured vector is not a bad vector and is a continuing vector, And if it is not the n-th vector, the input signal of the next vector is multiplied by the predetermined number of Force applied to the pins and is characterized in that it includes a second determination and inspection and measuring an output signal from said output pins, and then proceeds to the first determining step and inspection.

According to another aspect of the present invention, there is provided a semiconductor device failure analysis method comprising: a semiconductor device having a predetermined number of input pins and output pins; and a test pattern from the first to n-th vectors of the semiconductor device, A method for analyzing failure of a semiconductor device having a tester for inspecting and analyzing defects using a predetermined number of analysis vectors for each of vectors required for analysis in the event of failure, the method comprising the steps of: The method comprising: a first measurement step of applying to the input pins and measuring an output signal from the output pins; a determination step of determining whether the measured vector is a bad vector; if the determination vector is not a bad vector, And if it is not the n-th vector, the input signal of the next vector is applied to the predetermined number of input pins A first checking step of measuring an output signal from the first output pins and proceeding to the determining step, and if it is determined to be a defective vector and a restart vector, masking the defective vector and proceeding to the first checking step Determining whether the defective vector is a vector requiring analysis if the defective vector is a continuing vector as a result of the determination, and inserting a predetermined number of analysis vectors for the defective vector after the defective vector if analysis is required And if it is determined that the analysis is not necessary, the process proceeds to the first inspection step, and if it is determined in the first inspection step that the first to n < th > And a second checking step of sequentially applying and measuring the vector of the continuity vector; And a second measurement step of applying an input signal of the first vector to the predetermined number of input pins and measuring an output signal from the output pins if the measured vector is a vector that requires bad, Inserting a predetermined number of analysis vectors for the defective vector and performing a defect check from the first vector to the predetermined number of analysis vectors and then masking the defective vector and a predetermined number of analysis vectors for the defective vector A failure analysis and masking step, and a determination step of determining whether the measured vector is a normal vector, a continuous vector, or an analysis-free vector, or whether the measured vector is the n-th vector after the failure analysis and masking step, And if it is not the n-th vector, the input signal of the next vector is applied to the input pin and the output signal from the output pin is measured It characterized in that it includes a failure analysis method for a restart vector comprising the step of proceeding to said failure analysis and masking steps.

1 is a block diagram for explaining a defect inspection method of a semiconductor device.

2 is a flowchart for explaining a defect inspection method of a semiconductor device according to the present invention.

3 is a flowchart for explaining a failure analysis method for a continuity vector of a semiconductor device of the present invention.

4 is a flowchart illustrating a failure analysis method for a restart vector of a semiconductor device according to the present invention.

Hereinafter, a defect inspection and analysis method of a semiconductor device of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a flowchart for explaining a defect inspection method of a semiconductor device according to the present invention. First, an input signal of a first vector is applied to an input pin of a semiconductor device in a tester 30 shown in FIG. 1, The output signal is measured (operation 100). The tester compares the actual output signal of the first vector with the output signal of the inspection pattern to determine whether it is a defective vector (operation 110). If it is not a bad vector, the tester determines whether the vector is the n-th vector (last vector) (Step 120). If it is a defective vector, it is determined whether the tester is a restart vector (operation 130). The designer recognizes the inspection pattern of the semiconductor device in advance and stores this information in the tester. This restart vector is a vector that affects the failure of the next vector. If it is a restart vector, the tester masks the defective vector and proceeds to operation 100 (operation 140). Masking means to exclude this bad vector from the test pattern. If it is not a restart vector, it is a continue vector. Therefore, the defective vector does not affect the failure of the next vector. Therefore, the process proceeds to step 120 to continuously perform the test. If it is determined in operation 120, the tester applies an input signal of the next vector to the input pin of the semiconductor device, measures an output signal from the output pin, and proceeds to operation 110 (operation 150) . If it is determined in operation 120, the operation is terminated.

According to the defect inspection method of a semiconductor device of the present invention, if the failure of each vector affects the failure of the next vector, it is possible to continue the inspection according to the conventional method if the vector is divided into the restart vector and the continuity vector, , And if it is a restart vector, it affects the failure of the next vector. Therefore, the defective vector is masked and the inspection is restarted from the beginning.

3 is a flowchart for explaining a failure analysis method for a semiconductor device according to the present invention, and is a flowchart for explaining a method for analyzing a failure of a continuous vector.

First, the tester applies the input signal of the first vector to the input pin of the semiconductor device and measures the output signal from the output pin (operation 200). The tester compares the output signal with a desired output signal, and if it is the same, it is determined to be normal. Otherwise, it is determined that the output is defective (operation 210). If it is determined that the defective vector is a restart vector, the tester determines whether the defective vector is a restart vector (operation 220). If it is determined in step 210 that the defective vector is not defective, the tester determines whether the defective vector is the n-th vector (the last vector) (operation 240). If it is determined as a restart vector in operation 220, the tester masks the defective vector and proceeds to operation 240 in operation 230. If it is determined in operation 240, the tester applies the input signal of the next vector to the input pin of the semiconductor device, measures the output signal from the output pin, and proceeds to operation 210 step). If it is determined in operation 220 that the vector is not a restart vector, the tester determines whether the vector is a vector that needs to be analyzed (operation 260). Whether or not the vector is needed for analysis is still determined by the designer, just like the restart vector. If the analysis is required, the tester inserts the analysis vector between the defective vector of the inspection pattern and the next vector (step 270). This analysis vector consists of one or more vectors that the designer makes to identify the cause and location of the failure. If it is not the vector that needs analysis, proceed to step 240. If it is determined in operation 240, the tester applies the first vector and measures the vector in operation 280. The tester determines whether it is the n-th vector, and ends the operation if it is the n-th vector (Step 290). As a result of the determination in operation 290, if the vector is not the n-th vector, the tester measures the vector by applying the next vector, and proceeds to operation 290 (operation 300). In steps 280 to 300, an inspection pattern is newly inspected after inserting and masking the inspection pattern.

The failure analysis method of the continuity vector of the present invention is performed by distinguishing whether or not the vector is defective analysis. If it is defective and the vector is not continuous, it is determined whether or not the analysis is necessary. If analysis is necessary, If the failure vector is a bad restart vector, the bad vector is masked and the next vector is checked continuously.

4 is a flowchart for explaining a failure analysis method for a semiconductor device according to the present invention, and is a flowchart for explaining a failure analysis method of a restart vector.

First, the tester applies the input signal of the first vector to the input pin of the semiconductor device and measures the output signal from the output pin (operation 400). The tester determines whether the first vector is a defective vector (operation 410). If it is a defective vector, it is determined whether the tester is a restart vector (operation 420). If it is a restart vector, the tester determines whether the defective vector is a vector requiring analysis (operation 430). If the analysis is a required vector, the tester inserts the analysis vector between the defective vector and the next vector (operation 440). As described above, this analysis vector is made up of one or more vectors that the designer makes to identify the cause and location of the failure. After inserting the analysis vector, the tester applies the input signal of the first vector to the input pin of the semiconductor device and measures the output signal from the output pin (operation 450). Then, the tester determines whether this vector is the last analysis vector (operation 460). If not, the tester applies and measures the next vector (step 470). If it is the last analysis vector, the tester masks from the bad vector to the last analysis vector. If it is determined in step 410, 420, or 430 that the defective vector, the restart vector, or the vector that is not required to be analyzed, or after step 480, the tester determines whether the vector is the n-th vector (step 490). If the vector is not the n-th vector, the tester applies the next vector and measures it, and proceeds to operation 410 (operation 500). If it is an n-th vector, the tester ends the operation.

The failure analysis of the restart vector according to the present invention is performed by discriminating whether or not the vector is defective analysis. If it is defective and the restart vector is determined, it is determined whether or not the analysis is necessary, And performs the inspection from the first vector to the analysis vector and masks the defective vector and the analysis vector. And, if it is not bad and it is still a vector and it is not a vector that needs analysis, continue the inspection from the next vector.

That is, the flow charts of FIGS. 2, 3, and 4 are flow charts of the inspection program in the tester. The flowchart of FIG. 2 shows a method for performing a defect inspection, and the flowcharts of FIGS. 3 and 4 show a method for simultaneously performing a defect inspection and a defect analysis.

When a defect is detected after performing the defect inspection method of FIG. 2 for a semiconductor element, the defect inspection and analysis method of FIGS. 3 and 4 can be performed on a semiconductor element in which a defect has occurred, . The failure analysis methods of FIGS. 3 and 4 may be performed first, and the method of FIG. 4 may be performed, or the method of FIG. 4 may be performed first and the method of FIG. 3 may be performed.

In addition, since the present invention can be applied not only to an order circuit but also to a combination circuit, there is no restart vector in the case of a combination circuit. Therefore, if a defect inspection and analysis method for the continuity vector of FIG. 3 is used for defect analysis, Can be easily found.

Therefore, the defect inspection and analysis method of the semiconductor device of the present invention can simultaneously perform defect inspection and analysis.

Then, it is possible to eliminate the defect caused by the defect of the previous vector, and accurately identify the defect caused by the defect of the actual circuit.

Claims (4)

A semiconductor device having a predetermined number of input pins and output pins; And And a tester for discriminating defects by using inspection patterns from the first to n-th vectors of the semiconductor element, the method comprising the steps of: A measurement step of applying an input signal of the first vector to the predetermined number of input pins and measuring an output signal from the output pins; Masking the defective vector and proceeding to the first measurement step if the measured vector is a defective vector and a restart vector; And If the measured vector is not a bad vector but a continuous vector, it is determined whether the measured vector is the n-th vector. If the measured vector is not an n-th vector, And a second determination and inspection step of applying a voltage to the predetermined number of input pins, measuring an output signal from the output pins, and proceeding to the first determination and inspection step. 2. The method according to claim 1, wherein the continuity vector is a vector which does not affect the failure of the next vector. A semiconductor device having a predetermined number of input pins and output pins; And A semiconductor device having a tester for inspecting and analyzing defects by using a predetermined number of analysis vectors for each of inspection patterns from the first to n-th vectors of the semiconductor device and vectors requiring analysis at the time of defect occurrence of the vectors In the failure analysis method, A measurement step of applying an input signal of the first vector to the predetermined number of input pins and measuring an output signal from the output pins; Determining whether the measured vector is a defective vector; Determining whether the measured vector is an n < th > vector if it is determined that the measured vector is not a defective vector according to the determination step; And then proceeding to the determination step; A masking step of masking the defective vector and proceeding to the first inspection step if it is determined to be a defective vector and a restart vector as a result of the determination step; Determining whether the defective vector is a vector requiring analysis if the defective vector is a continuing vector as a result of the determining step; and inserting a predetermined number of analysis vectors for the defective vector after the defective vector, 1 < / RTI > inspection step, and if the analysis is not required, go to the first inspection step; And And a second inspection step of sequentially applying and measuring vectors from the first vector to the n-th vector in the case of the n-th vector as a result of the first inspection step. A semiconductor device having a predetermined number of input pins and output pins; And A semiconductor device having a tester for inspecting and analyzing defects by using a predetermined number of analysis vectors for each of inspection patterns from the first to n-th vectors of the semiconductor device and vectors requiring analysis at the time of defect occurrence of the vectors In the failure analysis method, A measurement step of applying an input signal of the first vector to the predetermined number of input pins and measuring an output signal from the output pins; Inserting a predetermined number of analysis vectors for the defective vector and performing a defect check from the first vector to the predetermined number of analysis vectors if the measured vector is a vector that requires defective, A bad analysis and masking step of masking a bad vector and a predetermined number of analysis vectors for the bad vector; And Determining whether the measured vector is a normal vector, a continuation vector, or an analysis-free vector, or whether the measured vector is the n-th vector after the failure analysis and masking step, and if the vector is an n-th vector, and if not, applying an input signal of the next vector to the input pin, measuring an output signal from the output pin, and proceeding to the failure analysis and masking step. .